Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
  • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
  • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/04—Speed or phase control by synchronisation signals

Definitions

• the present invention relates to the generation of a clock signal in an integrated circuit.
• the present invention applies in particular, but not exclusively to contactless chips, such as RFID chips (Radio-Frequency IDentification tag).
• RFID chips Radio-Frequency IDentification tag
• Such chips generally comprise modulated radio signal transmission and reception circuits for exchanging data with a reader, a power supply circuit for generating from the electromagnetic field generated by the reader a supply voltage of the integrated circuit. , a processing unit, and a non-volatile memory, for example of the EEPROM type.
• the transmit and receive circuits of the chip use a clock signal whose frequency must vary as little as possible in order to be able to decode the received data and to emit signals that can be decoded by a reception unit of a reader.
• this clock signal must be synchronized with that of the reader.
• the reader sends the chip a reference signal from which the chip adjusts the frequency of its clock signal.
• a local oscillator is generally used which produces a reference frequency from which the clock signal is generated.
• the oscillators are sensitive to their environment, and in particular to temperature variations.
• a contactless chip can be subjected to very variables.
• the internal temperature of a chip may vary significantly during a communication session with a reader.
• the reference frequency generated by the local oscillator can also vary during a communication session.
• the reference signal enabling the chip to determine its clock frequency is generally transmitted only once, at the beginning of a communication session with a reader. As a result, the chip does not have the ability to readjust its clock frequency several times during a session.
• the object of the present invention is to regulate a clock frequency based on a received signal.
• This objective is achieved by providing a method for generating a clock signal comprising the steps of:
• the method comprises steps of:
• the method comprises the steps of: Performing a second measurement of a characteristic of a first occurrence of the second event in the received signal,
• a measure of the characteristic of each new occurrence of the second event in the received signal is performed and compared with the second measurement, the first measure being corrected according to the result of the comparison.
• each event in the received signal is a pulse having two fronts
• the measurements are performed by counting the number of pulses of the first clock signal between the two fronts.
• the second clock signal is generated by dividing the frequency of the first clock signal by the first measurement.
• the first measurement is previously divided by a constant number before being used to generate the second clock signal.
• the correction of the first measurement is performed if the variation of the characteristic of the second event exceeds a certain threshold value.
• the correction of the first measurement is performed by incrementing or decrementing the first measurement of a fixed value according to whether the variation of the characteristic of the second event is increasing or decreasing.
• the invention also relates to a device for generating a clock signal comprising:
• measurement means for making a first measurement of a characteristic of a reference event in a received signal, using a first clock signal, and
• the device comprises:
• correction means for correcting the first measurement as a function of the variation of the characteristic of the second event, the second clock signal being generated as a function of the first corrected measurement.
• the measuring means performs a second measurement of the characteristic of a first occurrence of the second event in the received signal, and a third measurement of the characteristic of a new occurrence of the second event in the received signal
• the device comprising comparison means for making a comparison of the third measurement with the second measurement, the correction means correcting the first measurement according to the result of the comparison.
• the measurement means perform a measurement of the characteristic of each new occurrence of the second event in the received signal, the comparison means make a comparison of each new measurement with the second measurement, and the Correction means correct the first measurement at each comparison.
• the means for generating the second clock signal divide the frequency of the first clock signal by the first measurement.
• the means for generating the second clock signal first divide the first measurement by a constant number, the result of the division being used to generate the second clock signal.
• the correction means applies a correction to the first measurement if the variation of the characteristic of the second event exceeds a certain threshold value.
• the correction means apply a correction to the first measurement by incrementing or decrementing the first measurement of a fixed value according to whether the variation of the characteristic of the second event is increasing or decreasing.
• the invention also relates to an integrated circuit comprising a device as defined above.
• the integrated circuit comprises modulated radio-frequency transmission and reception circuits, a power supply circuit for generating from a received radio-frequency signal a supply voltage of the integrated circuit, a processing unit and a non-volatile memory.
• FIG. 2 represents in the form of blocks a circuit for generating a clock signal according to the invention
• Figs. 3A and 3B are flowcharts of frequency adjustment procedures of a clock signal according to the invention
• FIGS. 4A and 4B show in the form of timing diagrams the form of signals transmitted to a contactless chip
• FIG. 5A shows curves of variation of certain signals in a clock generation circuit having no regulation device
• FIG. 5B shows curves of variations of certain signals in the clock generation circuit illustrated in FIG. 2.
• FIG. 1 represents an integrated circuit TG such as a contactless chip, comprising a CPU processing unit coupled to an MEM memory.
• the processing unit communicates with an external reader RD coupled to an antenna 2, using an antenna 1 connected to a RFST radio frequency stage.
• the RFST stage is connected to a DEM demodulator and a MOD modulator.
• the demodulator is connected to a decoder DEC which provides the CPU processing data received and demodulated.
• the modulator modulates data provided by the processing unit and applies the modulated data to the RFST stage for transmission to the RD reader.
• the CPU processing unit is connected to the MEM memory by address and data buses, for transmitting an address AD to access and a word W to store or read in the memory at the address AD.
• the integrated circuit also comprises a clock signal generation circuit CKGEN providing a first clock signal SF0 which clock the decoder DEC and a second clock signal SFC which clock the modulator MOD.
• the transmission of data between the integrated circuit TG and the reader RD is for example carried out using a modulation ASK (Amplitude Shift Keying) or PSK (Phase Shift Keying).
• the DEM demodulator provides the decoder an RS signal whose shape corresponds to the envelope of the received signal.
• the decoder samples this signal using the first clock signal SFo to obtain a binary signal containing the received data.
• Figure 2 shows the clock signal generating circuit CKGEN.
• This circuit. comprises a local oscillator OSC and a first counter CPT1.
• the oscillator generates the first clock signal SF 0 of frequency Fo.
• the counter CPT1 receives the clock signal SF0 and the signal RS coming from the demodulator DEM.
• the output of the counter is connected to the input of a state machine SM which distributes the value of the counter in several registers including a register NEVT1.
• the register NEVT1 is connected to the input of a DIV divider whose output is connected to an NFC register.
• the circuit CKGEN comprises a second counter CPT2 receiving the clock signal SF0 and controlled by the value contained in the NFC register.
• the output of the counter CPT2 provides the SFC clock signal at the output of the CKGEN circuit.
• the first counter CPT1 counts the pulses of the signal SFo between a rising edge and a falling edge of the signal RS. For this purpose, it is initialized and triggered at each rising edge of the signal RS, and stopped at each falling edge of this signal. The value of the counter is therefore proportional to the duration of a pulse of the signal RS.
• the state machine SM loads the registers to which it is connected with the value of the counter CPT1 according to an expected order of the different events in the received frames, each event corresponding to a pulse.
• the value of the counter CPT1 is loaded by the state machine SM into the register NEVT1.
• the divisor DIV divides the value contained in this register by a constant factor R.
• the division result is stored in the NFC register.
• the counter CPT2 counts the pulses of the clock signal SF 0, and outputs the clock signal SFC which includes a pulse each time the counter has reached the value contained in the NFC register.
• the reference event EVT1 generally consists of a pulse having a predefined duration, which is transmitted only in a first frame of a communication session between a reader RD and the integrated circuit TG.
• the reference event is provided to allow the integrated circuit TG to generate a clock frequency FC having a value required by the reader RD to exchange data with the latter. It is therefore not possible to use new occurrences of the reference event in the signal received by the integrated circuit to reset the frequency of clock FC, in case of drift of the frequency Fo of the local oscillator OSC.
• the circuit CKGEN comprises two additional registers NEVT2 and NEVT20 connected to the state machine SM and to the inputs of a comparator C1.
• the output of the comparator is connected to an input of a correction circuit COR applying a correction to the value of the NFC register according to the result of the comparison.
• the two registers NEVT2 and NEVT20 receive from the state machine SM the value of the counter CPT1 when a second event EVT2 distinct from the first event appears in the received signal RS.
• the register NEVT20 receives the value of the counter CPT1 when a first occurrence of the second event appears in the received signal, while the register NEVT2 receives the value of the counter CPT1 when new occurrences of the second event appear in the received signal.
• the comparator C1 supplies the correction circuit COR with the difference between the values contained in the two registers NEVT2 and NEVT20.
• This difference is representative of a variation in the measurement of the duration of the second event. This duration is defined by the RD reader and is therefore assumed to be constant. Therefore, a variation of this measurement reveals a variation of the frequency Fo of the oscillator.
• the frequency FC of the clock signal SFC is adjusted several times during a communication session of the integrated circuit TG with a reader RD, even if the reference event EVT1 used for the determination of the frequency FC clock is transmitted only once.
• the correction circuit COR applies a correction to the value of the NFC register when the value received from the comparator exceeds a certain threshold.
• the correction applied by the circuit COR may consist in incrementing or decrementing the value of the register by a fixed value depending on whether the value supplied by the comparator C1 is positive or negative.
• the NFC register is incremented or decremented according to whether the variation of the characteristic of the second event EVT2 is increasing or decreasing.
• the correction circuit transfers the contents of the register NEVT2 into the register NEVT20 when it applies a correction to the contents of the NFC register.
• the CKGEN circuit comprises two additional additional NDO and ND00 registers connected to the state machine and to the inputs of a comparator C2.
• the output of the comparator C2 is connected to an input of the correction circuit COR.
• the two registers ND0 and ND00 receive from the state machine SM the value of the counter CPT1 when a third event distinct from the first two events appears in the received signal RS.
• the register ND00 receives the value of the counter CPT1 when a first occurrence of the third event appears in the received signal, while the register NDO receives the value of the counter CPT1 when new occurrences of the third event appear in the received signal.
• the correction circuit COR uses the output of the comparator C2 in a manner analogous to the output of the comparator C1 to correct the value stored in the NFC register.
• This arrangement makes it possible to adjust the FC frequency of the SFC clock signal even more frequently. In furthermore, it makes it possible to obtain better adjustment accuracy if one of the second and third events has a low occurrence frequency in the received signal, and the other event has insufficient time to obtain good accuracy.
• FIG. 3A represents a procedure that is executed upon reception by the integrated circuit TG of the first frame of a communication session between a reader and an integrated circuit. This procedure consists of the following successive steps:
• step 11 occurrence of the events EVT1, EVT2 and DO and loading of the duration of these events in the registers NEVT1, NEVT20 and ND00,
• Step 12 calculation of the value contained in the NFC register as a function of the duration NEVT1 of the event EVT1, and step 13: generation of the clock signal SFC at the frequency FC according to the contents of the NFC register.
• the flowchart of FIG. 3B represents a procedure that is executed on receipt of the second frame and each of the following frames transmitted by the reader RD to the integrated circuit TG during the session. This procedure consists of the following successive steps:
• step 21 occurrence of events EVT2 and DO and loading of the duration of these events in the registers NEVT2 and NDO,
• Step 22 calculating the difference A between the values contained in the registers NEVT2 and NEVT20, and the difference B between the values contained in the registers ND0 and ND00
• step 23 calculating a new value of the NFC register according to the previous value of the NFC register and the differences A and B, and
• step 24 generation of the SFC clock signal at the frequency FC according to the contents of the NFC register.
• Figs. 4A and 4B show the shape of a first frame and subsequent frames transmitted by a reader RD to the integrated circuit TG during a session.
• the first frame received by the integrated circuit comprises a header successively comprising:
• the following pulses correspond to the bits DO at 0 and D1 to 1 of the data transmitted in the frame.
• the following frames represented in FIG. 4B comprise a header comprising the same pulses as the first frame, except for the pulse corresponding to the first EVT1 event.
• the pulse with the longest duration is that corresponding to the first EVT1 event which is used to determine the clock frequency FC of the SFC output signal of the CKGEN circuit.
• the pulse corresponding to the third event OD used to adjust the frequency FC appears most frequently in the frames, but has the shortest duration of the three events.
• the state machine SM distributes the successive values of the counter CPT1 in the registers NEVT1, NEVT20, NEVT2, ND00 and ND0 according to the order of occurrence of the corresponding events in the frames received during a session.
• the NEVTl, NEVT20 and NDOO registers are filled in the first frame received during a session, while the NEVT2 and NDO registers are updated each subsequent frame received during the session.
• the state machine can also detect bits at 0 in the received data and load the counter value CPT1 into the NDO register.
• FIGS. 5A and 5B show evolution curves from the instant t0 of reception of a first frame, the following information:
• FIG. 5A shows that if the frequency Fo is not constant, while the content of the NFC register remains constant, the frequency FC substantially follows the variations of the frequency Fo, and leaves a tolerance zone delimited by high frequencies. FCM and low FCm.
• FIG. 5B shows the same signals as FIG. 5A, when the content of the NFC register is corrected by the correction circuit COR as a function of the drift of the frequency Fo determined by measuring the evolution of the duration of EVT2 events and / or DO. This figure shows that if such a correction is made, the FC frequency remains in the FCm-FCM tolerance zone.
• the decoding performed by the decoder DEC consists in counting the time between 2 fronts by means of the counter CPT1 clocked by the first clock signal SF 0. The number obtained is compared to NEVT2 / 2. The result of the comparison indicates whether it is a datum at 0 ( ⁇ NEVT2 / 2) or a datum at 1 (> NEVT2 / 2).
• the device according to the invention is susceptible of various variants.
• the invention is not limited to adjusting a clock frequency as a function of pulse duration measurements. It is possible to envisage a measurement of any other characteristic, such as, for example, a number of pulses between two particular events.
• the pulse duration measurements can be performed between two successive opposite fronts or in the same direction (between two rising edges or between two successive falling fronts). Neither is it necessary for the measurement of the first event and the first measure of the second event to be performed at the same time
• the measured events do not have to appear in the same signal.
• the correction applied to the first measure may consist in determining this measure without taking into account the previous value of this measure.
• the invention does not necessarily apply to contactless chips. It applies more generally to any system comprising transmitting and / or receiving circuits using a clock frequency determined from the received signal.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Synchronisation In Digital Transmission Systems (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=36293323

Family Applications (1)

Country Status (6)

Families Citing this family (1)

Family Cites Families (3)

• 2005
  • 2005-09-06 FR FR0509082A patent/FR2890465A1/fr not_active Withdrawn
• 2006
  • 2006-07-20 EP EP06778895A patent/EP1922834A1/de not_active Withdrawn
  • 2006-07-20 WO PCT/FR2006/001778 patent/WO2007028867A1/fr active Application Filing
  • 2006-07-20 JP JP2008529654A patent/JP2009507442A/ja active Pending
  • 2006-07-20 CN CN2006800327407A patent/CN101258705B/zh active Active
• 2008
  • 2008-03-03 US US12/041,449 patent/US7675341B2/en active Active

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events