EP1905068A2 - Technique destinee a reduire les non uniformites de siliciure par adaptation d'un profil dopant vertical - Google Patents

Technique destinee a reduire les non uniformites de siliciure par adaptation d'un profil dopant vertical

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Publication number
EP1905068A2
EP1905068A2 EP06770831A EP06770831A EP1905068A2 EP 1905068 A2 EP1905068 A2 EP 1905068A2 EP 06770831 A EP06770831 A EP 06770831A EP 06770831 A EP06770831 A EP 06770831A EP 1905068 A2 EP1905068 A2 EP 1905068A2
Authority
EP
European Patent Office
Prior art keywords
region
dopant
target depth
metal
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06770831A
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German (de)
English (en)
Inventor
Frank Wirbeleit
David Brown
Patrick Press
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Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
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Filing date
Publication date
Priority claimed from DE102005024911A external-priority patent/DE102005024911A1/de
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP1905068A2 publication Critical patent/EP1905068A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention relates to the field of fabrication of integrated circuits, and, more particularly, to semiconductor devices having metal-silicide portions on semiconductor regions to reduce the resistance of the semiconductor regions.
  • CD 3 critical dimension
  • Reducing this extension of the channel, commonly referred to as channel length, may significantly improve device performance with respect to fall and rise times of the transistor element due to the smaller capacitance between the gate electrode and the channel and due to the decreased resistance of the shorter channel.
  • the individual semiconductor devices such as field effect transistors, capacitors and the like, are primarily based on silicon, wherein the individual devices are connected by silicon lines and metal lines. While the resistivity of the metal lines may be improved by replacing the commonly used aluminum with, for example, copper and copper alloys, process engineers are confronted with a challenging task when an improvement in the electrical characteristics of silicon-containing semiconductor lines and semiconductor contact regions is required.
  • a semiconductor structure 100 includes a substrate 101, for example, a silicon substrate in which is formed a field effect transistor 110 of a specified conductivity type, such as an N-channel transistor or a P-channel transistor.
  • the transistor element 110 comprises an isolation structure 113 formed of an insulating material, such as silicon dioxide, silicon nitride and the like, which defines an active region 112 in the substrate 101.
  • a gate electrode 115 is formed over a gate insulation layer 118 that separates the gate electrode 115 from the active region 112.
  • Spacer elements 116 made of, for example, silicon dioxide or silicon nitride, are located at the sidewalk of the gate electrode 115.
  • source and dram regions 114 including respective extensions 114a are formed and exhibit an appropriate lateral dopant profile required to connect to a channel region 111, in which a conductive channel builds up between the drain and the source regions 114 upon application of an appropriate control voltage on the gate electrode 115.
  • the gate length of the transistor element 110 determines the channel length of the transistor 110 and therefore, as previously pointed out, significantly affects the electrical characteristics of the transistor element 110, wherein a reduced gate length and thus reduced overall dimensions of the transistor 110 will result in an increased resistance of the gate electrode 115 and contact areas 114b of the drain and source regions 114, although heavily doped, owing to the reduced area that is available for charge carrier transport.
  • a typical process flow for forming the semiconductor structure 100 may comprise the following steps. After the formation of the isolation structure 113 by well-known photolithographic etch and deposition techniques, implantation steps are performed to create a required vertical dopant profile in the active region 112. Subsequently, the gate insulation layer 118 is formed according to design requirements. Thereafter, the gate electrode 115 is formed by patterning, for instance, a polysilicon layer, by means of sophisticated photolithography and etching techniques. Then, a further implantation step for forming the source and drain extensions 114a within the source and drain regions 114 is performed and the spacer elements 116 may be formed by deposition and anisotropic etching techniques. The spacer element 116 may be used as an implantation mask for a subsequent implantation process in which a dopant is implanted into the active region 112 to form the source and drain regions 114, thereby creating the required high dopant concentrations in these regions.
  • the dopant concentration varies in Figure Ia in the horizontal direction, i.e., in the length direction of the gate electrode 115, as well as in the vertical direction, which will hereinafter be referred to as depth direction x, indicated by the arrow.
  • the dopant profile of the source and drain regions 114 is depicted as a " region having a sharp boundary, in reality the dopant profile varies continuously due to the moderately non-localized nature of the implantation process in the depth direction x and the subsequent annealing steps that are performed for activating the implanted atoms and for curing the crystalline damage caused by the implantation step.
  • the dopant profile has to be selected in conformity with certain parameters of the transistor element 110.
  • the peak concentration in the depth direction x may be located near the surface, i.e., the contact area 114b, and may significantly drop with increasing depth.
  • Figure Ib schematically shows the vertical dopant profile in the drain and source regions 114 as it may typically be encountered in conventional transistor elements having a gate length 1151 of approximately 100 nm and even less.
  • the horizontal axis represents the extension along the depth direction x, wherein for instance in Figure Ia a specified depth x s is illustrated as a dashed line.
  • the vertical axis represents the dopant concentration in a logarithmic scale, wherein the type of dopants in the drain and source regions 114 is determined by the type of transistor element that the transistor 100 represents.
  • a very high dopant concentration may be present at or near the surface 114b, which may significantly drop with increasing depth so as to yield a concentration at the specified depth x s that may be significantly less.
  • Figure Ic schematically shows the semiconductor structure 100 in a further advanced manufacturing stage.
  • metal suicide regions 117 are formed within the drain and source regions 114 and a metal suicide region 119 is formed in the gate electrode 115.
  • the metal suicide regions 117, 119 are formed from a refractory metal, such as cobalt, nickel, titanium, platinum and the like, or combinations of two or more appropriate metals.
  • a refractory metal such as cobalt, nickel, titanium, platinum and the like, or combinations of two or more appropriate metals.
  • metal silicide regions 117, 119 typically one or more metal layers of specified thickness are conformally deposited by any appropriate deposition technique, such as physical vapor deposition, chemical vapor deposition and the like, wherein for instance an initial layer thickness may be selected to obtain a vertical extension of the silicide regions 117 in accordance with device requirements.
  • a thickness of the region 119 is, however, coupled to a specified thickness of the silicide regions 117, since frequently the regions 117 and 119 are formed in a common manufacturing process.
  • a more complex manufacturing scheme may be used to substantially decouple the formation of the regions 117, 119. It may now be assumed that a design thickness of the metal silicide region 117 is given by the depth x s . Based on the target depth x s and on the basis of the well-known reaction behavior of the refractory metal or metals under consideration with the underlying silicon, in principle the finally obtained tnicKness or me metal suicide regions i iv may be adjusted by correspondingly controlling process parameters, such as the initial layer thickness, temperature and duration of a subsequent heating process so as to initiate the diffusion of the refractory metal or metals into the silicon, thereby generating the metal suicide compound.
  • the metal silicide regions 117 may have, however, a certain roughness, indicated as 117a, the characteristics of which may significantly depend on device and process specifics. For instance, in some process regimes, P-channel transistors having a structure similar to the transistor 110 may exhibit a more pronounced roughness 117a for a nickel silicide compared to N-channel transistors formed within the same semiconductor structure 100. On the other hand, for nickel platinum silicide, the roughness 117a may be more pronounced for N-channel transistors compared to P-channel transistors.
  • the non-uniformity of the metal silicide regions 117 i.e., the roughness 117a, which may also vary between different transistor types in the same structure
  • a degradation of electrical parameters of the semiconductor structure 100 may be observed due to pronounced parameter variation between different devices and due to, for instance, increased leakage currents at the drain and source regions 114.
  • non- uniformities of the metal silicide regions 117 may negatively affect the performance of future device generations having even more tightly set process tolerances.
  • the present invention is directed to a technique that enables the formation of metal silicide regions in highly doped semiconductor regions containing silicon, wherein the roughness of the metal silicide region may significantly be reduced to provide a more precisely defined interface with the surrounding semiconductor region.
  • a vertical dopant concentration within the silicon-containing semiconductor region may be modified to provide, compared to conventional source and drain regions, an increased dopant concentration at or near a depth at which the interface of the metal silicide region is to be formed.
  • the increased dopant concentration may significantly modify the diffusivity of the metal during the formation of the metal silicide region.
  • a method comprises identifying a target depth of a metal silicide region to be formed in a silicon-containing semiconductor region which is formed above the substrate.
  • the method further comprises forming a dopant profile in the silicon-containing semiconductor region along a depth direction of the silicon-containing semiconductor region on the basis of the targef'depth to obtain a local maximum of a dopant concentration in the neighborhood of the target depth.
  • the metal suicide region is formed on the basis of the target depth.
  • a method comprises identifying a first target depth for a metal suicide region for a drain and source region of a first specified transistor type that is to be formed on one or more substrates.
  • the method further comprises forming the drain and source regions of the first specified transistor type on one or more substrates with a dopant profile on the basis of the first target depth, wherein the dopant profile is adjusted with respect to a depth direction of the one or more substrates, so as to obtain, for increasing depth, an increasing dopant concentration when approaching the first target depth.
  • the metal suicide region is formed in the drain and source regions of the first specified transistor type on the basis of the first target depth.
  • Figure I schematically shows a cross-sectional view of a conventional transistor prior to the formation of a metal silicide region
  • Figure Ib represents a graph which schematically illustrates a dopant profile in the depth direction of the conventional transistor shown in Figure Ia;
  • Figure Ic schematically shows a cross-sectional view of the transistor of Figure 1 after the formation of metal silicide regions according to a conventional technique
  • Figures 2a-2b represent graphs for illustrating an exemplary dependency of the diffusivity of a refractory metal with respect to the penetration depth in the presence of an exemplary conventional dopant concentration ( Figure 2a) and an illustrative example of a dopant concentration according to illustrative embodiments of the present invention
  • FIGS. 2c-2f schematically illustrate cross-sectional views of a transistor element during various manufacturing stages in accordance with illustrative embodiments of the present invention
  • Figure 3 schematically shows a cross-sectional view of a semiconductor device comprising two transistor elements with different target depths for forming metal silicide regions in accordance with illustrative embodiments of the present invention.
  • Figure 4 schematically shows a cross-sectional view of a transistor element during fabrication, wherein a dopant concentration is modified in accordance with illustrative embodiments of the present invention on the basis of epitaxial silicon deposition. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to
  • the present invention is based on the concept that the diffusivity of refractory metal within a I doped semiconductor region may be influenced by the dopant profile within the semiconductor region.
  • the dopant profile of drain and source regions of transistors formed on the basis of silicon the kinematic behavior during a chemical reaction for forming metal suicide regions in the drain and source regions may be influenced to obtain more precisely defined interfaces between the metal suicide region and the semiconductor region, thereby reducing any deleterious effects that may be caused by metal suicide interface roughness, as is described with reference to Figure Ic.
  • the diffusivity of refractory metal atoms within a substantially crystalline semiconductor region is significantly affected by the presence of dopants, in particular when the dopants and the refractory metal atoms may exhibit a
  • diffusivity may be understood as an averaged random distance an atom may move within the semiconductor crystal at a specified temperature, for example, during the formation of a metal suicide in a crystalline silicon region where reaction kinetics significantly depend on the type of metal used and on the temperature at which the chemical reaction is initiated.
  • the reaction speed for forming metal silicide may, however, be significantly influenced by the additional dopants, since the diffusion of the dopants and of the refractory metal atoms may be based on substantially the same crystal-specific mechanisms, in particular when the refractory metal and the dopant material may have a similar diffusion behavior within silicon.
  • curve A may qualitatively represent a typical conventional dopant concentration with respect to a depth direction, indicated as x and plotted as the horizontal axis.
  • the dopant concentration at a zero depth i.e., the surface of a drain or source region
  • the dopant concentration at a zero depth is moderately high, such as 10 19 dopant atoms per cubic centimeter, which may drop significantly with increasing depth, so that a corresponding dopant concentration at a specified depth x s indicated by curve C, may be some orders of magnitude less than at
  • the depth x s may indicate a target depth for an interface between metal silicide and silicon of the drain or source region.
  • Curve B in Figure 2a may qualitatively represent a corresponding diffusivity of a refractory metal within silicon for any given process conditions during a silicidation process.
  • curve B may schematically represent the diffusion speed of nickel for a specified process temperature during the formation of a nickel silicide region in a highly doped source or drain region. Due to the presence of a high amount of dopant atoms at the surface, i.e., depth 0, the initial diffusivity of the metal atoms may be moderately low, wherein it should be appreciated that certain fluctuations of the diffusion behavior of the metal atoms may be present at depth 0, which may be caused by any surface irregularities, and the like.
  • the chemical reaction will also progress at a moderate speed, wherein any initially present fluctuations of the reaction front are driven into the material, i.e., along the depth direction x, with substantially the same moderate reaction speed.
  • the concentration of the dopants may significantly drop, thereby resulting in a corresponding significant increase of the diffusivity of the metal atoms so that any fluctuations initially present in the reaction front may now be "amplified” due to the significantly increased reaction speed. Consequently, at the depth x s , a significant roughness of the corresponding metal silicide front may have built up due to this "amplification effect" caused by the drastically increased reaction speed.
  • a modified dopant concentration will be established to obtain an increased dopant concentration at or at least in the vicinity of the target depth x s compared to the dopant concentration as shown in Figure 2a, thereby also modifying the reaction behavior during the silicidation process, which may result in a significantly reduced roughness of the metal silicide front.
  • Figure 2b schematically shows a graph depicting a modified dopant concentration within a silicon- containing semiconductor region with respect to the depth direction x and a corresponding difference in diffusivity of a refractory metal that may be achieved due to the modified dopant concentration.
  • curve D represents the modified dopant concentration within a drain or source region, wherein an increased dopant concentration is centered around the target depth x s .
  • the notion "increased” in this respect is to be understood that, at least at the target depth x s , an increase of the dopant concentration is present, when the target depth x s is approached from the left, i.e., with increasing depth so that at least within a certain neighborhood of x s , the dopant concentration increases with increasing depth.
  • a local maximum of the dopant concentration with respect to the depth direction x is located at or in the vicinity of the target depth x s .
  • the notion “in the vicinity” or “near” is to be understood that a distance of the local maximum to the target depth x s is less than a distance of the local maximum to the location representing the depth 0, where a maximum dopant concentration may prevail in conventional devices.
  • the notion “near” or “in the vicinity” is meant to describe a depth of approximately 80-120% with the target depth being located at 100%.
  • the actual local maximum may be located at a depth x m> indicated by arrow F, wherein this local maximum is located in the vicinity of the target depth x s since a distance of the local maximum to the target depth x s is significantly less compared to the distance of the target depth x s from the surface portion, i.e., the depth 0.
  • Curve E schematically represents the corresponding reaction speed with respect to a dopant concentration as represented for instance by curve D, wherein qualitatively a moderately low reaction speed is achieved, which even drops upon the respective increase of the dopant concentration, due to reduced diffusivity of the refractory metal atoms. Consequently, any initial fluctuations of the metal suicide front may not be substantially “amplified” and may even be reduced due to a "smoothing" effect of the reduced reaction speed. Thus, the metal suicide front may exhibit a reduced roughness and thus a more well-defined interface to the remaining silicon region at the target depth x s .
  • the dopant concentration and the diffusivity D, E are of illustrative nature only and other dopant profiles may be created in accordance with the present invention.
  • curves G and H schematically show corresponding dopant profiles in the depth direction that may also be appropriate for forming a metal suicide interface in a more localized manner.
  • the dopant concentrations shown in Figure 2b may refer to a single dopant species having a specified conductivity type so that a corresponding profile is substantially determined by this single dopant species.
  • an N-channel transistor may have heavily N-doped drain and source regions with only a negligible amount of counter dopants in the vicinity of the target depth x s , the effect of which on the dopant profiles may also be negligible, at least in the vicinity of the target depth x s .
  • the curves D, G, H may represent "accumulated" dopant concentration contemplating two or more different ion species, which may have the same or different conductivity types.
  • the high concentration at the target depth x s may be achieved by providing a certain amount of doping and by counter doping the area around the target depth x s so as to achieve a moderately low effective dopant concentration with respect to the electrical behavior, while still having an increase ⁇ dopant concentration with respect to the actual number of dopant atoms per volume unit and thus with respect to the effect on the diffusivity of any metal used for the formation of a metal suicide region.
  • dopant concentration is to be understood as the latter meaning.
  • Figure 2c schematically shows a semiconductor device 200 comprising a substrate 201, which may represent any appropriate substrate for the formation of silicon-based semiconductor elements.
  • the substrate 201 may represent a bulk silicon substrate having formed on an upper portion thereof a crystalline silicon layer.
  • the substrate 201 may represent an SOI-type (silicon on insulator) substrate having formed above an insulating layer (not shown) a silicon-containing semiconductor layer.
  • the semiconductor device 200 may further comprise a transistor element 210 including an isolation structure 213 formed within the substrate 201, i.e., within a silicon-containing semiconductor layer, so as to define an active region 212.
  • a channel region 211 is formed below the gate insulation layer 218 and laterally separates semiconductor regions in which deep drain and source regions are to be formed.
  • extension regions 214a are formed adjacent to the gate electrode 215, which may have formed on sidewalls thereof offset spacers 216a.
  • the arrow x indicates a depth direction x, wherein the depth direction x is substantially orthogonal with respect to an initial surface of the substrate 201.
  • the depth direction x is well defined, even for any surface topology created above the substrate 201 during the manufacturing process of the device 200, as for instance the back side of the substrate 201 may be used to define the orthogonality of the depth direction x.
  • the sign of the depth direction x as indicated by the arrow it is to be understood that an increasing depth is considered as starting from a surface portion, such as the portion 214b with value 0 and directed into the substrate 201. Consequently, a target depth x s may be defined as the distance of the initial surface 214b and a desired position of an interface of a metal silicide region to be formed adjacent to the gate electrode 215.
  • the "origin" of the depth direction x may be located above the surface 214b, when semiconductor devices 200 are considered, requiring the formation of selectively epitaxially grown source and drain regions, as will be described in more detail with reference to Figure 4 later on.
  • a typical process flow for forming the semiconductor device 200 as shown in Figure 2c may comprise the following processes.
  • the transistor 210 to be formed in and on the active region 212 may represent a specified transistor type, such as an N-channel transistor or a P-channel transistor having specified transistor dimensions, such as a gate length, a gate width, a specified thickness of the gate insulation layer 218 and the like.
  • the target depth x s is selected to obtain the desired decrease of the overall sheet resistivity of the surface portion 214b.
  • the sheet resistivity and also the overall contact resistance of the drain and source regions to be formed in the transistor element 210 may significantly depend on the type of refractory metal used for forming the metal silicide region and the target depth x s .
  • the manufacturing processes for the device 200 are adapted on the basis of the target depth x s so as to obtain a modified dopant profile in the depth direction x, as is for instance described with reference to Figure 2b.
  • the formation of the device 200 may thus comprise any processes for forming the isolation structure 213 and the gate electrode 215 including the gate insulation layer 218 and the offset spacer 216a in accordance with well-established process techniques, as are also described with reference to Figure Ia.
  • an ion implantation process 220 may be performed to create a dopant concentration required for the formation of the extension regions 214a.
  • a rapid thermal anneal process may be performed to activate the dopants within the region 214a and also recrystallize implantation- induced damage.
  • the anneal procedure may be performed in a later stage after the formation of deep drain and source regions.
  • appropriate spacer elements may be formed by well-established deposition and anisotropic etch techniques.
  • Figure 2d schematically shows the semiconductor device 200 after the formation of spacer elements 216, which act as implantation masks during an ion implantation process 221 for forming deep drain and source regions 214.
  • the ion implantation 221 may be performed as a single implantation step, in which implantation parameters, such as implantation energy and dose are controlled on the basis of the target depth x s .
  • the average penetration depth of the ion implantation 221 with respect to the dopant species used in this implantation process may be determined such that an increased dopant concentration is obtained in the vicinity of the target depth x s .
  • a corresponding appropriate implantation energy for the dopant species under consideration may readily be determined on the basis of well-established simulation calculations.
  • the implantation process 221 may comprise two or more implantation steps so as to modify the vertical dopant profile in the manner as described above.
  • an additional implantation step may be performed which is designed to modify the preceding or subsequent implantation for the formation of the deep drain and source regions 214, thereby creating the desired increased dopant concentration at or in the vicinity of the target depth x s .
  • an additional implantation step may be performed on the basis of a different dopant species, which may have the same or a different conductivity type compared to the dopant species used for the preceding or subsequent implantation step for actually defining the drain and source regions 214.
  • a dopant species may be used for the formation of the deep drain and source regions 214 that exhibits a significantly different diffusivity compared to the refractory metal, which may be used subsequently in the formation of metal suicide regions in the drain and source regions 214.
  • this dopant species may have a reduced effect on the diffusivity of the refractory metal so that the "amplification" effect may be somewhat less pronounced wherein, nevertheless, the introduction of a second dopant species having a more pronounced effect on the diffusivity of the refractory metal, i.e., having a similar diffusivity as the refractory metal, may even further enhance the smoothing effect of the increased dopant concentration at or in the vicinity of the target depth x s .
  • the second dopant species may differ in its conductivity type so as to act as a counter dopant, thereby reducing the "electrically effective" dopant concentration, while on the other hand increasing the actual dopant concentration, which acts as a reaction decelerating material.
  • the ion implantation 221 may De ⁇ esigne ⁇ to ODtam a mgn ⁇ opant concentration at or near the target depth x s so that, for a given refractory metal or metals to be used in a subsequent silicidation process and given process conditions, the ion implantation 221 may be considered as a "barrier" implantation with respect to the subsequent suicide formation, since the reaction front is significantly "slowed down.”
  • the device 200 may be annealed to substantially activate the dopants incorporated during the implantation sequence 221 and possibly by the implantation 220 ( Figure 2c), and also to cure crystalline damage caused by the implantation 221 and 220.
  • Figure 2e schematically shows the semiconductor device 200 in a further advanced manufacturing stage.
  • a layer of refractory metal 222 is conformally formed on the device 200.
  • the layer 222 of refractory metal may be comprised of one or more metals, such as nickel, cobalt, titanium, platinum, tungsten and the like, wherein the layer 222 may be comprised of two or more sub-layers if different refractory metals are applied, or the layer 222 may be provided as a single layer formed from a single refractory metal or formed of a compound of two or more different refractory metals.
  • the layer 222 may be formed on the basis of well-established deposition techniques, such as sputter deposition, chemical vapor deposition (CVD) and the like, wherein a thickness of the layer 222 is controlled on the basis of the target depth x s .
  • CVD chemical vapor deposition
  • the thickness of the layer 222 is sufficient to allow the formation of metal suicide down to the target depth x s .
  • Corresponding data with respect to the silicon "consumption" during a silicidation process with one or more refractory metals of interest may be obtained on the basis of test runs, experience, and the like.
  • the device 200 is subjected to a heat treatment under specified conditions, that is, a specified temperature and duration, so as to initiate the diffusion and thus the reaction of the refractory metal of the layer 222 with silicon in the regions 214 and in the gate electrode 215.
  • a heat treatment under specified conditions, that is, a specified temperature and duration, so as to initiate the diffusion and thus the reaction of the refractory metal of the layer 222 with silicon in the regions 214 and in the gate electrode 215.
  • the formation of metal suicide in the gate electrode 215 maybe decoupled from a corresponding process for forming metal suicide in the drain and source regions 214.
  • a cap layer (not shown) may be provided on top of the gate electrode 215 so that the gate electrode 215 is protected during a subsequent silicidation process.
  • the cap layer may be removed and a further layer of refractory metal may be deposited and a further chemical reaction may be initiated, in which substantially the gate electrode 215 is affected, while a reaction in the drain and source regions 214 may substantially be reduced due to previously formed metal suicide and due to the modified dopant concentration, which may significantly slow down a further penetration of the metal suicide front beyond the target depth x s .
  • the gate electrode 215 may receive a different metal suicide, wherein the formation and thus the dimensions of the respective metal suicide may substantially be decoupled from the corresponding metal suicide regions in the drain and source regions 214.
  • cobalt may require a two-step heat treatment with an intermediate selective etch step for removing non-reacted cobalt so as to transform the cobalt suicide from a high ohmic phase into a low ohmic phase.
  • a single heat treatment may be appropriate, as is for instance the case for nickel, nickel platinum and the like.
  • metal from the layer 222 diffuses into the region 214 wherein, due to the modified ddparit" pfome in me ⁇ eptn ⁇ irecuon x, a silicidation front of improved uniformity may form, thereby significantly reducing any roughness of an interface between metal suicide and semiconductor material.
  • Figure 2f schematically shows the semiconductor device 200 after the completion of the above- described process sequence.
  • the device 200 comprises a metal suicide region 219 formed in the gate electrode 215 and metal suicide regions 217 within the deep drain and source regions 214.
  • an interface 217a is substantially located at or in the vicinity of the target depth x s wherein the corresponding roughness is, at least in substantially horizontal portions, significantly reduced compared to prior art techniques.
  • the modification of the dopant profile may be adapted in accordance with a desired target depth x s for a specific transistor type.
  • a desired target depth x s for a specific transistor type.
  • P-type and N-type transistors usually commonly formed in CMOS devices may exhibit a different behavior with respect to the formation of a suicide region.
  • a common target depth x s may be selected for both transistor types, wherein the respective modified dopant profiles may result in an increased uniformity of the formation of corresponding metal suicide regions.
  • different target depths x s or different transistor types may be considered appropriate and the implantation sequence for forming the modified dopant profile may be performed differently for the various different transistor types, as will be described next.
  • Figure 3 schematically illustrates a semiconductor device 300 having formed therein two different types of transistors 310 and 350, which may require a metal suicide region having a different target depth x s and y s , respectively.
  • the transistor 310 may comprise a deep drain and source region 314 and corresponding extension regions 314a, wherein a dopant profile along the depth direction may be modified as is previously discussed with reference to Figures 2b-2f. That is, the dopant concentration of the drain and source regions 314 is increased at the target depth x s .
  • the transistor 310 may be covered by a mask, such as a resist mask 323, to protect the transistor 310 during an implantation process 324 that is configured to form corresponding deep drain and source regions in the transistor 350 with a dopant profile having an increased dopant concentration at or in the vicinity of the target depth y s .
  • a mask such as a resist mask 323, to protect the transistor 310 during an implantation process 324 that is configured to form corresponding deep drain and source regions in the transistor 350 with a dopant profile having an increased dopant concentration at or in the vicinity of the target depth y s .
  • the same criteria apply as previously described with reference to the implantation 221 ( Figure 2d).
  • corresponding anneal cycles may be performed and the further processing may be continued as is also described with reference to Figure 2e. That is, a layer of refractory metal may be deposited with a thickness that is sufficient to consume silicon at least down to the target depth y s .
  • a common silicidation process may be performed, while in particular the modified dopant profile in the transistor 310, having the smaller target depth x s , substantially maintains the suicide front at or in the vicinity of x s , while the suicide front in the second transistor 350 may progress down to the target depth y s . Consequently/ a liig ⁇ ief " degree ot process flexibility in the formation of metal suicide regions for different transistor types is provided without additional process complexity, since the formation of the resist mask 323 is a standard procedure in the conventional process flow, when different types of transistors are required.
  • FIG. 4 schematically shows a semiconductor device 400 having formed thereon a transistor element 410, in which at least a portion of dopants is introduced by deposition or diffusion.
  • the transistor 410 comprises a gate electrode 415 having formed thereon spacer elements 416 adjacent to which are formed epitaxially grown silicon-containing semiconductor regions 424.
  • a target depth x s is shown, at which an interface of a metal suicide region has to be formed. It has to be appreciated that the target depth x s may also be located within an active region 412 that is formed within a substrate 401 prior to the formation of the regions 424.
  • the transistor 410 may be formed in accordance with the process techniques previously described with reference to Figure Ia and 2c-2f, wherein, prior to the formation of deep drain and source regions, the regions 424 may be formed by well-established selective epitaxial growth techniques, in which a specific dopant species may be added to the deposition atmosphere to provide the regions 424 as doped regions.
  • a desired vertical dopant profile may be adjusted. For example, since the deposition rate is well known for a given deposition recipe, the addition of the dopant precursor may be controlled on the basis of the target depth x s .
  • a highly localized concentration peak may be created with a specified dopant species at the target depth x s .
  • a corresponding burst of the dopant precursor may be generated in the deposition atmosphere of the selective epitaxial growth process, when the target depth x s is reached.
  • the process parameters may be correspondingly adjusted in order to appropriately reduce the deposition rate, at least during the deposition of the material "in the vicinity" of the target depth x s .
  • a substantially uniform dopant concentration may be produced within the epitaxially grown regions 424 and the required modification of the dopant profile in the depth direction may be obtained by a specifically designed ion implantation process, as is also described with reference to Figure 2d when referring to the ion implantation 221.
  • a precise location of an increased dopant concentration, i.e., of the target depth x s may have to be formed within the active region 412.
  • the region 412 may be recessed adjacent to the spacer elements 416 by any appropriate technique, such as isotropic or anisotropic etching.
  • an oxidation process may be performed in a highly controllable manner and the silicon dioxide may be removed by well-established highly selective and well-controllable wet chemical etch techniques, thereby forming a recess 424a in a highly controllable fashion. Thereafter, the epitaxial growth process for forming the regions 424 may be performed in the same manner as described above, wherein now the target depth x s may be located within the recess 424a, thereby allowing a highly localized dopant concentration peak with a desired dopant species.
  • optional further implantation processes may be performed to form deep drain and source regions having a vertical extension as required by device requirements.
  • An anneal process may be performed to activate the dopants introduced by the optional ion implantation step. It should be appreciated that additional implantation processes for forming the deep drain and source regions may be omitted when the recesses 424a are formed and the dopant pitrtile may substantially oe completely established on the basis of controlling the dopant precursor concentration in the selective epitaxial deposition atmosphere. In this case, the anneal process may be omitted since the dopant atoms are typically placed at lattice sites.
  • the spacer 416 may be removed by well- established highly selective etch techniques and then a corresponding implantation sequence may be performed to form extension regions adjacent to the gate electrode 415. Thereafter, further spacer elements, such as the spacers 416, may be formed and metal suicide regions may be formed in a similar way as is previously described with reference to Figure 2f.
  • the highly localized increased dopant concentration at or in the vicinity of the target depth x s provides an enhanced "localization" of the metal suicide interface, thereby enhancing the overall characteristics of the transistor 410.
  • the "barrier" effect of the concentration peak may be adjusted to be extremely pronounced substantially without significantly affecting the overall "electric" dopant profile.
  • the present invention provides an enhanced technique for the formation of metal suicides having reduced non-uniformities at an interface to the remaining semiconductor region, thereby improving the performance of transistor elements.
  • the improved metal suicide characteristics may be achieved by modifying the vertical dopant profile within the deep drain and source regions, wherein an increased dopant concentration is generated at or in the vicinity of a target depth for the metal suicide interface, which may form a "barrier" dopant concentration.
  • the barrier concentration may significantly affect the diffusivity and thus the reaction speed during the metal suicide formation process.
  • the barrier dopant concentration may be formed by a specifically designed implantation sequence, which may include one or more implantation steps, and/or by the introduction of dopants on the basis of an epitaxial deposition process.
  • the dopant concentration affecting the metal diffusivity may be decoupled, at least to a certain degree, from the electrically effective dopant concentration, thereby providing enhanced flexibility in designing the barrier concentration substantially independently from the electric transistor performance.

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Abstract

Par modification de la concentration de dopant vertical dans des zones sources et de drainage profondes, le comportement de réaction durant la formation de zones en siliciure métallique (217) peut être contrôlé. Dans ce but, une concentration accrue de dopant est formée autour d'une profondeur cible (Xs) pour l'interface de siliciure métallique, réduisant ainsi les vitesses de réaction et améliorant ainsi l'uniformité de l'interface en siliciure métallique obtenue.
EP06770831A 2005-05-31 2006-05-23 Technique destinee a reduire les non uniformites de siliciure par adaptation d'un profil dopant vertical Withdrawn EP1905068A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102005024911A DE102005024911A1 (de) 2005-05-31 2005-05-31 Technik zur Reduzierung der Siliziumungleichförmigkeiten durch Anpassen eines vertikalen Dotierprofiles
US11/379,079 US20060270202A1 (en) 2005-05-31 2006-04-18 Technique for reducing silicide non-uniformities by adapting a vertical dopant profile
PCT/US2006/019722 WO2006130375A2 (fr) 2005-05-31 2006-05-23 Technique destinee a reduire les non uniformites de siliciure par adaptation d'un profil dopant vertical

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CN110233106B (zh) * 2018-03-05 2022-10-25 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
KR102481414B1 (ko) * 2018-07-05 2022-12-23 어플라이드 머티어리얼스, 인코포레이티드 실리사이드 막 핵생성

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JP3014030B2 (ja) * 1995-05-31 2000-02-28 日本電気株式会社 半導体装置の製造方法
US6037232A (en) * 1997-09-15 2000-03-14 Advanced Micro Devices Semiconductor device having elevated silicidation layer and process for fabrication thereof
US20020031909A1 (en) * 2000-05-11 2002-03-14 Cyril Cabral Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets
US6555880B2 (en) * 2001-06-07 2003-04-29 International Business Machines Corporation Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
US6858506B2 (en) * 2002-08-08 2005-02-22 Macronix International Co., Ltd. Method for fabricating locally strained channel
US6902991B2 (en) * 2002-10-24 2005-06-07 Advanced Micro Devices, Inc. Semiconductor device having a thick strained silicon layer and method of its formation
JP3840198B2 (ja) * 2003-04-28 2006-11-01 株式会社東芝 半導体装置およびその製造方法

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KR20080019656A (ko) 2008-03-04
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