EP1898353A2 - Rahmeninterpolationsschaltung, Rahmeninterpolationsverfahren und Anzeigevorrichtung - Google Patents

Rahmeninterpolationsschaltung, Rahmeninterpolationsverfahren und Anzeigevorrichtung Download PDF

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Publication number
EP1898353A2
EP1898353A2 EP20070016752 EP07016752A EP1898353A2 EP 1898353 A2 EP1898353 A2 EP 1898353A2 EP 20070016752 EP20070016752 EP 20070016752 EP 07016752 A EP07016752 A EP 07016752A EP 1898353 A2 EP1898353 A2 EP 1898353A2
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EP
European Patent Office
Prior art keywords
motion vectors
frame
vector
block
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP20070016752
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English (en)
French (fr)
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EP1898353A3 (de
Inventor
Hiroshi Yoshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP1898353A2 publication Critical patent/EP1898353A2/de
Publication of EP1898353A3 publication Critical patent/EP1898353A3/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformations in the plane of the image
    • G06T3/40—Scaling of whole images or parts thereof, e.g. expanding or contracting
    • G06T3/4007—Scaling of whole images or parts thereof, e.g. expanding or contracting based on interpolation, e.g. bilinear interpolation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/513—Processing of motion vectors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/577—Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/80—Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/012—Conversion between an interlaced and a progressive signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
    • H04N7/0132—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0135—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes
    • H04N7/014—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes involving the use of motion vectors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0261—Improving the quality of display appearance in the context of movement of objects on the screen or movement of the observer relative to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G09G2320/106—Determination of movement vectors or equivalent parameters within the image
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers

Definitions

  • One embodiment of the invention relates to a frame interpolating circuit and a frame interpolating method which detect and use a motion vector, and a display apparatus using the frame interpolating circuit and the frame interpolating method.
  • Patent Document 1 Jpn. Pat. Appln. KOKAI Publication No. 06-153167 ) discloses a motion vector detecting circuit which removes an isolated motion vector to prevent the image from being broken in the above case.
  • An object of the present invention is to provide a frame interpolating circuit and a frame interpolating method which can correct an assembly having vectors which are largely different from motion vectors of a peripheral block.
  • An embodiment of the present invention provides a frame interpolating circuit and a frame interpolating method which can correct an assembly having vectors which are considerably different from motion vectors of a peripheral block.
  • FIG. 1 is a block diagram showing an example of a configuration of a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 2 is a block diagram showing an example of a configuration of a motion vector detecting unit of a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 3 is a diagram for explaining an example of uncorrected motion vectors and corrected motion vectors in a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 4 is a flow chart showing an example of a vector correcting process which refers only to an upper vector in a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 1 is a block diagram showing an example of a configuration of a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 2 is a block diagram showing an example of a configuration of a motion vector detecting unit of a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 3 is a diagram for explaining an example of uncorrect
  • FIG. 5 is a diagram for explaining an example of a vector correcting process which refers only to an upper vector in a fame interpolating circuit according to an embodiment of the present invention.
  • FIG. 6 is a flow chart showing an example of a vector corresponding process which refers only to a left vector in a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 7 is a flow chart showing an example of a vector corresponding process which refers to one of an upper vector and a left vector in a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 8 is a flow chart showing an example of a vector corresponding process which refers to one of an upper vector and a left vector in a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 6 is a flow chart showing an example of a vector corresponding process which refers only to a left vector in a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 7 is a flow chart showing an example of a vector
  • FIG. 9 is a diagram for explaining vector values showing a concrete example of a vector correcting process performed by a frame interpolating circuit according to an embodiment of the present invention.
  • FIG. 10 is a block diagram showing an example of a configuration of a display apparatus including a frame interpolating circuit according to an embodiment of the present invention.
  • a frame interpolating circuit 1 in FIG. 1, for example, has a frame memory 11 which receives an input image signal I 1 having 60 frames/second of RGB standards or YCbCr standards as an example and outputs an output image signal I 2 having 120 frames/second as an example, and a motion vector detecting unit 12 which compares pixel values of a past frame (F1) and a present frame (F2) stored in the frame memory 11 to generate a motion vector by using symmetric searching, block matching, or the like and includes filtering using an upper left vector.
  • a frame memory 11 which receives an input image signal I 1 having 60 frames/second of RGB standards or YCbCr standards as an example and outputs an output image signal I 2 having 120 frames/second as an example
  • a motion vector detecting unit 12 which compares pixel values of a past frame (F1) and a present frame (F2) stored in the frame memory 11 to generate a motion vector by using symmetric searching, block matching, or the like and includes filtering using an upper left vector.
  • the frame interpolating circuit 1 has an interpolated frame generating unit 13 which generates an interpolated frame (F3) on the basis of the past frame (F1) and the present frame (F2) from the motion vector detecting unit 12 and the motion vector generated by the motion vector detecting unit 12, and a control unit 14 which controls an entire operation as will be described below.
  • the motion vector detecting unit 12 has a motion vector matching unit 21, a final vector determining unit 22, and a motion vector filter unit 23 using the upper left vector.
  • the motion vector matching unit 21 and the final vector determining unit 22 in the motion vector detecting unit 12 including filtering using the upper left vector, and on the basis of the past frame image (F1) and the present frame image (F2) from the input image signal (I 1 ), motion vectors V 11 to V 55 as obtained before correction in FIG. 9 are detected.
  • a filtering process of the motion vector filter unit 23 using the upper left vector is performed by procedures described later.
  • the interpolated frame generating unit 13 Upon receiving the motion vectors V 11 to V 55 from the motion vector detecting unit 12 including filtering using the upper left vector, the interpolated frame generating unit 13 generates the interpolated image (F3) on the basis of the past frame image (F1) and the present frame image (F2) from the input image signal (I 1 ) to output the past frame image (F1), the interpolated image (F3), and the present frame image (F2) to the subsequent part in the order named. In this manner, even though a video image includes large motion, for example, a smooth and natural video image free from breakdown can be displayed on a panel display unit.
  • a filtering process to correct an assembly of motion vectors such as the uncorrected motion vectors V 11 to V 55 as shown in FIG. 9, which are considerably different from motion vectors of a peripheral block, will be described below in detail by using the flow charts or the like shown in FIGS. 3 to 8. Steps in the flow charts in FIGS. 4, 6, and 7 can be replaced with circuit blocks, respectively. Therefore, all the steps in the flow charts can be redefined as blocks, respectively.
  • FIG. 3 As motion vectors, an upper vector having 0 of an x component is set, subsequent present blocks 10, 10, 10, and 10 are set, and blocks having 0 as x components are set. A part of the motion vectors 10 is a part having a high probability of erroneous detection.
  • the corrected present vector is circulated, and "2" obtained by adding step ⁇ to "1" is the value of the next present vector.
  • the vector value is gradually changed into “3", "4", "3", "2”, and "1".
  • step ⁇ As the value of the step ⁇ , "1", “2", “3”, or the like can be properly set.
  • step S11 when a plurality of motion vectors in the plurality of blocks are received from the final vector determining unit 22, one of the present vectors, i.e., the vector V1 is compared with an upper vector V2 (step S11).
  • step value ⁇ ( ⁇ is a constant such as 1)
  • step S13 it is asked whether xt - xu
  • step S16 When
  • the filtering process is performed to one present vector V1 in the frame.
  • the filtering process is preferably performed to the motion vectors in all the blocks in the frame.
  • a filtering process using a left vector will be described below with reference to FIG. 5. Operations to be performed are the same as those in the filtering process using the upper vector shown in FIG. 3.
  • step S21 when a plurality of motion vectors in a plurality of blocks are received from the final vector determining unit 22, one of the motion vectors, i.e., a present vector V1 is compared with a left vector V3 (step S21).
  • step value ⁇ ( ⁇ is a constant such as 1)
  • step S23 it is asked whether xt - xl
  • step S26 When
  • the filtering process is performed to one present vector V1 in the frame.
  • the filtering process is preferably performed to the motion vectors in all the blocks in the frame.
  • step S31 when a plurality of motion vectors in a plurality of blocks are received from the final vector determining unit 22, one of the motion vectors, i.e., a present vector V1 is compared with an upper vector V2 (step S31).
  • step value ⁇ ( ⁇ is a constant such as 1)
  • step S34 a smoothing process using the upper vector shown in FIG. 4 as a base point is performed (step S34).
  • step S34 a smoothing process using the upper vector shown in FIG. 4 as a base point is performed (step S34).
  • step S36 When the value of the present vector V1 is close to the value of the left vector V3 in step S33, a smoothing process using the left vector shown in FIG. 6 as a base point is performed (step S36).
  • the filtering process of one of the vectors in the frame i.e., the present vector V1 is performed.
  • the filtering process is preferably performed to the motion vectors in all the blocks in the frame.
  • a present vector is filtered with reference to vectors in an upper block and a left block to make it possible to suppress vectors from being sharply changed and to correct vector erroneous detection with a certain degree of assembly. Therefore, breakdown of an interpolated image caused by sharp changes of vectors can be reduced.
  • a plurality of uncorrected vectors V 11 to V 51 especially, the vectors V 24 , V 34 , V 44 , V 23 , V 33 , V 43 , V 22 , V 32 , and V 42 supplied from the final vector determining unit 22 form an assembly of motion vectors which are largely different from motion vectors of a peripheral block.
  • the vectors V 24 , V 34 , V 44 , V 23 , V 33 , V 43 , V 22 , V 32 , and V 42 are changed into vectors V 24 ', V 34 ', V 44 ', V 23 ', V 33 ', V 43 ', V 22 ', V 32 ', and V 42 ', respectively, by the filtering process using the upper left vector as shown in FIG. 7.
  • the assembly having vectors which are considerably different from the motion vectors of a peripheral block can be corrected. In this manner, an interpolated image can be avoided from being broken by sharp changes of the vectors.
  • a panel display apparatus 30 using the frame interpolating circuit 1 has, an example, a tuner unit 31 which outputs a broadcast signal as a video signal, a scaler 32 which performs a scaling process for the video signal, an IP converting unit 33 which performs IP conversion to the video signal, a processing unit 34 including color management, enhancer, and correcting circuits and the like, the frame interpolating circuit 1 described above, and a panel unit 15 such as a liquid crystal display unit or an FPD (Flat Panel Display) which receives an output from the frame interpolating circuit 1.
  • a tuner unit 31 which outputs a broadcast signal as a video signal
  • a scaler 32 which performs a scaling process for the video signal
  • IP converting unit 33 which performs IP conversion to the video signal
  • processing unit 34 including color management, enhancer, and correcting circuits and the like
  • the frame interpolating circuit 1 described above and a panel unit 15 such as a liquid crystal display unit or an FPD (Flat Panel Display) which receives an output
  • the panel display apparatus 30 having such a configuration can cause the frame interpolating circuit 1 to correct an assembly having vectors which are considerably different from motion vectors of a peripheral block as described above.
  • a smooth and natural video image can be displayed by using an interpolated frame having an unbroken video image.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Computer Hardware Design (AREA)
  • Television Systems (AREA)
EP20070016752 2006-09-08 2007-08-27 Rahmeninterpolationsschaltung, Rahmeninterpolationsverfahren und Anzeigevorrichtung Withdrawn EP1898353A3 (de)

Applications Claiming Priority (1)

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JP2006244729A JP4799330B2 (ja) 2006-09-08 2006-09-08 フレーム補間回路、フレーム補間方法、表示装置

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EP1898353A2 true EP1898353A2 (de) 2008-03-12
EP1898353A3 EP1898353A3 (de) 2008-07-23

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JP4982345B2 (ja) * 2007-12-10 2012-07-25 株式会社東芝 フレーム補間回路、フレーム補間方法、表示装置
JP2010081411A (ja) * 2008-09-26 2010-04-08 Toshiba Corp フレーム補間装置及びフレーム補間方法
ITTO20110653A1 (it) * 2011-07-20 2013-01-21 Inst Rundfunktechnik Gmbh Apparecchio visore per la visualizzazione di immagini 3d

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WO1996033571A2 (en) * 1995-04-11 1996-10-24 Philips Electronics N.V. Motion-compensated field rate conversion
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WO2006012375A1 (en) * 2004-07-20 2006-02-02 Qualcomm Incorporated Method and apparatus for motion vector processing

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EP1898353A3 (de) 2008-07-23
JP2008067222A (ja) 2008-03-21
US20080063289A1 (en) 2008-03-13
JP4799330B2 (ja) 2011-10-26

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