Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3436—Arrangements for verifying correct programming or erasure
  • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
  • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3436—Arrangements for verifying correct programming or erasure
  • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells

Definitions

• the present invention relates to non-volatile memory, and more particularly to a method and apparatus for reducing soft-writing in a multilevel flash memory.
• Other memory is multi-level, having more than one bit in each memory cell. Multiple bits require more than two levels of current to represent the bits, further reducing the margin for error in reading memory cells. The margin for error is more limited in multi-level memory than in single-level memory.
• Reference word lines 7 select a row of reference cells 8, while reference bit lines 9 from polarization circuit 11 select the column.
• reference word lines 7 are all at the same voltage level VXR, which is also the voltage for word line WLS 3.
• Reference bit lines 9 and bit lines 5 for the matrix memory array 1 are typically around 1V. Word lines 3 that are not active are held at OV, while unselected bit lines 5 are floating.
• the voltage VXR applied to cells 6 is higher than the three reference cell's 8 threshold voltages.
• the current in each of the N selected cells 6 is compared to one reference cell 8 in the case of a single bit memory cell, or to three reference cells 8 in the case of a two bit memory cell.
• FIG. 1B a graph illustrating voltage threshold distributions for matrix cells in a single bit memory.
• FIG. 1B is discussed in conjunction with FIG. 1A.
• a reference cell 8 has a threshold voltage (Vtr) 13 at which it activates.
• Vtr threshold voltage
• VXR read 15 In order to read on the gate of a selected cell 6 and/or a reference cell 8, a voltage VXR read 15 must be higher than the threshold voltage Vtr 13.
• N different cells 6 are selected while the same reference cell 8 is always polarized. If the current (or its ratio/multiple) read from a memory cell is above the reference cell, then the value in the memory cell is 1 , otherwise it is 0.
• a two-bit matrix cell In a two-bit matrix cell, three read reference cells are used to distinguish between four different current states called 11 , 10, 01 , and 00. Each memory cell can have four different current values. Current values correspond to threshold values. In the case of a two-bit memory cell, there are four threshold distributions that represent the four current states, distributed around the three reference cells (see FIG. 1 D) during 'modify' operations.
• Figure 1C illustrates a simplified conventional memory circuit 10.
• Memory cells 12-1 through 12-n (collectively referred to as memory cells 12) are connected through drain polarization circuits 14-1 through 14-n (collectively referred to as polarization circuits 14) to current comparison circuit
• reference cells 18 make up a reference cell matrix for a two-bit memory cell.
• an enable signal is sent to drain polarization 14, while a voltage VX is applied to the gate of memory cell 12 by a row decoder (not shown).
• ld_cell current flows through memory cells 12 and drain polarization circuits 14.
• Reference cells 18 have their gates brought to voltage VX, while an enable signal is sent to drain polarizations 2OA, 2OB, and 2OC (collectively referred to as drain polarizations 20).
• Different currents Id_ref1 , Id_ref2 and
• 1C should be high enough to turn on all of reference cells 18, and high enough to supply current in order to read the cells within the time allotted. Higher voltage levels improve current comparison circuit 16 access and read times, however if it is too high then selected reference and memory cells may be soft-programmed or soft-written. High gate voltage and a polarized drain may result, particularly in an erased cell being soft-written. This will cause false reads from the memory cell.
• VXR 30 With a high voltage level VXR 30, it is possible to move the threshold voltage of reference cells 32 upward, including cells of distributions 11 , 10, and 01 , especially reference cell 32 A and matrix cells belonging to low threshold distribution 11 , which have the lowest voltage threshold level. Furthermore, the space between the distribution of voltage threshold levels, and space between the read reference thresholds and matrix cell threshold distributions may decrease, also causing memory read fails if current comparison circuit 16 could be unable to differentiate between the cells.
• the distance between matrix cell distributions and reference thresholds defines the read error margin. So that if, for example, reference cell VTR1 , after several reads, is soft-written, the margin to correctly read a cell belonging to distribution 10 is reduced.
• a system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell.
• a first group and second group of reference cells are coupled to the memory cell and are configured to receive a first and a second voltage.
• a current comparison circuit is coupled to the first and second groups of reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first group of reference cells, and to determine whether the memory cell holds a first range of values.
• the first group of reference cells receives the first voltage, and if the memory cell does not hold the first range of values, the system determines whether the memory cell holds a second range of values. Only the second group of reference cells receives the second voltage, thereby reducing soft-writing during the read operation.
• Each group of reference cells includes one of more reference cells.
• the number of groups of reference cells may differ and may change according to the kind of multilevel cell, according to the number of bits per cell.
• a first group of reference cells could include two reference cells while a second group of reference cells could include a single reference cell.
• the preseht invention reduces soft-writing in a multilevel flash memory by applying a lower voltage during a memory read or verify than conventional systems.
• a 2 bit memory cell there are three read reference cells in which first the first and second read reference cells are used in a first read while the third reference cell is used in a second read.
• the first two read reference cells are configured to receive a first gate voltage in a first phase that is lower than in a conventional system, while the third read reference cell is configured to receive a higher gate voltage (for example, the gate voltage applied to reference cells in conventional systems) during a second phase of the read, if the first phase does not yield the memory value.
• a higher gate voltage for example, the gate voltage applied to reference cells in conventional systems
• first and second read reference currents are compared to all selected array memory cells (whose gate receive first phase gate voltage and whose drains are polarized) to determine whether all the selected memory cells hold a first range of values (11 , 10). If all selected array cells belong to one of the two first values (11 or 10), then the memory read is complete, without completing the second phase.
• a second read phase is initiated in order to determine which of the second range of values (10 and 00) is in the array of memory cells.
• the read reference cells that have a lower threshold voltage
• the third read reference that has a higher voltage threshold
• its drain is polarized (in order to turn on the third read reference cell).
• the drains of the reference cells that were polarized during the first read phase are no longer polarized, therefore reducing soft-writing during the read operation by avoiding a high gate voltage at the same time that their drains are polarized.
• soft-writing is reduced by deactivating both the gate voltage and drain polarization for low-threshold reference cells during subsequent phases of a read operation.
• Read reference cells are more vulnerable to soft-writing than matrix cells because they are polarized for each read while the selected matrix cells are different for each read.
• read reference cells have a polarized drain and have high gate voltage more often than matrix cells.
• some reference cells in particular the lower threshold ones) have a reduced gate voltage with their drain polarized.
• soft- writing is reduced by deactivating the drain polarization for matrix low-threshold cells during subsequent phases of a read operation, although a gate voltage may still be applied. This may avoid the case of high gate voltage with a polarized drain on low threshold cells.
• Figure 1A is a simplified schematic illustrating a conventional circuit for a matrix array of M rows and P bit lines.
• Figure 1B a graph illustrating voltage threshold distributions for matrix array cells in a single bit memory.
• Figure 1C is a schematic diagram illustrating a conventional memory and reference cell routing system.
• Figure 2 a graph illustrating voltage threshold distributions for a matrix array of cells in a multilevel memory.
• Figure 3 is a block diagram illustrating one embodiment of the invention in a memory circuit.
• Figure 4 is a flow diagram illustrating one method for reducing soft-writing in the memory circuit of FIG. 3.
• Figure 5 is a timing diagram illustrating enable signals applied to the drain polarization circuits in FIG. 3.
• Figure 6 is a voltage diagram illustrating gate voltages applied to the reference and memory cells in FIG. 3.
• Figure 7 is a voltage and timing diagram for a conventional system illustrating enable signals applied to the drain polarization circuits 20 and 14 and voltage applied to reference cells 18 and memory cell 12 in FIG. 1.
• Figure 8 is a voltage and timing diagram illustrating enable signals applied to the drain polarization circuits, and gate voltage applied to the memory cell in FIG. 3.
• the present invention relates to non-volatile memory, and more particularly to a method and apparatus for reducing soft-writing in a multilevel flash memory.
• the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
• FIG. 3 is a block diagram illustrating one embodiment of the invention in a two-bit memory circuit 300.
• Selected memory cell 305 is connected through drain polarization circuit 310 to current comparison circuit 315.
• Three reference cells 320A, 320B, and 320C (collectively referred to as 320) make up a reference cell matrix for two-bit memory cell 305.
• Drain polarization circuits 325-A, 325-B, and 325-C (collectively referred to as 325) connect reference cells 320 to current comparison circuit 315.
• Drain polarization circuits 310 and 325 polarize the drain of selected memory cell 305 and reference cells 320 (respectively) during read memory operations.
• Selected memory cells of the array 305-1 through 305-m are collectively referred to as 305.
• Drain polarization circuits 310-1 through 310- m are collectively referred to as 310.
• Figure 4 is a flow diagram illustrating one method for reducing soft-writing in the memory circuit 300 of FIG. 3 during a read operation.
• a row decoder (not shown) applies a voltage VXR1 (illustrated in FIG. 6) to the gate of memory cell 305 in FIG. 3 and to the gates of reference cells 320A and 320B.
• Drain polarization circuits 325A, 325B and 310 also receive enable signals, polarizing the drains of reference cells 320A and 320B, and selected memory cells 305.
• Voltage VXR1 may be less than voltage VXR in a conventional system, for example 1 volt lower, and sufficiently high to activate reference cells 320A and 320B.
• current comparison circuit 315 determines whether the memory cell 305 holds a first range of values, for example bit values 11 and 10. Because lower voltage VXR1 has activated only reference cells 325-A and 325-
• the current comparison circuit 315 determines that at least one of the currents flowing through memory cells 305 falls outside the range for reference cells 320A and 320B, then in block 430 the drains and gates of reference cells 320A and 320B are turned off and the drain and gate of reference cell 320C are turned on. Then, in block 435, a second, higher voltage VXR2 is applied to the memory cells 305 and to reference cell 320C, while the drains of the cells belonging to the 11 or 10 state are turned off. Drain polarization circuit 325-C receives an enable signal and activate the drain of reference cell 320C while drain polarization circuits 325-A and 325-B are left floating during the second memory operation. Only a part of the drain polarization circuit 310 is disabled, which corresponds to already defined selected cells whose drains are left floating.
• Voltage VXR2 may be at the same level as voltage VXR in conventional systems, and another reading is done with reference cell 325-C.
• current comparison circuit 315 determines which value each still undefined memory cell 305 holds along a second range of values, for example 01 and 00, by determining whether the current flowing through each still undefined memory cell 305 is greater than or less than the current flowing through reference cell 320C.
• Figure 5 is a timing diagram illustrating enable signals transmitted to the drain polarization circuits 325 and 310 in FIG. 3.
• the horizontal axis represents time while the vertical axis represents signal level. From time zero to time T1 505 corresponds to a first read sequence in a read operation, while time T ⁇ 505 to time T2 510 corresponds to a second read in a single read operation of memory circuit 300, for example.
• EN3 in graph 520 may be set high for both first and second read sequences, as illustrated by the dotted line in graph 520.
• drain polarization circuits 325-A and 325-B receive enable signals EN1 and EN2 at the beginning of a read operation, for example.
• Graph 540 illustrates that polarization circuit 310 receives enable signal EnCeIIi during the same period. From time zero to time T1 505 corresponds approximately to blocks 400 and 415 in FIG. 4, after voltage is applied to reference cells 320A and 320B in block 400. If the value stored in the selected cell 305C is one in the lower memory range, for example 11 or 10, its corresponding enable signal EnCeIIi is deasserted at time T1 505 because its value is found and a second read is unnecessary.
• Enable signal EnCeII of the drain polarization circuit 310C will be deasserted after the first read if the corresponding cell 305 belongs to state 11 or 10, otherwise it may remain high if cell 305 belongs to 01 or 00 state and a second read is needed. Signals EN 1 and EN2 are deasserted at the end of the first read if a second read is necessary.
• graph 520 illustrates time T1 505 to time T2 510.
• enable signal ENCeIIi corresponding to the drains of the selected cell not yet defined in the first phase read and received by one of drain polarization circuits 310 in FIG. 3, is asserted from time zero through time T2 510, corresponding to both read sequences, as illustrated in graph 560.
• a second read is performed during a given read operation of memory circuit 300 when the stored value is in the upper range (for example, 01 and 00).
• Figure 6 is a voltage diagram illustrating gate voltages applied to the reference cells 320 and memory cell 305 in FIG. 3.
• Graphs 600 and 620 correspond to reference cells 320 and graph 640 corresponds to memory cell 305.
• the horizontal axis represents time while the vertical axis represents voltage level.
• Time T1 605 corresponds to time T1 505 in FIG. 5 while time T2 610 corresponds to time T2 510 in FIG. 5.
• time T1 605 to time T2 610 corresponds to a second read in a single read operation of memory circuit 300, for example.
• Graph 640 illustrates that in the case where at least one of the bit values is in the upper range, voltage VXR1 may be applied to memory cells 305 from time zero to time T1 605, and voltage VXR2 is applied to memory cells 305 from time TI 605 to time T2 610.
• Figure 8 is a voltage and timing diagram illustrating enable signals applied to the drain polarization circuits 310 and voltage applied to memory cells 305 in FIG. 3.
• voltage VXR1 is applied to the gate of reference cells 320A and 320B, and to the gate of memory cell 305, from time zero to time T1 805, as illustrated in graph 800. If the values stored in all selected cells of the array are in the lower range, then at approximately time T1 805, voltage will then decrease to zero (not illustrated).
• VXR1 lower than voltage VXR. Drains of selected cells have a different enable signal so that drains of cells that have already been defined in the first read phase can be left floating during the second read phase, thereby reducing the likelihood of soft-writing by avoiding a high gate voltage with a polarized drain for low threshold cells.
• the gate of reference cell 320C may be pre- charged to VXR1/VXR2 during a first read.
• the gates of each of the reference cells 320 may be brought to VXR1 , a voltage level that will activate only reference cells 320A and 320B, not 320C.
• VXR1 and VXR2 may be increased in order to achieve greater speed.
• Pre-charging gates and pre-polarizing drains of reference cells may be used together or separately in order to decrease the amount of time needed for a second or further read sequence.
• the total time for two read sequences using the invention with pre-charging and pre-polarizing may be only slightly greater than the entire time taken in conventional systems for a read operation, providing the benefits of reducing the likelihood of soft-writing and threshold drift with a small impact on speed.
• the above embodiments apply to a two-bit memory circuit, but also that the invention may be implemented with a multi-level memory with more than two bits, for example three, four, or eleven bits. More read sequences may be used for correspondingly more bits, with several (rather than only two) levels of voltage being used. For example, in a four-bit memory, 16 values are stored so 15 reference cells may be used. 14 read sequences may be used, or 13, or 7, or however many a designer wishes to implement, balancing the likelihood of soft- writing the reference cells/matrix cells and threshold drift with speed and timing.

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• 2005
  • 2005-12-20 WO PCT/US2005/046412 patent/WO2006071686A2/en active Application Filing
  • 2005-12-20 EP EP05855037A patent/EP1839312A2/de not_active Withdrawn

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