WO2006071686A3 - Method and system for reducing soft-writing in a multi-level flash memory - Google Patents

Method and system for reducing soft-writing in a multi-level flash memory Download PDF

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Publication number
WO2006071686A3
WO2006071686A3 PCT/US2005/046412 US2005046412W WO2006071686A3 WO 2006071686 A3 WO2006071686 A3 WO 2006071686A3 US 2005046412 W US2005046412 W US 2005046412W WO 2006071686 A3 WO2006071686 A3 WO 2006071686A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory cell
writing
reducing soft
flash memory
voltage
Prior art date
Application number
PCT/US2005/046412
Other languages
French (fr)
Other versions
WO2006071686A2 (en
Inventor
Lorenzo Badarida
Casser Fabio Tassan
Simone Bartoli
Giorgio Oddone
Original Assignee
Atmel Corp
Lorenzo Badarida
Casser Fabio Tassan
Simone Bartoli
Giorgio Oddone
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from IT002538A external-priority patent/ITMI20042538A1/en
Application filed by Atmel Corp, Lorenzo Badarida, Casser Fabio Tassan, Simone Bartoli, Giorgio Oddone filed Critical Atmel Corp
Priority to EP05855037A priority Critical patent/EP1839312A2/en
Publication of WO2006071686A2 publication Critical patent/WO2006071686A2/en
Publication of WO2006071686A3 publication Critical patent/WO2006071686A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.
PCT/US2005/046412 2004-12-29 2005-12-20 Method and system for reducing soft-writing in a multi-level flash memory WO2006071686A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05855037A EP1839312A2 (en) 2004-12-29 2005-12-20 Method and system for reducing soft-writing in a multi-level flash memory

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IT002538A ITMI20042538A1 (en) 2004-12-29 2004-12-29 METHOD AND SYSTEM FOR THE REDUCTION OF SOFT-WRITING IN A FLASH MEMORY AT MULTIPLE LEVELS
ITMI2004A002538 2004-12-29
US11/144,174 US7522455B2 (en) 2004-12-29 2005-06-02 Method and system for reducing soft-writing in a multi-level flash memory
US11/144,174 2005-06-02

Publications (2)

Publication Number Publication Date
WO2006071686A2 WO2006071686A2 (en) 2006-07-06
WO2006071686A3 true WO2006071686A3 (en) 2007-04-12

Family

ID=36615416

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/046412 WO2006071686A2 (en) 2004-12-29 2005-12-20 Method and system for reducing soft-writing in a multi-level flash memory

Country Status (2)

Country Link
EP (1) EP1839312A2 (en)
WO (1) WO2006071686A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10468096B2 (en) 2012-10-15 2019-11-05 Seagate Technology Llc Accelerated soft read for multi-level cell nonvolatile memories

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050157555A1 (en) * 2004-01-21 2005-07-21 Tsuyoshi Ono Nonvolatile semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050157555A1 (en) * 2004-01-21 2005-07-21 Tsuyoshi Ono Nonvolatile semiconductor memory device

Also Published As

Publication number Publication date
WO2006071686A2 (en) 2006-07-06
EP1839312A2 (en) 2007-10-03

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