WO2007076512A3 - Methods and device for improved program-verify operations in non-volatile memories - Google Patents

Methods and device for improved program-verify operations in non-volatile memories Download PDF

Info

Publication number
WO2007076512A3
WO2007076512A3 PCT/US2006/062627 US2006062627W WO2007076512A3 WO 2007076512 A3 WO2007076512 A3 WO 2007076512A3 US 2006062627 W US2006062627 W US 2006062627W WO 2007076512 A3 WO2007076512 A3 WO 2007076512A3
Authority
WO
WIPO (PCT)
Prior art keywords
verify
threshold level
sub
relative
programming
Prior art date
Application number
PCT/US2006/062627
Other languages
French (fr)
Other versions
WO2007076512A2 (en
Inventor
Siu Lung Chan
Original Assignee
Sandisk Corp
Siu Lung Chan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/323,596 external-priority patent/US7224614B1/en
Priority claimed from US11/323,577 external-priority patent/US7310255B2/en
Application filed by Sandisk Corp, Siu Lung Chan filed Critical Sandisk Corp
Priority to KR1020087015676A priority Critical patent/KR101317625B1/en
Priority to EP06848897A priority patent/EP1966802A2/en
Priority to JP2008548835A priority patent/JP4638544B2/en
Publication of WO2007076512A2 publication Critical patent/WO2007076512A2/en
Publication of WO2007076512A3 publication Critical patent/WO2007076512A3/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.
PCT/US2006/062627 2005-12-29 2006-12-27 Methods and device for improved program-verify operations in non-volatile memories WO2007076512A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020087015676A KR101317625B1 (en) 2005-12-29 2006-12-27 Methods and device for improved program-verify operations in non-volatile memories
EP06848897A EP1966802A2 (en) 2005-12-29 2006-12-27 Methods and device for improved program-verify operations in non-volatile memories
JP2008548835A JP4638544B2 (en) 2005-12-29 2006-12-27 Method and apparatus for improved program verify operation in non-volatile memory

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/323,596 US7224614B1 (en) 2005-12-29 2005-12-29 Methods for improved program-verify operations in non-volatile memories
US11/323,596 2005-12-29
US11/323,577 US7310255B2 (en) 2005-12-29 2005-12-29 Non-volatile memory with improved program-verify operations
US11/323,577 2005-12-29

Publications (2)

Publication Number Publication Date
WO2007076512A2 WO2007076512A2 (en) 2007-07-05
WO2007076512A3 true WO2007076512A3 (en) 2007-08-16

Family

ID=38110643

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/062627 WO2007076512A2 (en) 2005-12-29 2006-12-27 Methods and device for improved program-verify operations in non-volatile memories

Country Status (5)

Country Link
EP (1) EP1966802A2 (en)
JP (1) JP4638544B2 (en)
KR (1) KR101317625B1 (en)
TW (1) TWI328231B (en)
WO (1) WO2007076512A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101559088B1 (en) 2008-04-08 2015-10-08 샌디스크 테크놀로지스, 인코포레이티드 Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITRM20080114A1 (en) * 2008-02-29 2009-09-01 Micron Technology Inc COMPENSATION OF CHARGE LOSS DURING THE PROGRAMMING OF A MEMORY DEVICE.
JP5172555B2 (en) 2008-09-08 2013-03-27 株式会社東芝 Semiconductor memory device
JP5193830B2 (en) 2008-12-03 2013-05-08 株式会社東芝 Nonvolatile semiconductor memory
KR101005117B1 (en) * 2009-01-23 2011-01-04 주식회사 하이닉스반도체 Operating method of non volatile memory device
JP5039079B2 (en) * 2009-03-23 2012-10-03 株式会社東芝 Nonvolatile semiconductor memory device
KR101554727B1 (en) 2009-07-13 2015-09-23 삼성전자주식회사 Nonvolitile memory device and program method thereof
US8223556B2 (en) * 2009-11-25 2012-07-17 Sandisk Technologies Inc. Programming non-volatile memory with a reduced number of verify operations
KR101633018B1 (en) 2009-12-28 2016-06-24 삼성전자주식회사 Flash memory device and program method thereof
JP2011258289A (en) * 2010-06-10 2011-12-22 Toshiba Corp Method for detecting threshold value of memory cell
KR101656384B1 (en) * 2010-06-10 2016-09-12 삼성전자주식회사 Method of writing data in a non-volatile memory device
JP5380506B2 (en) * 2011-09-22 2014-01-08 株式会社東芝 Nonvolatile semiconductor memory device
JP2014053060A (en) 2012-09-07 2014-03-20 Toshiba Corp Semiconductor storage device and control method of the same
JP2014063551A (en) 2012-09-21 2014-04-10 Toshiba Corp Semiconductor memory device
TWI514394B (en) * 2013-08-27 2015-12-21 Toshiba Kk Semiconductor memory device and its control method
JP7132443B2 (en) * 2019-10-12 2022-09-06 長江存儲科技有限責任公司 METHOD OF PROGRAMMING MEMORY DEVICES, SYSTEMS AND RELATED MEMORY DEVICES
US11594293B2 (en) 2020-07-10 2023-02-28 Samsung Electronics Co., Ltd. Memory device with conditional skip of verify operation during write and operating method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050162923A1 (en) * 2004-01-27 2005-07-28 Guterman Daniel C. Charge packet metering for coarse/fine programming of non-volatile memory
US20050162916A1 (en) * 2004-01-27 2005-07-28 Guterman Daniel C. Efficient verification for coarse/fine programming of non-volatile memory
US20050248988A1 (en) * 2004-05-05 2005-11-10 Guterman Daniel C Boosting to control programming of non-volatile memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3679544B2 (en) * 1997-03-28 2005-08-03 三洋電機株式会社 Nonvolatile semiconductor memory device
JP3977799B2 (en) * 2003-12-09 2007-09-19 株式会社東芝 Nonvolatile semiconductor memory device
US7136304B2 (en) * 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7170793B2 (en) * 2004-04-13 2007-01-30 Sandisk Corporation Programming inhibit for non-volatile memory
ITRM20050310A1 (en) * 2005-06-15 2006-12-16 Micron Technology Inc SLOW CONVERGENCE IN SELECTIVE PROGRAMMING IN A FLASH MEMORY DEVICE.

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050162923A1 (en) * 2004-01-27 2005-07-28 Guterman Daniel C. Charge packet metering for coarse/fine programming of non-volatile memory
US20050162916A1 (en) * 2004-01-27 2005-07-28 Guterman Daniel C. Efficient verification for coarse/fine programming of non-volatile memory
US20050248988A1 (en) * 2004-05-05 2005-11-10 Guterman Daniel C Boosting to control programming of non-volatile memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101559088B1 (en) 2008-04-08 2015-10-08 샌디스크 테크놀로지스, 인코포레이티드 Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise

Also Published As

Publication number Publication date
KR101317625B1 (en) 2013-10-10
WO2007076512A2 (en) 2007-07-05
TWI328231B (en) 2010-08-01
JP2009522707A (en) 2009-06-11
JP4638544B2 (en) 2011-02-23
EP1966802A2 (en) 2008-09-10
KR20080096645A (en) 2008-10-31
TW200746151A (en) 2007-12-16

Similar Documents

Publication Publication Date Title
WO2007076512A3 (en) Methods and device for improved program-verify operations in non-volatile memories
WO2010117807A3 (en) Two pass erase for non-volatile storage
TW200709209A (en) Selective slow programming convergence in a flash memory device
WO2009111158A3 (en) Charge loss compensation during programming of a memory device
EP1686592A3 (en) Partial erase verify
TW200707189A (en) Memory block erasing in a flash memory device
WO2005073975A3 (en) Efficient verification for coarse/fine programming of non-volatile memory
WO2002082447A3 (en) Soft program and soft program verify of the core cells in flash memory array
WO2003036650A3 (en) Method for erasing a memory cell
WO2005073977A3 (en) Variable current sinking for coarse/fine programming of non-volatile memory
TW200703340A (en) Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells
JP2010535395A5 (en)
TW200737211A (en) An programmable non-volatile memory device of lowing program margin needed for user program operation and method for testing the same
WO2009139567A3 (en) Memory device and memory programming method
TW200632922A (en) High speed programming system with reduced over programming
TW200703338A (en) Memory structure and method of programming
JP2008305536A5 (en)
DE60122059D1 (en) Programming method for a semiconductor memory cell
TWI265522B (en) Operation scheme for spectrum shift in charge trapping non-volatile memory
KR20120092911A (en) Semiconductor memory apparatus and method of erasing data
TWI368226B (en) Method for programming error correction code into a solid state memory device with varying bits per cell and device using the same
EP1176609A3 (en) Testing of multilevel semiconductor memory
WO2007111688A3 (en) Method and apparatus for programming/erasing a non-volatile memory
JP2012142067A5 (en)
TW200625315A (en) Nonvolatile semiconductor memory device which erases data in units of one block including a number of memory cells, and data erasing method of the nonvolatile semiconductor memory device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200680050047.2

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2006848897

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2008548835

Country of ref document: JP

Ref document number: 1020087015676

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE