TWI328231B - Methods and device for improved program-verify operations in non-volatile memories - Google Patents

Description

1328231 IX. Description of the Invention: [Technical Field] The present invention relates generally to non-volatile semiconductor memory such as electrically erasable programmable read only memory (EEPROM) and flash EEPROM. It relates to non-volatile semiconductor memory that implements time-saving features during stylized verification operations. [Prior Art] Solid-state memory capable of storing charges non-volatilely, especially solid-state memory in the form of eepr〇m and flash EEPROM packaged as a small factor (small f0rm factor) card has recently become a variety of actions and handheld Selected storage devices in devices, especially information devices and consumer electronics. Unlike RAM (Random Access Memory), which is also a solid-state memory, the flash memory system is non-volatile and retains its stored data even after the power is turned off. Despite the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage devices based on rotating magnetic media such as hard drives and flexible disks are not suitable for mobile and handheld environments. This is due to the fact that the disk drive tends to be bulky and prone to mechanical failure and has high latency and high power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, embedded and flash memory in the form of removable cards are ideally suited for mobile and handheld environments due to their small size, low power consumption, high speed and high reliability. EEPR0M and electrically programmable read-only memory (EPROM) are non-volatile memory that can be erased and new data is written or "programmed" into its memory 117671.doc 1328231 unit. Both of these utilize a floating (unconnected) conductive closed end of the field effect transistor structure which is located between the source and the gate regions on the channel region in the semiconductor substrate. A control gate is then provided on the floating gate. The threshold voltage characteristics of the transistor are controlled by the amount of charge held on the floating gate. That is, for the positioning of the charge on the floating gate, there is a corresponding voltage (probability) that must be applied to the control gate before the conduction of the transistor to the conduction between the source and the drain region. The floating gate maintains a range of charge and can therefore be programmed to any threshold voltage level within the threshold voltage window. The size of the threshold voltage window is determined by the minimum and maximum threshold levels of the device. Delimitation 'The minimum and maximum threshold levels of the device correspond to the range of charge that can be programmed onto the floating gate. The threshold window usually depends on the characteristics, operating conditions and history of the memory device. A distinct, resolvable threshold voltage level range can in principle be used to represent a determined memory state of a cell. A transistor that acts as a memory cell is typically programmed by one of two mechanisms to "programmed" The state is in "hot electron injection", the high voltage applied to the drain accelerates electrons across the substrate channel region. At the same time, the high voltage applied to the control gate pulls the hot electrons Passing a thin gate dielectric to the floating gate. In the "tunneling injection", a high voltage is applied to the substrate relative to the substrate. In this way, electrons are pulled from the substrate to the inserted floating gate. The memory device can be erased by a number of mechanisms. For EPR 〇M, 5' can erase memory in large quantities by removing the charge from the floating gate using ultraviolet radiation. For EEPROM, A threshold voltage is applied to the substrate at the control gate to tunnel electrons in the floating gate to the substrate channel region via a thin oxygen 117671.doc 1328231 (ie, Fowler-Nordheim tunneling (Fowler-Nordheim) Tunneling)) electrically erases the memory cell. Typically, the EEPR〇M can be erased bit by bit. For flash EEPr〇m, all or one of the erasures—or multiple blocks The ground erases the memory, wherein one block can be composed of 5 12 bytes or more of the memory. The example memory device of the non-volatile memory unit includes T installed on a card. One or more memory chips. Each memory chip package An array of memory cells supported by peripheral circuits such as decoders and erase, write and read circuits. More complex memory devices also have a controller that performs intelligent and higher order memory operations and interfaces. There are many commercially successful non-volatile solid state memory devices used today. These memory devices can employ different types of memory cells, each type having one or more charge storage elements. Circles 1A through 1E indicate Illustratively illustrating different examples of non-volatile memory cells. A sleepy 1A schematically illustrates a non-volatile memory having a floating gate for storing charge in the form of an EEPROM cell. Electrically erasable and programmable The read memory (EEPROM) has a similar structure to the EPROM, but additionally provides a mechanism for electrically loading and removing charges from its floating closed end without exposure to UV radiation after application of an appropriate voltage. Examples of such units and methods of making the same are given in U.S. Patent No. 5,5,95,924.囷1B schematically illustrates a flash EEPROM cell having a select gate and a control or pilot gate. The memory cell 10 has a split channel "12 between the source 14 and the drain "expanded 117671.doc. A single unconnected early τ system is effectively formed with two transistors MT2 in series. T1 acts as a float The interpole 20 and the memory transistor controlling the closed end 30. The floating gate can store an optional amount of charge. The amount of current in the channel portion of the H T1 depends on the voltage on the control closed-pole 30 and resides in the inserted floating gate. The number of charges on the pole 20. D2 acts as the selective transistor with the selected gate 40. #Τ2 is selected by the gate bias voltage when it is turned on 'it allows the current in the channel portion of T1 to be at the source The passage between the poles and the selection of the electrical body independently of the control of the electricity at the closed pole provides an opening along the source drain-channel. One advantage is that it can be used to cut off the charge attributed to the cell at the floating gate. Depletion (positive) and their conduction at zero control gate voltage. Another advantage is that it allows for easier implementation of source side injection stylization. A simple embodiment of a split channel memory cell is shown in Figure 1. Illustrated by the dotted line as shown in Fig. 3, the selection gate The pole and the control gate are connected to the same word line by placing the charge storage element (floating gate) on one of the channels and the control gate structure (which is part of the word line) on the other channel portion and located The charge storage element is implemented. This effectively forms a cell having two transistors in series, wherein a transistor (memory transistor) controls the flowable by a combination of the amount of charge on the charge storage element and the voltage on the word line. The number of currents through its channel portion, and another transistor (selective transistor) causes the word line to act as its gate alone. U.S. Patent Nos. 5,070,032, 5'095'344, 5,315,541, 5,343,063 and 5,661,53 An example of such a unit's use in a memory system and a method of manufacturing the same. 117671.doc 1328231 A more improved embodiment is to select the gate and the control gate independently of each other and not between the dotted lines When connected...implements the connection of the row control gates in the cell array to the control (or steering) lines perpendicular to the word lines. The effect is to read or program the word lines freely. Two functions must be performed simultaneously at the same time. The two functions are: (1) acting as the idle electrode of the selection transistor. Therefore, an appropriate voltage is required to turn on and off the selected transistor.

The split channel unit body shown in 圊1B; and driving the voltage of the charge storage element to a desired level via an electric field (capacitance) between the word line and the charge storage element. It is often difficult to perform both of these functions in an optimal manner using a single voltage. In the case of independent control of the control interpole and the selection gate, the word line only needs to perform the function (1), and at the same time, the added control line performs the function (2). This ability allows the «X to compare the performance of the program, which makes the stylized voltage suitable for the target data. The use of a flash EEPROM array to independently control (or direct) the gate is described in, for example, U.S. Patent Nos. 5,313,421 and 6,222,762.圊ICtf is an illustrative representation of another flash EEPROM module with dual floating gates and independent selection and control gates. The memory cell 1 eliminates a memory cell similar to 囷1B except that it effectively has two transistors in series. In this type of unit, 'two storage elements (ie, T1_left storage element and T1_right storage element) are included on their channels between the source and the drain diffusion with a selective transistor between them The Th memory transistors have floating gates 20 and 20 and control gates 3 and 3, respectively. The selection of the transistor τ2 is controlled by the selection gate 40. At any one time, only the pair of memory transistors are accessed for reading or writing. When accessing the storage unit T1 to the left, turn on T2 and T1-right to allow the current in the channel portion of the τι·left to pass between the source and the 汲H7671.doc 1328231 pole. Similarly, when accessing When the storage unit T1 • is right, turn on T2 and Τ1 - left. One of the gates of the selected gate polysilicon is very close to the floating gate and a substantially positive voltage (eg, 20V) is applied to the selected gate so that electrons stored in the floating gate can tunnel to the selective gate polysilicon And achieve erasure.囷1D schematically illustrates a string of memory cells organized into a reverse (NAND) cell. The NAND cell 50 is composed of a series of memory transistors m, M2, ... Μη (η = 4, 8, 16 or higher) which are derived from their source and daisy-chained ). A pair of selection transistors SI, S2 control the connection of the memory transistor chain to the outside via the source terminal 54 and the terminal terminal 56 of the NAND cell. In a memory array, when the source select transistor S1 is turned on, the source terminal is coupled to the source line. Similarly, when the drain select transistor S2 is turned on, the drain terminal of the NAND cell is coupled to the bit line of the memory array. Each memory transistor in the chain has a charge storage element to store a given amount of charge to represent the desired memory state. The control gate of each memory transistor provides control over read and write operations. The control gates of each of the selected transistors S1, S2 provide controlled access to the NAND cells via source terminal 54 and gate terminal 56 of the NAND cell, respectively. When the addressed memory transistor in the NAND cell is read and verified during the stylization, its control gate is supplied at an appropriate voltage. At the same time, the remaining unaddressed memory cell system in the NAND cell 5 is fully turned on by applying a sufficient voltage across its control gate. In this way, the conductive path is effectively generated from the source of the individual memory transistor to the source terminal 54 of the NAND cell and also from the gate of the individual memory transistor 117671.doc -10- 1328231 to the gate terminal 56 of the cell. . A memory device having the NAND cell structure is described in U.S. Patent Nos. 5,570,315, 5,903,495, 6,046,935. Figure 1E schematically illustrates a non-volatile memory having a dielectric layer for storing charge. A dielectric layer is used in place of the electrically conductive floating gate elements described earlier. Such memory devices utilizing dielectric storage elements have been used by Eitan et al.

It is described in "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell, " IEEE Electron Device Letters, U.S. U.S.A., Vol. 21, pp. 543-545. The dielectric layer extends over the channel between the source and the drain diffusion. The charge for one data bit is located in the dielectric layer adjacent to the drain and the charge for the other data bit is located in the dielectric layer adjacent the source. For example, U.S. Patent Nos. 5,768,192 and 6,011,725 disclose non-volatile memory cells having a dielectric sandwiched between two ceria layers. Multi-state data storage is performed by independently reading the binary state of the charge storage region separated by a space within the dielectric. Memory Array A memory device typically includes a two-dimensional array of memory cells arranged in columns and rows and addressable by word lines and bit lines. The array can be formed according to an inverse (N〇R) type or a NAND type architecture. NOR Array 囷 2 illustrates an example of a n〇R array of § recalled cells. A memory device having an n〇r type architecture has been implemented in a cell of the type illustrated in the circle 1 b or 1C. Each column of memory cells is daisy-chained by its source and drain 117671.doc IJ28231. This design is sometimes referred to as a virtual ground design. Each memory cell ι〇 has a source 14' poleless 16, a control gate 30 and a selection pole 40. In one column: "Single 兀 makes its selection gate connected to word line 42. - the cells in the row have their source and poles connected to the selected positioning elements 34 and 36. In some embodiments in which the memory cells have their control gates and select gates independently controlled, the guide lines 36 are also Connect the control gates of the cells in a row. Many flash EEPROM devices are implemented in a memory cell in which each of the Lu# memory cells is formed with their control gates and select gates connected together. In this case, no guide lines are needed and a word is needed. The line simply connects all of the control gates and select gates of the cells in each column. Examples of such designs are disclosed in U.S. Patent Nos. 5,172,338 and 5,418,752. In these designs, the word line basically performs two functions: column selection and supplying the control gate voltage to all cells in the column for reading or programming. N AND Array 囷3 illustrates an example of a NAND array of memory cells, such as shown in 囷id •. Along the NAND chain, one bit line is coupled to the 汲 terminal 56 of each NAND chain. Along each column of the nanD chain, a source line can connect all of the source terminals 54 of the NAND cell. Moreover, the control gates of the NAND chain along a column are connected to a series of corresponding word lines. An entire column of naND chains can be addressed by turning on the selected transistor pair (see - 囷1D) via the associated word line to control the appropriate voltage on the gate. When a memory transistor representing a memory cell in the NAND chain is being read, the remaining memory transistors in the chain are difficult to turn on via their associated word lines such that the current of the chain is substantially dependent on The level of charge stored in the unit being read. NAND architecture 117671.doc -12- 1328231 An example of an array and its operating system as part of a memory system are found in U.S. Patent Nos. 5,570,315, 5,774,397 and 6, 〇 46,935. Stylization and Stylization Suppression In the case of stylization against memory, a stylized voltage pulse is applied to the word line connected to the page of a selected memory cell. In this page, the memory cells to be programmed are set to other memory cells whose bit line voltage is set to 〇V and not yet to be programmed, so that the bit line voltage is set to the system power supply voltage Vdd to suppress stylization. . Setting the bit line to vdd effectively cuts off the selected transistor and causes the floating channel on the opposite side of the chain. During stylization, the voltage at the floating channel will rise with a high word line voltage. This will effectively reduce the potential difference between the channel and the charge storage unit' thereby preventing electrons from being pulled from the channel to the charge storage unit for programming. Block Erase The stylization of a charge storage memory device can only result in more charge being added to its charge storage element. Therefore, the existing charge in the erased charge storage element must be removed prior to program operation. Providing an erase circuit (not shown to erase one or more blocks of memory cells. When together (ie, at _ instant) one of the entire array of cells or a significant unit of the array When a non-volatile memory system such as EEPROM is called, the EEPROM flashes "EEPRQM. Once erased, then the group unit is re-thailed. The group of units that can be erased together can be one or A plurality of addressable erasing units are formed. The erasing unit or block usually stores one or more stomach f-pages to program and read the unit, and the camp can be Xia ^, ' < early in the early morning Stylized or read 117671.doc -13· - more than one page. Each page usually stores one or more sectors; the size is determined by Φ4 ^ ^. Disk drive, i's standard 512-bit user data plus sectors for additional information on the number of bytes used for the batting and/or the block in which the user f is stored. Read/Write The circuit establishes at least - current breakpoint ^ in the usual two-shaped SEEPR0M^ to conduct the conduction window (C〇 Nduction window) is divided into two regions. When a cell is read by applying a pre-charged, fixed voltage, its source and drain current are resolved by comparison with the breakpoint level (or reference current w) = State, if the current reading is higher than the current reading of the breakpoint level, then the unit is determined to be in a logic state (eg 'zero' state). On the other hand, if the current is less than the current at the breakpoint level, then The decision unit is in another logic state (eg, "one" state.) Therefore, the two state unit stores one bit of digital information. A reference current source that can be externally programmed is often provided as a memory system. Partly to generate a breakpoint level current. In order to increase the memory capacity, as the state of semiconductor technology develops, flash EEPROM devices are being manufactured to have ever higher density. Another method for adding storage capacity is to make each A memory cell stores more than two states. - For a multi-state or multi-bit quasi-EEPROM memory cell, the conduction window is split into more than two regions by more than one breakpoint so that each The unit can store more than one bit of data.—The information that can be stored in a given EEPR〇M array is therefore increased with the number of states that each unit can store. It has 117671.doc 1328231 multi-state or multi-bit quasi-memory unit EEPR〇M or flash eepr〇m has been described in U.S. Patent No. 5,172,338. In practice, 'the source electrode and the 汲 electrode of the early element are typically sensed by applying a reference voltage to the control gate. The upper state conducts the current to read the memory state of the cell. Therefore, for each given charge on the floating gate of the cell, the corresponding conduction current with respect to the fixed reference control gate voltage can be detected. Similarly, the charge & range that can be programmed to the (iv) gate defines a corresponding threshold _ voltage window or a corresponding conduction current window. Alternatively, instead of detecting the conduction current in the split current window, a threshold voltage for a given memory state in the test can be set at the control gate and the conduction current is detected below or above the threshold current. In one implementation, the detection of the conduction current relative to the threshold current is achieved by examining the rate at which the conduction current completely discharges the capacitance of the bit line.囷4 illustrates the relationship between the source-drain current ID and the control gate voltage VCG for the four*-one loads Q1 to Q4 that the floating gate can selectively store at any one time. The four pairs of VCG solid lines represent four possible charge levels that can be programmed on the floating gate of the memory cell, which correspond to four § 己 recall states, respectively. As an example, the threshold voltage window of a unit group can be in the range of up to 3.5 yen. The six memory states can be demarcate by dividing the threshold window into five regions with a spacing of 0.5 每 per region. For example, if a reference current (lREF) of 2 μΑ is used as shown, the unit stylized with Q1 can be considered to be in the memory state “1" 'because its curve intersects iREF at 乂(3)=〇5 ¥ and 丨0V demarcation in the threshold window area. Similarly, Q4 is in memory state "5". II7671.doc 15 As can be seen from the above description, the more states the memory cells are stored, the finer the threshold window is. This will require more precision in stylization and read operations to achieve the desired resolution. U.S. Patent No. 4,357,685 discloses a method of staging a 2-state EPROM' wherein when a unit is programmed to a given state, the unit is subjected to a continuous stylized voltage pulse, each time adding an increasing charge to the floating gate. Between pulses, the cell is read back or verified to determine its source-no-pole current relative to the breakpoint level. Stylized stop when the current state has been verified to have reached the desired state. The stylized bursts used can have an increased period or amplitude. Previous prior art stylized circuits only applied stylized pulses to step through the erased window from the erased or grounded state until the target state was reached. In fact, to allow for sufficient resolution, each segmented or demarcated region will require at least about five stylized steps to be landscaped. This performance is acceptable for 2-state memory cells. However, for multi-state cells, the number of steps required increases with the number of partitions and, therefore, must increase stylized precision or resolution. For example, a 丨6 state unit may require an average of at least 40 stylized pulses to be programmed to a target state.圊5 schematically illustrates a memory device having a typical configuration of a memory array, which can be stored by a read/write circuit 〇7, a column decoder 130, and a row decoder 160. take. As described with respect to circles 2 and 3, the memory cell system of the memory cells in memory array 1 can be addressed via a set of selected word lines and bit 7L lines. Column decoder 13 selects one or more word lines and row decoder 160 selects one or more bit lines to apply the appropriate voltage 117671.doc ·16·1328231 to the respective gates of the addressed memory transistor. A read/write circuit 170 is provided to read or write (program) the memory state of the addressed memory transistor. The read/write circuit Π0 includes a plurality of read/write modules connectable to the memory elements in the array via bit lines. Factors Affecting Read/Write Performance and Accuracy To improve read and program performance, parallel read or program multiple charge storage elements or memory transistors in an array. Therefore, a logical π page" memory component is read or programmed together. In existing memory architectures, a column typically contains a number of interlaced pages. All memory elements of a page will be read or programmed together. The row decoder will selectively connect each of the interlaced pages to a corresponding number of read/write modules. For example, in one implementation, the memory array is designed to have a page size of 532 bytes (5 12 bytes plus an additional 20-bit group). If each row contains a 汲-bit line and there are two interlaced pages per column, then this reaches 85 12 rows, each of which is associated with 4256 ticks. There will be 4256 sensing modules that are connectable. Read or write all even or odd bit lines in parallel. In this way, the page is read from the page of the memory element—the page is parallelized with 4256 bits (ie, 532 bytes) or the 35 data is programmed into the page of the memory element. The read/write module forming the read/write circuit 170 can be configured in various ways as mentioned above, by conventionally juxtaposed squares for all even or all odd bit lines. Performing the operation and improving the read write write #作~ By (four) interleaved page group, the alternate bit line" frame helps to alleviate the problem of assembling the read/write circuit block. 1 also I17671. Doc

-17- is specified by considering the capacitive coupling of the control bit line to the bit line. The block decoder is used to multiplex the group of read/write modules to even or odd pages. In this way, the parent error group can be grounded each time a group of bit lines is read or programmed. Minimize the direct adjacent bit lines. However, the 'interlaced page architecture' is disadvantageous in at least three respects. First, it requires additional multiplexed circuits. Second, it is slow in terms of performance. Two reads or two stylization operations are required to complete the reading or programming of a memory cell connected by a sub-line or connected to a column. Third, it is also not optimal in dealing with other interference effects, such as floating gates when programming two adjacent charge storage elements at different times (such as independently in odd and even pages). The polar level is the field coupling between adjacent charge storage elements. U.S. Patent Publication No. 2004_0057318-A1 discloses a memory device that allows parallel sensing of a plurality of connected memory cells and a method thereof. For example, all memory cells along a column that share the same word line are read or programmed together as one page. This "full bit line" architecture doubles the performance of the alternate bit line architecture while minimizing errors caused by adjacent interference effects. However, sensing all bit lines does cause crosstalk problems caused by currents induced between adjacent bit lines due to their mutual capacitance. By sensing the conduction current of each adjacent bit line, This problem is addressed by making the voltage difference between each adjacent bit line substantially independent of time. When this condition is imposed, all the displacement currents due to the capacitance of the various bit S lines are dropped, since they all depend on the time varying voltage difference. A sensing circuit coupled to each bit line has a voltage clamp on the bit line such that 117671.doc 18· 1328231 does not perform the second sub-loop until the first threshold in the group has been verified The value is up. In the preferred implementation, the operation of _ is called "one-bit (four)"("OBP") is performed at the end of the first-cutting ring to check whether the group has any memory in the group. The unit is programmed to exceed the first-threshold level. In the event, the subsequent verification loop will no longer require 〇Bp but will contain the second sub-cycle.

The additional features and advantages of the present invention will become apparent from the following description of the preferred embodiments of the invention. [Embodiment]

囷 6A schematically illustrates a compact memory device having a set of read/write circuits that provides a scenario for practicing the present invention. The memory device includes a two-dimensional array 300 of memory cells, a control circuit 31A, and a read/write circuit 370. The memory array 300 can be addressed by a word line through a column decoder 33 and by a bit line via a row decoder 360. The read/write circuit 37 is implemented as a group

Memory unit. In a preferred embodiment, the pages are comprised of memory cells in contiguous columns. In another embodiment in which a column of memory cells is divided into a plurality of blocks or pages, a block multiplexer 350 is provided to multiplex the read/write circuits 37 至 to individual blocks. Control circuit 310 cooperates with read/write circuit 370 to perform a memory operation on memory array 300. Control circuit 310 includes state machine 312, on-wafer address decoder 314, and power control module 316. State machine 312 provides wafer level control of the memory operation. The on-wafer address decoder 314 supplies the address interface between the host or the address used by the host or the 117671.doc -20· 1328231 〇 忆 控制器 controller ^ # μ > μ & 7 to the hacker and 36 〇 The hardware address used. The power control module 3 16 controls the power and voltage supplied to the word lines and bit lines during the memory operation. The preferred arrangement of the compact memory device shown in Figure 6 illustrates the access to the memory array 300 by various peripheral circuits on opposite sides of the array in a symmetrical manner to enable access on each side. The line and circuit are reduced by half. Therefore, the column decoder is split into column decoders 330Α and 330Β, and the row/decoder is split into row decoders 360Α and 360Β. In an embodiment in which a column of memory cells is divided into a plurality of blocks, the region The block multiplexer 35〇 splits into a block multiplexer 350Α and 350Β»similarly, the read/write circuit is split into a read/write circuit 37 from the bottom to the bit line and from the array 3〇. The top of the crucible is connected to the read/write circuit 37 of the bit line. In this way, the density of the read/write module and thus the density of the set of sensing modules 480 is substantially reduced - half The entire set of ρ sensing modules 480 in parallel operation allows parallel reading or programming of one cell along a column (or page) of a column. An example memory array can have ρ = 512 bits Tuple (5 12x8 bits). In the preferred embodiment, the block is a series of whole In another embodiment, the block is a subgroup of cells in the column. For example, the unit of the subgroup may be one half of the entire column or one quarter of the entire column. The unit of the subgroup may be a series of Connected units or every other unit or every predetermined number of units. Each sensing module includes a sense amplifier for sensing the conduction current of the memory unit. 囷6C illustrates several sensing modules to read / Write to the preferred grouping of the stack. The read/write stack 490 allows implementation in a space efficient manner of factoring out the common components of the H7671.doc -21- = sensing module shown in the circle 6Α Figure 6D is an unintentional illustration of the overall configuration of the basic components in the read/write stack shown in Figure 6: 螬 & @ λ crystal μ^ 'read/write stack 490 includes A stack of sense amplifiers 212 for sensing k bit lines, a 17-inch module 44G for storing or inputting data via a 1/〇 bus bar 231 (4) person or output data Data latch 11430 - stacking - processing and storing data in the read / write stack 49 a processor 5 (10), and a stack bus 421 for communicating between the stacked components. The stack bus controller in the read/write circuit 37 provides control and timing signals via line 411 for: The various components in the stack are fetched/written. The coprocessor includes one or more registers or latches 52 for temporarily storing data during processing. A preferred read/write stack has been disclosed in 2004. A preferred sense amplifier is disclosed in U.S. Patent Application Publication No. 2004-109357357A, the entire disclosure of which is incorporated herein by reference. . Examples of Reading and Styling for Multi-State Memory Circles 7A through 7E, 8 to 8 £, and from the top to the three examples of multi-bit encoding of the state memory. In a 4-state memory cell, four states can be represented by two bits. One prior art is to program the memory using 2-path stylization. The first bit (the next page bit) is stylized by the first path. Subsequently, the same unit is programmed in the second path to indicate the desired first & (top page bit). In order to not change the value of the first bit in the second round, the memory state representation of the second bit depends on the value of the first bit. 117671.doc -22- 1328231 囷7A to 7E illustrate the stylization and reading of 4-state memory encoded by the conventional 2-bit Gray code. Dividing the range of programmable threshold voltages (the threshold window) of the memory unit into four regions, representing an unprogrammed "U" state and three other increasingly stylized states"A", &quot ;B" and "c". The four regions are divided by the boundary threshold voltages DA, db, and Dc, respectively. 7A illustrates the threshold of the 4-state memory array when each memory cell stores the data of two bits using the conventional Gray code. Voltage distribution. The four distributions represent the four memory states, U", "A" ' "B" and "C" groups. Before stylizing the memory unit, 'first erase it to its "U" or "unstylized" status. As the memory unit becomes more and more stylized, it gradually reaches the memory state "A","B" and "C". Gray code uses (upper, lower) to represent ''U' as (1) , 1) 'Express "A" is expressed as (1, 〇), will,, B" is expressed as (〇, 〇) and "C" is expressed as (〇, 1).囷7B shows the next page stylization using Gray code with the existing, 2-path stylization mechanism. For a page unit to be staggered, the upper and lower bits will cause two logical pages: a logical lower page consisting of lower bits and a logical upper page composed of upper bits. The first stylized path only stylizes the next page bit. With proper encoding, the subsequent, second stylized path to the same page unit will program the logical upper page bit without resetting the logical lower page bit. The Gray code is a commonly used code in which only the bit changes when transitioning to the adjacent state. Therefore, since only one bit is involved, this code has the advantage of having less demand for error correction. The general mechanism when using Gray code is to make "represent "unprogrammed" conditions.

117671.doc -23· Therefore, by (top page, next page bit) = indicates that the erased memory state "u" » in the first path of the stylized logic page, the storage bit " Any unit of " will therefore change its logical state from (χ,〇 to (χ,〇), where X" denotes the upper-level "unrelated" value. However, since it has not been programmed, it is consistent For example, the "i "tag"χ" can be expressed by (s, 0) logic state by stylizing the unit to the memory state "A". That is, before the second stylized path The memory state "A" indicates the lower bit value "〇. 囷7C illustrates the upper page stylization using the Gray code with the existing, 2-path stylization mechanism. The second path is programmed to store the logical upper page. Bits. Only those units that require the previous page bit value "〇" will be programmed. After the first path, the cell in the page is in a logical state (1, 丨) or (1, 〇). Keep the value of the next page in the second path, you need to distinguish the lower bit value or 1. For the transition from (1,0) to (〇,〇) to the stylized memory unit considered as memory state "B" for the transition from (1,1) to (〇, 〖) In this way, the memory unit in question is programmed to the memory state "c„. In this way, during the retrieval period, the memory of the next page can be decoded by determining the memory state programmed in a unit. Page bit. The stylized pulse is applied to the side-by-side memory unit by the parent, and then each of the units is sensed or programmed to determine whether any of them have been programmed into Stylized with its target state, each time a programmatically validates a unit, even when the stylized pulse continues to be applied to complete the stylization of other units in the group, the unit is locked or programmed to be protected from further programs. As can be seen from 7B and 7C, during the next page of stylization, it is necessary to verify the status of the stroke with respect to the state of the demarcation threshold voltage Da <A" 117671.doc •24· 1328231 (by "Verification A&quot ; indicated). Then, for For page stylization, 'need to perform stylized verification against state "B" and "c" Therefore, the previous page verification will require 2 path verifications relative to the threshold threshold voltage Db and %: "Verification B" and "Verify C". 囷7D describes the read operation required to distinguish the bits under the * state memory encoded by Gray code. Because of the memory state encoded by (U) "A" and by (〇,〇) encoding The "B '丨 all and "〇'丨 you; ^甘丁^ 八 as its lower position, so whenever the memory unit is programmed to the state "W, the lower bit T will be detected. Conversely, whenever the memory unit is not stylized or stylized in the state "U", "c", the lower bit "r will be detected. Therefore, the next page read will need to be read relative to the demarcation threshold voltage DA&Dci2 path: read A and read C, respectively.囷 7E illustrates the read operation required to distinguish the bits above the 4-state memory encoded in Gray code. It will need to read the path relative to the threshold threshold voltage: read B. In this way, any cell with a programmed threshold voltage of less than % is detected to be in a memory state "" and vice versa. When the second path is stylized, the Gray code, 2 path stylization mechanism can become a problem. For example, when the next bit is in "〗", the stylization of the previous page bit to "〇" will cause a change from (1,丨) to (〇, υ. This requires the case unit to self "U" is gradually programmed to "c via "Α" and "Β", and if there is a power outage before the stylization, the memory unit can terminate in one of the transition memory states (for example, "A"). When reading a memory unit, it will decode "A" into a logical state (1, 〇). This gives the upper and lower + correct result, since it should be (0, 1) Similarly, if it reaches "B", it will correspond to (0, 0) ^ When the upper bit is correct, the bit H7671.doc -25· 1328231 is still wrong. Since the unstylized state "u" all the way: (a11 the way t〇) the most stylized state "c" possible change, so this code • mechanism has the charge position of the adjacent cells stylized at different times The effect of the potential difference between the quasi-ops. Therefore, it also increases the field between adjacent floating gates. Effect coupling ("Yupin effect'·). Figures 8A through 8E illustrate the stylization and 5 buy of 4 state memory encoded with another logic code ("LM codes). This code provides more fault tolerance (fault_t〇 Leranee) and φ mitigate adjacent element coupling due to YuPin effect. Figure 8A illustrates the threshold voltage distribution of a 4-state memory array when each δ-recall unit uses LM code to store two-bit data. The difference between the code and the conventional Gray code shown in 囷7Α is that the upper and lower bits are reversed for the states "Α" and „c". The LM" code has been disclosed in the US patent No. 6,657,891 and it is advantageous to reduce field effect coupling between adjacent floating gates by avoiding stylized operations that require large charge changes. Figure 8B illustrates the use of LM code in an existing, 2-round stylized mechanism. The next page is stylized. The fault-tolerant LM code basically prevents any previous page stylization from transitioning through any intermediate state. Therefore, the first round of the next page stylizes the logical state (1, 1) to an intermediate state (X' 0), if by "Unstylized "memory state"U is stylized to the "intermediate" state represented by (X,〇), which has a greater than Da in the widely distributed state Less than Dei has programmed threshold voltage. Circle 8C shows the previous page stylization using the LM code with the existing, 2-round stylization mechanism. In the second round of stylizing the previous page, if the next page is at "1 ", then by "unprogrammed" memory state" 117671.doc •26· s; 1328231 Stylized to "A", the logical state (1, 丨) is changed to (〇, 丨). If the following: Page 兀 is in ··〇", then by "middle" The state is stylized to "Β" and gets: Logic state (〇, 0). Similarly, if the previous page is kept at "1", then when the next page is programmed to "0", it will It is necessary to change the state, self, and intermediate state to (1, 0) by stylizing "intermediate, state" to "C". Since the previous page stylization only involves stylization to the next adjacent memory state, there is no large amount of charge change from one round to another round. From the "U" to the rough "intermediate" state, the φ page is programmed. To save time. However, this will cause the "LM" code to be equally susceptible to stylized errors or power outages during the previous page stylization. For example, the state "Α" can be moved to a threshold voltage that cannot be distinguished from the "middle" state. Circle 8D illustrates the read operation required to identify the bit below the 4-state memory encoded with the LM code. Decoding It will depend on whether the previous page has been programmed. If the previous page has been programmed, then reading the next page will require a read path relative to the threshold threshold voltage: read B. On the other hand, if the previous page has not been programmed , then the next page • is stylized to the "intermediate•' state (囫8B), and reading B will cause an error. Conversely, reading the next page will require a read path relative to the demarcation threshold voltage Da: Read A. In order to distinguish between the two conditions, when the upper page is being programmed, a flag ("LM"flag) is written in the previous page. During the reading, the upper page is first assumed to be stylized and thus The read]3 operation will be performed. If the ^^ flag is read, the assumption is correct and the read operation is performed. On the other hand, if the first read does not generate a flag, it will indicate that it has not been programmed. The previous page and therefore will have to read the next page by reading the A operation. 囷8E Description Discrimination The read operation of 117671.doc •27· c S ) 1328231 is required for the OM code to encode the upper level of the 4 state memory. As can be clearly seen from the figure, the page read will need to be separately relative to the threshold threshold voltage! ) 8 and 〇 (: 2 path read: read A and read C. Similarly, if the previous page has not been programmed, the decoding of the previous page can be confused by the "intermediate" state. Again The LM flag will indicate whether the previous page has been programmed. If the previous page is not programmed, the read data will be reset to , ^" to indicate that the previous page is not programmed. LM code is in the support page Stylized memory can also become a problem. When staging or reading a page of memory cells, partial page stylization allows one part of the page to be programmed in a path and not programmed in subsequent paths. The stylized remainder of the LM code presents a problem in a stylized operation that only partially fills the previous page with data. In the subsequent upper page stylization of the _completed unfilled page, the data can be stylized. To the wrong state. By convention, 1 'bit representation " none The "condition, and therefore the lower and upper elements are initially set to "丨" in the uncompiled "U" state. The previous page should be "1" 'which means unfilled The unit in the section. If the next page bit in the unfilled part is accidentally "丨", the resulting logic state (1,1) will keep the unit in ',u". However, if the next page If the bit is , it will result in a logic state (1, 0) that will cause the unit to be programmed to the most stylized (highest threshold voltage) "c" state. The possibility of reaching the (0, 0) or "B" state is no longer considered as soon as the subsequent stylized path of the unfilled portion is completed, as it can be returned from the "C" to a less stylized state.囷9A to 9E illustrate the stylization and reading of the 4-state memory with the preferred logic code ("LM New" code). The LM new code is similar to the lm code but does not have the above disadvantages.圚9A shows that when each memory unit causes the new code to store two 117671.doc • 28· 1328231 bits of data, the threshold voltage distribution of the 4-state memory array ^ LM new code has been revealed in Li et al. U.S. Patent Publication No. 2005-0237814 A1, which is incorporated herein by reference. This code differs from the LM code shown in Figure 8A in that the logical codes for the states "B" and "C" are interchangeable. Therefore, for "U" (superordinate, lower bit) is ( 1, 1), for "A" (superordinate, lower) is (〇, 1), for "B" (superordinate, lower) is (1,0), and for "C&quot (upper bit, lower bit) is (0, Ο)» This code avoids the problem of partial page stylization in the above LM code, because when the lower bit is at "0", it will now be partially unfilled. The previous page is stylized to the "Β" state. Subsequent stylization of partially unfilled parts will allow stylization from (1,0) to (0, 0) logic state, which corresponds to stylized from "Β" "C" state. 囷9Β illustrates the next page stylization using the LM new code with the existing, 2-path stylization mechanism. The fault-tolerant LM new code basically avoids any previous page stylization through any intermediate state transition. The next page of the first path is stylized to transition the logic state (1, 1) to an intermediate state (X, 〇), By stating "unprogrammed"memory state"U to the "intermediate" state represented by (X,0), the "intermediate" state has greater than DA but less than Dc The programmed threshold voltage. Figure 9C illustrates the upper page stylization using the LM new code with the existing, 2-path stylization mechanism. In the second path of the "0" The next page bit is at "1 ", as indicated by the stylized "unprogrammed"memory state" to "A", the logical state (1,1) is changed to ( 0,1). 117671.doc •29- 1328231 The lower right page π is at "ο, and the logic state is obtained by stylizing from the middle, & intermediate state to "c" (G, similarly, If the previous page remains at ", ·, then when the next page has been programmed to "0", you need to programmatically convert the "intermediate" state to the middle of the "B" , the state transitions to (1, 〇). +囷91) Describes the read required to distinguish the bits under the 4-state memory encoded by the LM new code. Take the operation. As for the status of the LM code, the same considerations apply here. First, the read 6 operation is performed to determine whether the 1^]^ flag can be read. If the LM flag can be read, the bay has been read. Styling the previous page and reading _ will correctly generate the next page of information. On the other hand, ## has not been programmed on the previous page, the next page will be read by reading the A operation. Circle 9E illustrates the ° selling operation required to identify the bit above the 4-state memory encoded in the LM new code. As can be clearly seen from the figure, the previous page read will need to be read in 3 paths relative to the threshold threshold voltages Da, Db and Dc: read A, 5 sell B and read C. The decoding of the previous page has the same considerations as described with respect to the LM flag of the above LM code. A discussion of the various codes used above for the example 4 state memory shows that the read operation may involve a single sensing path in "Read B" that compares the programmed threshold voltage to the threshold threshold voltage DB . The read b operation is suitable for reading the upper page under the S-Gray code or reading the next page under the LM code or reading the next page under LM Shinsaki. The read operation may also involve a 2-path read such as reading the next page under the conventional Gray code or taking the upper page under the LM code: read A and read C. The read operation may also involve reading the 3-path read of the previous page as in the LM new code. Read A, Read B, and Read c. I17671.doc -30· 1328231 囷10 schematically illustrates in more detail the sensing module shown in FIG. 6A suitable for sensing the memory. The sensing module 480 senses the conduction current of the memory cells in the chain 50 via the coupled bit line 36. It has a sensing node 481 that is selectively coupled to a bit line, a sense amplifier 600, or a read bus 499. Initially, isolation transistor 482 connects bit line 36 to sense node 481 when enabled by signal BLS. The sense amplifier 600 senses the sense node 48 1 . The sense amplifier includes a precharge/clamp circuit 64A, a RC cell current discriminator 650, and a latch 660. The sensing module 480 enables sensing of the conduction current of the selected memory cell in the reverse key. Before sensing, the voltage to the gate of the selected memory cell must be set via the appropriate word line and bit line. As will be described in more detail later, for a given memory state under consideration, the precharge operation begins by charging the unselected word line to voltage Vread and then charging the selected word line to a predetermined threshold voltage vT(i). The precharge circuit 64 then causes the bit line voltage to reach a predetermined threshold voltage suitable for sensing. This will induce the source _ 汲 传导 • • 流 • • • • • • • • 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测 侦测Conduct current. When there is a nominal voltage difference between the source and the drain of the memory cell, the conduction current is a function of the charge in the memory cell and the applied %(1). • When the Vt(1) voltage is stable, the conducted current or programmed threshold voltage of the selected memory cell can be sensed via the coupled bit line 36 via the transistor 63 that is gated using the signal XXL. The cell current discriminator 65A acts as a discriminator or comparator for the current level. It is lightly connected to the sensing node to sense the conduction current in the memory unit 117671.doc -31 - body unit. When the pre-charging is cut off by the transistor 632 as controlled by the signal HHL, the sensing starts. The conduction current will be subsequently charged to the unit. The flow discriminator 6 5 0 comes from the visitor * wood _ 疋 考 test electric discharge. When the light is lightened by cutting off the number XXL of the transistor 630, the predetermined discharge period ends. The magnitude of the sensed conduction power is reflected by the amount of voltage discharge of the reference capacitor at the end of the cycle, and when the result is controlled by the strobe signal STB, the result is latched into the latch 66〇 . The cell current discriminator 65 〇 effectively determines whether the conduction current of φ single turns is higher or lower than a given boundary current value IG(j). If it is high, the latch 66 is set to a predetermined state with a signal INV = 1 (high). In response to setting the signal INV to the "high" latch 66, the pull-down circuit is activated, which senses the node 481 and thus the connected bit line 邗 to the ground voltage. This will inhibit the memory unit 1 The conduction current in the 而 regardless of the control gate voltage, because there will be no voltage difference between the source and the drain of the cell. Generally, σ ' will exist by the corresponding number of multi-path sensing modules 4 8 〇 The page controller 498 supplies control and timing signals to each of the sensing modules. The page controller 498 causes each of the multipath sensing modules 480 to pass a predetermined number. The path ϋ = 1 to Ν) and the cycle also supplies a predetermined demarcation current value for each path Ι() ϋ) β. As is well known in the art, the boundary current value can also be implemented as a threshold voltage or a sense of supply. The time period is measured. After the last path, the page controller 498 reads to the read bus 499 with the signal [^] enabling the transfer gate 488 to use the state of the sense node 481 as sensed data. Will read a page from all multipath modules 48〇 Data Similar sensing module has been disclosed in Cernea, who's title

117671.doc -32- ·: S 1328231 is "IMPROVED MEMORY SENSING CIRCUIT AND METHOD FOR LOW VOLTAGE OPERATION" is dated August 4, 2005, U.S. Patent Publication No. 2005-0169082-A1. The entire disclosure of U.S. Patent Publication No. 2005-0169082-A1 is incorporated herein by reference. Smart, time-saving, stylized verification One of the important aspects of non-volatile memory performance is stylized speed. This section discusses ways to improve the stylized performance of multi-state non-volatile memory. Specifically, improved stylized operations are implemented with time-saving stylized verification. Fast Path Write ("QPW") The preferred stylized operation is referred to as "fast path write" (or "QPW"), which is disclosed in U.S. Patent No. 6,643,188, the entire disclosure of which is here It is incorporated herein by reference. The purpose of stylized memory is to write data quickly but accurately. In binary memory, it is only necessary to use a threshold threshold to distinguish between two memory states. When the memory unit is stylized above the threshold of the threshold, it is considered to be in the "programmed" state, otherwise it remains in the "unprogrammed" state. Alternatively, for a given gate voltage, less programmed cells will have more conduction current. Therefore, when a threshold threshold voltage is applied to the gate of the memory cell, there will be a corresponding demarcation conduction current. If a cell has a conduction current higher than the demarcation conduction current, it is considered to be in an unprogrammed state; otherwise it is in a programmed state. In multi-state memory, the situation is more complicated because the boundary is divided between two points 117671.doc - 33 · boundary level for each intermediate state. When stylized to a central squat, the early squat must be programmed with a threshold between the two demarcation levels. Therefore, it must be above the first demarcation level, but it does not need to be too high or it will exceed the second demarcation level. Therefore, accurate stylization is required. In terms of the population of stylized memory units, this achieves a close clustering of the single 70 population between the demarcation levels (see 囷7 to 囷8). Any inaccuracy in stylization will cause the distribution of a given state to mis-expand beyond its demarcation level. Even if it is spread within the boundary but spread to the limit, it will still be attributable to programmatic interference or other environmental effects that are prone to errors. This problem deteriorates as the number of states increases or deteriorates when the available threshold window decreases, or deteriorates in both cases. A technique that tightly distributes the state by programming the same data multiple times. An example is a coarse-final stylized method as described in U.S. Patent No. 6,738,289, which is incorporated herein by reference. Figure 11 shows two distributions of memory cells with a given programmed memory state, where the more developed distribution is generated by a single path stylized in VL level verification, and the tighter distribution is from one VH The level verification verifies that the second path of the second path is generated. In the first path, the unit is written to the unit using a stylized waveform PW1 of the first, lower verify level VL, thereby producing a distribution 1301. The programmed waveform then begins with a lower value for the second path. In the second path, the stylized waveform PW2 uses the second, higher verify level VH to shift this to the distribution 1303. This allows the first pass to place the unit into the coarse distribution, which then becomes tighter in the second path. Figure 12 shows an example of a two-path stylized waveform. Between each stylized pulse 117671.doc -34· 1328231 is the smaller gate voltage level used to sense the state of the memory cell after the last programmed pulse. The first step PW1 1401 uses a lower verify level VL ' while pW2 uses a higher verify level vh. As described in U.S. Patent No. 6,738,289, the second path (pW2 14〇3) can use a smaller step size, but the processes are the same except for different verification levels. The disadvantage of this method is that each stylized sequence requires two paths: the stylized waveform has to go through both of the full steps to perform 14〇1 and then start at 14〇3. The φ circle 13 is a timing chart for sensing in the verification operation of the two-path stylization operation. First, the word line WL is precharged. Thereafter, the bit line bL is precharged. When the precharged voltage is stable, the first strobe STB senses the high conduction state of the memory cell and latches it. These high conduction state bits are latched to ground to prevent them from introducing source bias errors to subsequent sensing. After the voltage in the bit line has returned to a steady state, the memory cell is sensed in the second strobe STB. Thereafter, the word line is discharged and ready for setting to the next stylized pulse. When the SCAN signal is determined, the # sense data is transferred to the data latch. In the two-path stylization operation, the verify operation causes WL to be set to VL during the first path and then to VH during the second path. If a single path with a single staircase of stylized pulses can be used, allowing the distribution to undergo an initial stylization phase based on lower verification VLi, but once this initial level is reached, the process can be slowed down and a higher verify VH is used & By entering the distribution, the writer can be executed more quickly. This can be achieved by using a bit line bias to "program the fast-paced writer" programmed in a single sequence of sequences for the stylized waveform. This algorithm can be achieved with two paths written. 117671.doc 1328231 A similar effect is described in more detail in U.S. Patent No. 6,643,188. Figure 14 shows a single path stylized waveform for fast path writing, except that the verify operation is performed at the VL level and the VH bit. In addition to the quasi (see the smaller secondary pulses between each stylized pulse), the stylized waveform QPW 1501 is similar to the first phase of the two-path algorithm. However, once the verification at VL occurs, the ladder continues. Rather than restarting the staircase waveform, the bit line voltage is raised as the ladder continues to slow down the stylized rate until the cell is verified at VH. This allows the pulse of the stylized waveform to monotonically not decrease and significantly shorten the stylization/verification loop. 15 is a timing diagram for sensing in a verify operation of a path qPW stylized operation. First 'precharge the word line WL to VL. Thereafter the precharge bit line BL» When the precharge voltage is stable, the vl strobe STB will sense the memory cell and latch it. When the first SCan signal is asserted, the sense VL data is transferred to the data latch. Verifying that their units will set their bit lines to a voltage that will slow down the stylization. The word line is then raised to the level VH. After the precharged voltage has stabilized, the first VH strobe STB The memory cell will be sensed and the memory conduction state of the memory bank 7L will be latched and latched. The bit lines of such high conduction state are latched to ground to prevent it from introducing the source bias error to the subsequent sense. After the voltage in the bit line has returned to a steady state, the memory cell is sensed in the second VH strobe STB. Thereafter, the word line is discharged and ready for setting to the next stylized pulse. When the second scAN signal is determined, the sensed VH data is transferred to the data latch.

117671.doc • 36· Go to step 712 for a stylized pulse. Second Verification Sub-Cycle with respect to the Second Threshold Step 730: Modify the bit line voltage of the verified unit to slow down the programming. Step 740: Precharging the word line to a second threshold voltage, the sensing will be performed with respect to the second threshold voltage. Step 742: Sense the group memory unit in parallel. Step 744: If any of the cells have been successfully verified with respect to the second threshold voltage, proceed to step 750, otherwise proceed to the next stylized pulse in step 712. Step 750: If all of the units in the group that need to be verified against the second threshold value have been successfully verified, proceed to step 760, otherwise proceed to step 752. Step 752: Suppress the unit that has just been verified to be programmed and proceed to the next stylized pulse in step 712. Step 760: Stylize with respect to verification of the second threshold voltage. An important feature here is that at the end of the first VL verification sub-loop, if no cells in the group exceed VL, the second VH verification sub-loop will be redundant. No need to waste time sensing, strobing and scanning VH data. Therefore, as long as no cells in the group exceed VL, the second VH verification sub-loop can be skipped, thereby achieving some time savings. In general, the more bits are segmented by the memory unit, the more demanding it will be for precise stylization, and the SQPW verification mechanism will be more beneficial. 117671.doc • 39· 1328231 In a preferred embodiment, the SQPW verifies the use of an over-element (OBP) scan operation to detect any bit that exceeds VL after sensing and gating of the VL data. If no bit exceeds VL, it will go directly to the next stylized pulse. If any bit exceeds VL, it will return to the normal VL scan and perform the remaining operations as normal QPW. In the next verify pulse, the OBP scan operation will be skipped. Figure 17 is a timing diagram of SQPW verification before any bit exceeds VL. It can be considered as a shortened cyclical performance of SPQW verification, and it is applicable when there are no bits in the group unit that have exceeded VL. It is essentially a VL sub-cycle of QPW as shown in Figure 15, but with an additional decision or an (OBP) scan operation for whether any of the bits exceeds VL. As shown by the OBP waveform for the SCAN signal, the OBP scan operation occurs at the end of the VL sub-loop and at the beginning of the VH sub-cycle. It basically detects whether any of the bits exceeds VL by checking the sensed result relative to the VL for the side-programmed group of cells. The sequence for the shortened cycle shown in Figure 17 is as follows: Phase 1: The selected word line WL is precharged to VL. Stage 2: The bit line BL is precharged to a voltage suitable for sensing. Phase 3: Sensing and strobing (VL gating) STB. Stage 4: The voltage of word line WL is changed from VL to VH. After the bit line voltage has been restored, OBP (-bit over) is performed to determine if any bit has been verified at VL. If the OBP scan operation determines that no bit has exceeded VL, then a shortened cycle occurs after the word line is discharged and the next stylized pulse. If shortened here

117671.doc -40- 1328231 If any bit in the ring exceeds VL, the loop will expand to become a full loop that also has verification at the VH level. Figure 18 is a timing diagram of SQPW verification for the first case where the bit has exceeded VL. It can be considered as an extended loop performance of SPQW verification, and it is suitable for the first occurrence of one of the group elements over VL verification. It is essentially a VL sub-cycle followed by an OBP scan operation and then further expanded with the VH sub-cycle of QPW shown in Figure 15. The sequence for the extended cycle shown in Fig. 18 is as follows: Stages 1 to 4: The same as stages 1 to 4 of the shortened cycle shown in Fig. 17.

Phase 5: Transfer the sensed VL data to the data latch (VL SCAN (VL scan)). Since the WL charging started in phase 4 takes a relatively long time, it is necessary to perform VL SCAN on the same verification sequence immediately after the OBP detects that any bit exceeds VL to save time. Stage 6: Sensing and strobing (VH first strobe). In the preferred embodiment, this is a preliminary fast sensing for detecting a high current state such that it can be severed without interfering with subsequence sensing. Phase 7: Allow bit line BL to return to the appropriate voltage. Stage 8: Sensing and strobing (VH second strobe). Stage 9: Discharge the word line WL.

Phase 10: Transfer the sensed VH data to the data latch (VH SCAN (VH Scan)).圊19 is a timing diagram of SQPW verification in a subsequent cycle just after the cycle after at least one bit has exceeded VL. Think of it as a normal loop of SPQW verification and it applies to at least the group unit

117671.doc -41 - 1328231 A sub-quantity has passed the subsequent verification loop after the VL loop. The basics are as follows: normal fast speed write verification with VL sub-cycle and VH sub-cycle as shown in Figure 15. Phase 1: The selected word line WL is precharged to VL. Stage 2: The bit line BL is precharged to a voltage suitable for sensing. Phase 3: Sensing and strobing (VL gating) STB. Phase 4: The voltage of word line WL is changed from VL to VH, and the VL data of sensed I is transferred to the data latch (VL SCAN). Stage 5: Sensing and strobing (VH first strobe). In the preferred embodiment, this is a preliminary fast sensing for detecting a high current state substantially below the VH level such that it can be severed without interfering with subsequence sensing. Phase 6: Allow bit line BL to return to the appropriate voltage. Phase 7: Sensing and strobing the sensed VH data (Vh second strobe) Phase 8: Discharge the word line WL. φ Stage 9. Transfer the sensed VH data to the data latch (vjj SCAN (VH scan)). An example of A-B-C verification using SQPW The earlier description of SQWP refers to stylized verification for a given threshold level. The same principle is basically applicable if there is more than one threshold level to be verified. This can occur in stylized multi-bit memory (such as 2-bit or 4-state memory bounded by three threshold levels VA, VB, and VC). For example, the use of the LM new code for the stylization of the previous page as shown in 圊9C would require stylized verification for all three threshold levels. C. S) 117671.doc -42- 1328231 In a preferred embodiment, verification operations for each of the three threshold levels can be continuously performed from successive sensing of lower to higher word line WL voltages . Stylized verification is initially only relative to VA, ie, verification A. As the programming continues, when at least one bit has been programmed to exceed VA, the program verification will have verification A and verification B. Similarly, if at least one element has been programmed to exceed VB, the stylized verification will check all three threshold levels with Verification A, Verification B, and Verification C. A similar smart verification mechanism has been disclosed in U.S. Patent Publication No. 2004-0109362-A1. The entire disclosure of this disclosure is incorporated herein by reference. Circle 20A is a timing diagram for SQPW involving three threshold levels and shows an initial stylization phase involving only verification A. The shortened cycle shown in 圊17 applies to VL and VH, which are replaced by VAL and VAH, respectively, before any bit exceeds VAL. After the OBP operation, when the one-bit exceeds the first condition of VAL, the subsequent sequence is the same as the extended cycle shown in FIG. Thereafter, the normal cycle of Figure 19 applies. The time saved by SQPW will be the number of cycles that have been shortened (the duration of the normal cycle minus the duration of the shortened cycle) and the scan time difference between the OBP and VL scans when the cycle is shortened.

Figure 20B is a timing diagram for SQPW involving three threshold levels and shows an intermediate stylization phase when verifying B is initiated in addition to Verification A. Since at least one bit has exceeded VAL at this stage, no OBP operation is required to check for this event. The sensing at VAL and VAH follows only the normal QPW verification cycle as shown in Figure 19. The sensing of the VBL will initially be a shortened circa 117671.doc -43 - 1328231 ring as shown in 圊17. Furthermore, if any bit after the OBP exceeds VBL, the VB verification is similar to the extended loop shown in 圊18. Moreover, in the next sensing cycle, a normal loop similar to the loop shown in Figure 19 will restart. The time saved and wasted by the SQPW for verification at the VB level will be calculated in a manner similar to that for VA.圊20C is a timing diagram for SQPWs involving three threshold levels and shows the final stylization phase when C is verified in addition to Verification A and Verification B. Since at least one element has exceeded VAL at this stage, no OBP operation is required to check for this event. Furthermore, if any bit after the OBP exceeds VCL, the VC verification is similar to the extended loop shown in Figure 18. Moreover, in the next sensing cycle, a normal cycle similar to the one shown in circle 19 will resume. The time saved and wasted by the SQPW for verification at the VC level will be calculated in a manner similar to the initial phase of stylized verification involving only Verification A before any bit exceeds VAL. While the invention has been described with respect to the specific embodiments thereof, it should be understood that BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A to 1E schematically illustrate different examples of non-volatile memory cells. Figure 2 illustrates an example of a NOR array of memory cells. Figure 3 illustrates an example of a NAND array of memory cells, such as the NAND cells shown in Figure 1D. Figure 4 illustrates the relationship between the source-drain current and the control gate voltage for four different energies 117671.doc -44 - 1328231 charge Q1 to Q4 that can be stored at any time for the floating gate. Figure 5 schematically illustrates a typical configuration of a memory array accessible by a read/write circuit via a column and row decoder. Figure 6A schematically illustrates a compact memory device having a set of read/write circuits' which provides a scenario for practicing the present invention. Figure 6B illustrates a preferred configuration of the compact memory device shown in Figure 6A. Figure 6C illustrates a preferred grouping of several sensing modules to a read/write stack. Fig. 6D schematically illustrates the overall configuration of the basic components in the read/write stack shown in Fig. 6C. Figure 7A illustrates the threshold voltage distribution of a '4 state memory array when each memory cell stores data for two bits using a conventional Gray code. Figure 7B illustrates the next page stylization using Gray code with an existing, 2-path stylization mechanism. Figure 7C illustrates the previous page stylization using the Gray code with the existing, 2-path stylization mechanism. Figure 7D illustrates the read operation required to identify the lower bits of the 4-state memory encoded in Gray code. Figure 7E illustrates the read operation required to distinguish the bits above the 4-state memory encoded in Gray code. Figure 8A illustrates the threshold voltage distribution of a 4-state memory array when each memory cell stores data for two bits using the LM code. Figure 8B illustrates the next page stylization using the LM code with an existing, 2-path stylization mechanism. Figure 8C illustrates the stylization of the upper 117671.doc • 45· 1328231 page using the LM code with the existing, 2-path stylization mechanism. Figure 8D illustrates the read operation required to identify the lower bits of the 4-state memory encoded in the LM code. Figure 8E illustrates the read operation required to distinguish the bits above the 4-state memory encoded in the LM code. Figure 9A illustrates the threshold voltage distribution of a 4-state memory array when each memory cell stores two bits of data using the LM new code. Figure 9B illustrates the next page stylization using the LM new code with the existing, 2-path stylization mechanism. Figure 9C illustrates the upsizing of the previous page using the LM new code with the existing, 2-path stylization mechanism. Figure 9D illustrates the read operation required to distinguish the bits of the 4-state memory encoded with the LM new code. Figure 9E illustrates the read operation required to distinguish the bits above the 4-state memory encoded with the LM new code. Figure 10 schematically illustrates in more detail the sensing module shown in Figure 6A suitable for sensing the memory. Figure 11 shows two distributions of memory cells with a given programmed memory state, where the more developed distribution is generated by a single path stylized at the VL level, and the tighter distribution is one with The two paths of the second path verified at the VH level are stylized. Figure 12 shows an example of a two-path stylized waveform. Figure 13 is a timing diagram for sensing in a verify operation for a path stylized operation. 117671.doc • 46- Figure 14 shows a single path stylized waveform for fast path writing. Figure 15 is a timing diagram for sensing in a verify operation of a path QPW stylization operation. Figure 16 is a flow diagram of an improved stylized verification operation in accordance with the present invention. Figure 17 is a timing diagram of SQPW verification before any bit exceeds VL. It can be considered as a shortened cyclic performance of SPQW verification and is applicable whenever no bits in the group unit have exceeded VL. Figure 18 is a timing diagram of SQPW verification for the first case where a bit exceeds VL. Figure 19 is a timing diagram of SQPW verification in a subsequent cycle just after the cycle after at least one bit has exceeded VL. Figure 20A is a timing diagram for SQPW involving three threshold levels and shows an initial stylization phase involving only verification A. Figure 20B is a timing diagram for SQPW involving three threshold levels and shows an intermediate stylization phase when verifying B is initiated in addition to Verification A. Figure 20C is a timing diagram of SQPW involving three threshold levels and shows the final stylization phase when C is verified in addition to Verification A and Verification B. [Main component symbol description] 10 Memory unit 12 Split channel 14 Source 16 Deuterium 20 Floating gate 20' Floating gate 117671.doc -47- 1328231

30 Control Gate 30' Control Gate 34 Source Line 36 Bit Line/Guide Line 40 Select Gate 42 Word Line 50 Reverse Unit/Reverse Chain 54 Source Terminal 56 汲 Extreme 100 Memory Array 130 Column Decoding 160 row decoder 170 read/write circuit 212 sense amplification 231 I/O bus bar 300 two-dimensional array of memory cells 310 control circuit 312 state machine 314 on-chip address decoder 316 power control module 330 column decoding 330A Column Decoder 330B Column Decoder 350 Block Multiplexer 117671.doc • 48- 1328231 350A Block Multiplexer 350B Block Multiplexer 360 Line Decoder 360A Line Decoder 360B Line Decoder 370 Read / Write Circuit 370A Read/Write Circuit 370B Read/Write Circuit® 411 Line 421 Stack Bus 430 Data Latch 440 I/O Module 480 Sensing Module 481 Sensing Node 482 Isolation Transistor • 486 Pull-down circuit 488 Transfer gate 490 Read/write stack 498 page controller 499 Read bus 500 Common processor 520 Latch 600 Sense amplifier 610 Bit line voltage clamp 117671 .doc -49- 1328231 630 Transistor 632 Transistor 640 Precharge/Clamp Circuit 647 Node 650 Unit Current Discriminator 651 Node SEN 660 Latch 1301 Distribution 1303 Distribution 1401 First Step PW1 1403 Second Path PW2 1501 Stylized Waveform QPW BL bit line Ml memory transistor M2 memory transistor Μ memory transistor PW1 stylized waveform PW2 stylized waveform Q1 charge Q2 charge Q3 charge Q4 charge SI source select transistor S2 drain select transistor 117671.doc -50 - 1328231 τι Τ2 ΤΙ - left ΤΙ - right WL memory transistor selection transistor memory cell storage unit word line

r: S 117671.doc -51- ~

Claims (1)

1328231, the Japanese patent application No. 095150107, the patent application for the replacement of the Chinese patent application scope (March 99) 'X. The scope of the patent application: 1 · A parallelization of the threshold voltage and a stylized 4 ^ J madness A method for a group of 800 million memory cells, comprising: (a) applying a stylized pulse to the group of memory cells. (b) a predetermined edge relative to a margin below a threshold threshold voltage Verifying the group of memory cells by the first reference threshold voltage. (4) repeating (4) to (b) until one of the first memory cells in the group of memory cells has been verified with respect to the first reference threshold voltage Lu (4) modifies a stylized setting of the first memory unit that has been verified with respect to the first reference threshold voltage to slow down the subsequent stylized speed of the first memory unit; 0) a programmed pulse is applied to the group of memory cells; (f) verifying the group of memory cells relative to the first reference threshold voltage; (g) modifying another one that has been verified with respect to the first reference threshold voltage Remember the course of the hidden body 70 Setting to slow down the subsequent stylization of the other memory unit; (h) verifying the group of memory cells relative to the threshold threshold voltage; (1) suppressing a verification that has been verified against the threshold threshold voltage Further programming of any of the group of memory cells; and G) repeating (e) through (1) until all memory cells in the group of memory cells have been programmatically verified with respect to the threshold threshold voltage. 2. The method of claim 1, further comprising: accessing the group of memory cells by means of associated bit lines; and wherein the step of 117671-990311.doc 3. = modifying - stylizing settings comprises increasing Already about this first reference... The voltage of the first memory unit or another memory that is verified by the voltage is reduced by the voltage of the 7L line to slow down the stylized speed. The method of claim 1, further comprising: accessing the group memory unit by an associated bit line; providing a power supply voltage; and wherein the /P system is verified with respect to the boundary threshold voltage The steps of the step-by-step programming of the memory group include substantially increasing the bit line of the memory-single-equivalent to the power supply voltage, and at the same time 4. The cells have their bit lines at a voltage that is essentially zero. As in the method of claim 1, the stylized pulses in # are monotonically increasing with each pulse. 5_ The method of claim 1, wherein the group of memory cells is part of a flash EEPROM. 6. In the method of requesting the item, the group memory unit is embodied in a memory card. A method for juxtaposed staging a group of memory cells relative to a threshold threshold voltage, comprising: alternately applying a stylized pulse and verifying a stylized result for the group of memory cells that are juxtaposed; a first verification that is relative to a first reference threshold voltage at a predetermined margin below a threshold of the threshold threshold voltage; the mitigation has been verified against the first reference threshold voltage The group record 117671-990311.doc -2· 1328231 remembers the stylized speed of a memory unit in the body unit; - the second verification, which is relative to the threshold voltage; and suppresses the threshold voltage relative to the boundary And verifying further programming of the memory unit; and wherein: the second verification is not performed until at least a first one of the group of memory units has been verified with respect to the first reference threshold voltage. 8. The method of claim 7, further comprising: 0 accessing the group of memory cells by the associated bit line; and wherein the modifying a stylized setting comprises raising the first reference threshold The voltage is verified by a voltage on the bit line of the memory cell to slow down the stylized speed. 9. The method of claim 7, further comprising: accessing the group of memory cells by associated bit lines; providing - a supply voltage; and wherein X is further stabilizing steps of the 忆C memory unit Included that the bit line associated with the Φ 隐 ^ hidden body 实质上 is substantially raised to the power source [when the memory cell in the group memory cell is unsuppressed, the bit 7C line is substantially Zero voltage. 10. If the request item ^, Wanfa, ♦ the stylized pulse is increasing monotonically with each pulse. 11. The #丄,芡 method of claim 7 wherein the group of memory cells is part of a flash EEPROM. 12 _ If the request item 7 _ ^, , Wanfa, where the group of memory units are reflected in a memory card" II7671-99031l.doc 1328231 13. If requested! The method of any one of 12 t, i can be programmed into one of two states by the individual memory single/0 in the memory unit of the device, and the boundary threshold voltage is used for the two The state is demarcated. 14. The method of any of the claims, wherein each of the individual memory cells in the group of memory cells is programmable to one of two or more states and the threshold threshold voltage is used to The above state is one of a plurality of boundary threshold voltages that are demarcated. 15. As requested! The method of 4, wherein the step comprises repeating the steps relative to each of the plurality of boundary threshold voltages. 16. A non-volatile memory, comprising: a program group of memory cells to be programmed with respect to a threshold threshold voltage; a stylized circuit for applying a stylized pulse to the group of memory cells a sensing circuit having a first configuration for verifying the group of memory cells with respect to a first reference threshold voltage at a predetermined margin below a threshold of the threshold threshold voltage; a memory controller; the controller alternately controls operation of the programming circuit and the sensing circuit having the first configuration until one of the group of memory cells has been verified with respect to the first reference threshold voltage So far; a stylized delay circuit for slowing down the subsequent stylized speed of any one of the memory cells of the group of memory cells that have been verified with respect to the first reference threshold voltage; JJ767J-9903H .doc - a stylized suppression circuit for suppressing a step-by-step programming of a memory cell in the group of memory cells that has been verified with respect to the threshold threshold voltage; and control The operation of the stylized circuit and the sensing circuit, the operation verifying the province 1 of the group 2 with respect to the first reference threshold voltage, and then performing the test with respect to the threshold threshold voltage until All memory cells in the group of memory cells are programmed to verify relative to the threshold threshold voltage. The non-volatile memory of claim 16, further comprising: accessing the group of memory cells by the associated bit line; and wherein the step of modifying-staging the setting comprises raising the The first - the voltage of the bit line ^ of the memory cell is verified with reference to the threshold voltage to slow down the stylized speed. 18. The non-volatile memory of claim 16, further comprising: accessing the group of memory cells by associated bit lines; and wherein the stylized suppression circuit includes the memory of rising and suppressed The bit line associated with the body cell is substantially raised to a supply voltage while the unconstrained plurality of cells have their bit line at a substantially zero voltage. 19. The non-volatile memory of claim 16, wherein the stylized pulse is monotonically increasing with each pulse. 20. The non-volatile memory of claim 6, wherein the group of memory cells is part of a flash EEPROM. 21. The non-volatile memory of claim 16, wherein the group of memory cells 117671-990311.doc 1328231 is embodied in a memory card. 22. The non-volatile memory of any one of claims 16 to 21, wherein each of the individual memory cells in the group of memory cells is programmable to one of two states and the threshold voltage is used The two states are demarcated. 23. The non-volatile memory of any one of claims 16 to 21, wherein each of the individual memory cells is each programmable to one of two or more states, and the knife boundary L voltage is used to One of a plurality of boundary threshold voltages that are delimited by two or more states. 24. A non-volatile memory, comprising: a program group of memory cells to be programmed with respect to a threshold threshold voltage; a stylized circuit for applying a stylized pulse to the group of memory cells a sensing circuit having a first configuration for verifying the group of memory cells with respect to a first reference threshold voltage at a pre-(four) limit below a threshold of the threshold threshold voltage; 4 Recalling the pirate for the parallel _ memory unit alternately applying a stylized pulse and verifying the stylized result; the verification further comprising: a first verification, which is relative to - at a threshold voltage below the threshold a first reference threshold voltage at a predetermined margin; mitigating the stylized velocity of the memory unit in the group of memory cells that have been verified relative to the first reference threshold (four); 117671 -990311.doc -6 - Lee is the threshold voltage relative to the boundary; and the D-type suppression circuit suppresses any memory that has been tested against the boundary of the threshold. Stylized; and where The second test is not performed on this Dengji 5. Until the group record has been verified with respect to the first reference threshold voltage, at least - the first one of the body. 25. The non-volatile memory of claim 24, wherein the step of: comprising: accessing the group of memory cells by a related line; and the step of Chinese & The three voltages on the bit line of the memory cell that have been verified for the first-level test threshold voltage are slowed down to slow down the stylized speed. 26. The non-volatile memory of claim 24, further comprising: accessing the group of memory cells by associated bit lines; and wherein the "red-red suppression" circuit includes an increase and the suppression The bit line associated with the memory cell to substantially raise it to a supply voltage while the group of memory is monotonically unsuppressed by the memory cell such that its bit line is substantially zero voltage . 27. The non-volatile memory of claim 24, wherein the stylized pulses increase monotonically with each pulse. 28. The non-volatile memory of claim 24, wherein the group of memory cells is part of a flash EEPROM. 29. The non-volatile memory of claim 24, wherein the group of memory cells is embodied in a memory card. 30. The non-volatile memory of any one of claims 24 to 29, wherein each of the individual memory cells in the group of memory cells is programmable to one of two states H7671-990311.doc 1328231 And the boundary threshold voltage is used to divide the two shapes. The non-volatile memory of any one of claims 24 to 29, wherein each of the individual memory cells in the group of memory cells is programmable to one of two or more states and the threshold voltage is One of a plurality of demarcation threshold voltages for demarcating the two or more states. 32. A non-volatile memory, comprising: a program group of memory cells to be programmed with respect to a threshold threshold voltage; a stylized circuit for applying a stylized pulse to a group of memory cells; a sensing circuit having a first configuration for verifying the group of memory cells with respect to a first reference threshold voltage at a predetermined margin below a threshold of the threshold threshold voltage; a member for alternately applying a stylized pulse to the parallel group of memory cells and verifying the stylized result; wherein the verification further comprises: ...the first test, which is relative to a threshold voltage lower than the boundary The margin of the limit - the first reference threshold voltage at the predetermined margin; the salt mitigation has been verified relative to the far-reference threshold voltage of the group of the memory of the early memory - 兮? Love Wei set - ϋ. The stylized speed of the early TL of the IS body; a second verification, which is relative to the threshold voltage of the boundary; and the memory of any memory that has been verified against the threshold voltage of the second system. Step stylized; and wherein: 117671-990311.doc \ C'.- 1328231 does not perform the second verification until at least one of the first group of memory cells has been verified with respect to the first reference threshold voltage until. 3 3. The non-volatile memory of claim 3, wherein each of the individual memory cells in the group of memory cells is programmable to one of two states and the threshold voltage is used for The two states are demarcated. 3 4. The non-volatile memory of claim 3, wherein each of the individual δ-resonant units in the group of memory cells can be programmed to one of two or more sulcus' and the threshold threshold voltage One of a plurality of demarcation threshold voltages for performing eight boundaries for the two or more states. 117671-990311.doc