EP1831923B1 - Method for trimming a structure obtained by the assembly of two plates - Google Patents

Method for trimming a structure obtained by the assembly of two plates Download PDF

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Publication number
EP1831923B1
EP1831923B1 EP05825588.6A EP05825588A EP1831923B1 EP 1831923 B1 EP1831923 B1 EP 1831923B1 EP 05825588 A EP05825588 A EP 05825588A EP 1831923 B1 EP1831923 B1 EP 1831923B1
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EP
European Patent Office
Prior art keywords
wafer
trimming
chemical etching
layer
pedestal
Prior art date
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EP05825588.6A
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German (de)
French (fr)
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EP1831923A1 (en
Inventor
Marc Zussy
Bernard Aspar
Chrystelle Lagahe-Blanchard
Hubert Moriceau
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Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor

Definitions

  • the Figures 1A to 1C illustrate a conventional method of manufacturing a BSOI structure.
  • the Figure 1A represents a step of the process during which a first silicon plate 1 and a second silicon plate 2 will be put in contact.
  • the contact face of the plate 2 is the free face of a silicon oxide layer 3 formed on the plate 2.
  • This silicon oxide layer may have a thickness typically between 0.3 microns and 3 microns.
  • the Figure 1B represents the two plates 1 and 2 during the step of contacting contact (called "direct bonding" in English).
  • the figure 1C represents the structure obtained after thinning of the plate 1 to provide a thin layer 4 with a thickness of, for example, between 5 ⁇ m and 100 ⁇ m.
  • the assembled silicon wafers are standard size plates (100, 125, 150, 200 or 300 mm in diameter) or any other size. They are chamfered at the edges, as is schematized (without respect of the scale) on the Figures 1A to 1C , to avoid breakage problems that may occur during component manufacturing processes on BSOI structures.
  • a trimming step is performed in order to eliminate the peripheral zone of the thin layer.
  • the clipping step is usually performed by mechanical means.
  • the figure 2 shows the structure obtained, the thin layer 5 no longer having a peripheral area unbonded.
  • the trimming step may consist in mechanically machining the edge of the plate to be thinned fixed on the support plate.
  • it is difficult to machine the top plate of the structure (i.e. the plate to be thinned) without touching or damaging the bottom plate (or backing plate).
  • the interface between the two glued plates is very precise and it is impossible to mechanically stop very safely at this interface.
  • JP-A-11-067701 proposes a first step of mechanical thinning followed, to reach the interface, of a chemical thinning.
  • the edges of plates are fragile, which can make particularly difficult handling.
  • US 2001/055854 discloses a method of manufacturing a semiconductor element and a method of manufacturing a solar cell, the method comprising the step of transferring a semiconductor layer to the portion of a second element by separating the portion of a porous layer.
  • the present invention overcomes the disadvantages of the prior art.
  • the geometry of the upper plate and / or the lower plate is used, due to chamfering, to obtain a suitable trimming.
  • An etching solution chosen to attack the top plate of the stacked structure is used. This chemical attack can be homogeneous over the entire unglued part of the upper plate of the structure or mainly located at the level of the future thin layer.
  • FIGS. 3A to 3C are cross-sectional views illustrating a first embodiment of the method according to the invention.
  • the figure 3A shows the assembly of a first plate 11 and a second plate 12 fixed to one another according to contact faces.
  • the plate 11 is a silicon wafer.
  • the plate 12 is a silicon wafer 13 covered with a silicon oxide layer 14.
  • the attachment is by a molecular bonding technique well known to those skilled in the art.
  • the adhesion is for example at room temperature, then is reinforced by a heat treatment, for example between 900 and 1200 ° C for 2 hours.
  • the heat treatment atmosphere may be argon with about 2% oxygen (i.e. 98% argon and 2% oxygen by volume).
  • the silicon plate 11 is then deoxidized to remove the native oxide, for example by HF diluted to 10%, and then etching, for example by TMAH (tetramethylammonium hydroxide) or by KOH.
  • etching for example by TMAH (tetramethylammonium hydroxide) or by KOH.
  • TMAH tetramethylammonium hydroxide
  • KOH tetramethylammonium hydroxide
  • the entire free surface of the plate 11 undergoes this chemical etching and in particular the chamfered area referenced 15 on the figure 3A .
  • the etching is carried out so as to obtain a pedestal 16 at the contact faces of the two plates, the pedestal resting entirely on the second plate 12 (see FIG. figure 3B ). If the bonding is strong enough, the width of the pedestal corresponds approximately to the bonding area of the two plates. As detailed below, the lower the gluing, the narrower the pedestal.
  • the pedestal can be obtained by etching the plate 11 to a thickness of about 80 microns.
  • TMAH can be used diluted to 25%, at a temperature of 80 ° C for 4 hours.
  • This etching solution has the advantage of having a high selectivity (greater than 1000 between silicon and silicon oxide) and therefore very little attack the oxide layer 14 of the plate 12.
  • the silicon wafer 11 already slightly thinned by the etching, is thinned by its free face, for example by a mechanical action. It can be used for this purpose a rapid grinding process (or “grinding" in English) with a grinding wheel of the order of 50 microns (reference # 325) for example. This grinding is extended by a fine break-in which consists, for example, in honing the thinned plate with a grinding wheel of the order of 8 ⁇ m (reference # 2000), or even finer. This step removes a maximum of the area hardened during the previous grinding. The thinning stage is conducted until reaching the pedestal.
  • a possible final polishing step can be used to prepare a compatible surface state, for example with epitaxy.
  • a compatible surface state for example with epitaxy.
  • Such a surface condition is called "epi-ready" by those skilled in the art.
  • the remaining thickness after the thinning operations is determined according to the thickness required for the intended application.
  • the thickness of the plate 11 attacked by the etching solution is therefore also fixed as a function of the thickness of the desired thin layer 17 (see FIG. figure 3C ).
  • the pedestal will therefore have, after the rapid rectification step, a thickness greater than the thickness of the thin layer 17. It is then found that the edges of the SOI structure obtained are clean and well defined.
  • the first plate may be made of germanium and the second plate made of silicon which may or may not be oxidized.
  • An attack by H 2 O 2 heated to 70 ° C can burn the germanium to form the pedestal (for example 60 microns in height). This attack has no effect on the second silicon plate. Thinning can then make it possible to obtain an SGOI structure, for example having a thin layer of germanium 10 to 40 ⁇ m thick.
  • FIGS. 4A to 4D are cross-sectional views illustrating a second embodiment of the method according to the invention.
  • the Figure 4A shows the assembly of a first plate 21 and a second plate 22 fixed to each other in contact faces.
  • the plate 21 is a silicon plate 23 covered with a silicon oxide layer 24.
  • the plate 22 is also a silicon plate 25 covered with a silicon oxide layer 26.
  • the silicon oxides 24 and 26 both are thermal oxides, or they are both deposited but the thickness of the oxide layer 24 is therefore lower than the thickness of the oxide layer 26.
  • the plates 21 and 22 have been fixed by a molecular adhesion technique at room temperature.
  • the adhesion is reinforced by a heat treatment, for example between 900 and 1200 ° C for 2 hours.
  • the heat treatment atmosphere may be argon with 2% oxygen (98% argon and 2% oxygen by volume).
  • a first etching is then carried out to deoxidize the free surface of the plate 21.
  • HF diluted to 10% can be used for this purpose.
  • Figure 4B shows that the free edges including the chamfered areas of the plate 21 are deoxidized.
  • a second chemical attack is then carried out using TMAH diluted to 25%, for example to reduce the silicon thickness of the plate 23.
  • the entire free surface of the silicon wafer 23 undergoes this etching and in particular the lower chamfered zone. 27.
  • the etching is carried out so as to obtain a pedestal portion 28 at the contact faces of the plates 21 and 22, the portion 28 lying entirely on the second plate 22 via the oxide layer 24. remaining (see figure 4C ). This can be obtained by etching the silicon 23 to a thickness of, for example, 80 ⁇ m.
  • the etching solution can be at a temperature of 80 ° C and the attack can last 4 hours.
  • Thinning can also be obtained by various other techniques chosen from chemical attacks or dry etchings (ionic, reactive ionic, etc.), or even "lift-off" techniques.
  • FIGS. 5A to 5C are cross-sectional views illustrating a third mode of implementation of the method according to the invention.
  • the Figure 5A shows the assembly of a first plate 51 and a second plate 52 fixed to one another according to contact faces.
  • the plate 51 comprises a support 53, for example made of silicon, successively supporting a sacrificial layer 54 and a thin layer 55. If the mine layer 55 is made of silicon, the sacrificial layer 54 may be made of porous silicon.
  • the plate 52 is a silicon plate 56 covered with a protective layer of silicon oxide 57.
  • the plates 51 and 52 have been fixed to one another by a molecular adhesion technique at room temperature, the layer thin 55 being brought into contact with the protective layer 57.
  • the Figure 5B shows the structure obtained after the chemical attack to form the pedestal. All the elements forming the plate 51 has been attacked. This figure shows that the pedestal of the first plate 51 now rests entirely on the contact face of the second plate 52.
  • the first plate is then thinned by a "lift-off" technique, selectively etching the sacrificial layer 54. If the layer 54 is made of porous silicon and the thin layer 55 is made of silicon, etching of the sacrificial layer 54 can be obtained by a mixture of water, HF and H 2 O 2 . We obtain the structure represented in Figure 5C the thin layer 55 can be further thinned, for example mechanically.
  • the temperature of the etching solution (e.g., a 25% TMAH solution) used to obtain the pedestal can be modified to change the etching rate of the first (e.g., silicon) plate.
  • the figure 6 gives the shape of the silicon etching rate curve V of the TMAH as a function of the attack temperature T.
  • the etch rate of the solution can be varied if the composition of the etching solution changes.
  • the various modes of use of this etching solution make it possible to modify the attack speed (for example the more or less important recirculation of the solution in a tank of attack, the application of megasons).
  • the silicon removal dimension (80 ⁇ m in the previous examples) can range from a few tens of micrometers to a few hundred micrometers.
  • the minimum dimension to be attained during this removal is advantageously of the order of the dimension to be attained after rapid thinning of one of the plates in order to shape the thinned portion (or thin layer) of this plate.
  • the removal dimension may be 50 ⁇ m if the thin layer to be obtained must be 20 ⁇ m.
  • the fine thinning operation is performed by having reached the pedestal.
  • the temperature of the heat treatment used to enhance the molecular adhesion can be located in a very wide range, for example greater than 100 ° C.
  • Various surface cleaning techniques can be used before adhesion: chemical surface preparation, surface activation by plasma, UV, ozone, in combination or not.
  • the adhesion can also be carried out under partial vacuum.
  • etching methods can also be chosen for etching the protective layer and / or for making the pedestal to obtain a specific plate edge required for the intended application (recess or salient).
  • the method according to the invention is suitable for producing stacked structures of the silicon-on-insulator (SOI) type with very thin film thicknesses (of the order of a micrometer to a few micrometers) up to thicknesses of several tens of micrometers, even several hundred micrometers.
  • SOI silicon-on-insulator
  • the process according to the invention can be used for silicon wafers, but also for other semiconductors (germanium, III-V semiconductors, etc.), for insulating materials (glass, quartz, ceramic, etc.). ), for piezoelectric materials (lithium niobate, lithium tantalate, etc.).

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Bending Of Plates, Rods, And Pipes (AREA)
  • Connection Of Plates (AREA)
  • Surface Treatment Of Glass (AREA)
  • Micromachines (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Description

DOMAINE TECHNIQUETECHNICAL AREA

La présente invention se rapporte à un procédé de détourage d'une structure obtenue par assemblage de deux plaques. Elle se rapporte en particulier à une structure semi-conductrice, par exemple une structure BSOI.The present invention relates to a method of trimming a structure obtained by assembling two plates. It relates in particular to a semiconductor structure, for example a BSOI structure.

ÉTAT DE LA TECHNIQUE ANTÉRIEURESTATE OF THE PRIOR ART

Aujourd'hui, dans le domaine de la microélectronique, de plus en plus de structures sont obtenues par assemblage de deux plaques en matériaux semi-conducteurs qui peuvent être totalement ou partiellement traitées. Par exemple, pour fabriquer une structure BSOI (pour « Bonded Silicon On Insulator »), deux plaques de silicium sont assemblées par adhésion moléculaire. De façon plus précise, cet assemblage comprend une étape de préparation de surface, une étape de mise en contact et une étape de traitement thermique par exemple à 1100°C durant 2 heures. Ensuite, au moins une des deux plaques est amincie par rectification et/ou polissage mécano-chimique.Today, in the field of microelectronics, more and more structures are obtained by assembling two plates of semiconductor materials that can be totally or partially processed. For example, to manufacture a BSOI (Bonded Silicon On Insulator) structure, two silicon wafers are assembled by molecular bonding. More specifically, this assembly comprises a surface preparation step, a contacting step and a heat treatment step, for example at 1100 ° C. for 2 hours. Then, at least one of the two plates is thinned by grinding and / or chemical mechanical polishing.

Les figures 1A à 1C illustrent un procédé classique de fabrication d'une structure BSOI.The Figures 1A to 1C illustrate a conventional method of manufacturing a BSOI structure.

La figure 1A représente une étape du procédé au cours de laquelle une première plaque 1 en silicium et une deuxième plaque 2 en silicium vont être mises en contact. La face de contact de la plaque 2 est la face libre d'une couche d'oxyde de silicium 3 formée sur la plaque 2. Cette couche d'oxyde de silicium peut avoir une épaisseur typiquement comprise entre 0,3 µm et 3 µm. la figure 1B représente les deux plaques 1 et 2 lors de l'étape de mise en contact adhérent (appelé « direct bonding » en anglais). La figure 1C représente la structure obtenue après amincissement de la plaque 1 pour fournir une couche mince 4 d'épaisseur comprise par exemple entre 5 µm et 100 µm.The Figure 1A represents a step of the process during which a first silicon plate 1 and a second silicon plate 2 will be put in contact. The contact face of the plate 2 is the free face of a silicon oxide layer 3 formed on the plate 2. This silicon oxide layer may have a thickness typically between 0.3 microns and 3 microns. the Figure 1B represents the two plates 1 and 2 during the step of contacting contact (called "direct bonding" in English). The figure 1C represents the structure obtained after thinning of the plate 1 to provide a thin layer 4 with a thickness of, for example, between 5 μm and 100 μm.

Les plaques de silicium assemblées sont des plaques de dimension standard (de diamètre 100, 125, 150, 200 ou 300 mm) ou de tout autre dimension. Elles sont chanfreinées sur les bords, comme cela est schématisé (sans respect de l'échelle) sur les figures 1A à 1C, afin d'éviter des problèmes de casse susceptibles de se produire au cours des procédés de fabrication de composants sur les structures BSOI.The assembled silicon wafers are standard size plates (100, 125, 150, 200 or 300 mm in diameter) or any other size. They are chamfered at the edges, as is schematized (without respect of the scale) on the Figures 1A to 1C , to avoid breakage problems that may occur during component manufacturing processes on BSOI structures.

Ces chanfreins sur les bords des plaques entraînent la présence d'une zone périphérique de la couche mince non collée sur le substrat support. Cette zone périphérique doit être éliminée car elle est susceptible de se casser de façon non contrôlée et de contaminer la structure par des fragments ou particules indésirables.These chamfers on the edges of the plates cause the presence of a peripheral zone of the thin layer not bonded to the support substrate. This peripheral zone must be removed as it is likely to break in an uncontrolled manner and contaminate the structure with unwanted fragments or particles.

Pour remédier à ce problème, on procède à une étape de détourage afin d'éliminer la zone périphérique de la couche mince. L'étape de détourage est habituellement réalisée par un moyen mécanique. La figure 2 montre la structure obtenue, la couche mince 5 ne présentant plus de zone périphérique non collée.To remedy this problem, a trimming step is performed in order to eliminate the peripheral zone of the thin layer. The clipping step is usually performed by mechanical means. The figure 2 shows the structure obtained, the thin layer 5 no longer having a peripheral area unbonded.

L'étape de détourage peut consister à usiner mécaniquement le bord de la plaque à amincir fixée sur la plaque support. Cependant, il est difficile d'usiner la plaque supérieure de la structure (c'est-à-dire la plaque à amincir) sans toucher ou endommager la plaque inférieure (ou plaque support). En effet, l'interface entre les deux plaques collées est très précise et il impossible de s'arrêter mécaniquement de façon très sûre à cette interface.The trimming step may consist in mechanically machining the edge of the plate to be thinned fixed on the support plate. However, it is difficult to machine the top plate of the structure (i.e. the plate to be thinned) without touching or damaging the bottom plate (or backing plate). Indeed, the interface between the two glued plates is very precise and it is impossible to mechanically stop very safely at this interface.

Pour pallier ce problème, le document JP-A-11-067 701 propose une première étape d'amincissement mécanique suivie, pour atteindre l'interface, d'un amincissement chimique. Cependant, entre ces deux étapes, les bords de plaques sont fragiles, ce qui peut rendre en particulier les manipulations difficiles.To overcome this problem, the document JP-A-11-067701 proposes a first step of mechanical thinning followed, to reach the interface, of a chemical thinning. However, between these two stages, the edges of plates are fragile, which can make particularly difficult handling.

Une autre possibilité consiste à usiner les bords de la plaque supérieure de la structure jusqu'à entamer sur une faible épaisseur la plaque support inférieure comme cela est illustré dans le document WO-A-96/17377 . Cet usinage entraîne cependant un état de surface dont la rugosité et le niveau de contamination particulaire n'est pas toujours compatible avec le domaine de la microélectronique. Il faut alors retraiter les bords usinés pour améliorer leur état de surface, par exemple par un polissage mécano-chimique.Another possibility consists in machining the edges of the upper plate of the structure until starting on a small thickness the lower support plate as is illustrated in the document WO-A-96/17377 . This machining, however, results in a surface state whose roughness and the level of particulate contamination is not always compatible with the field of microelectronics. It is then necessary to reprocess the machined edges to improve their surface state, for example by chemical mechanical polishing.

US 2001/055854 décrit un procédé de fabrication d'un élément semiconducteur et un procédé de fabrication d'une cellule solaire, ce procédé comprenant l'étape consistant à transférer une couche semi-conductrice sur la partie d'un second élément en séparant la partie d'une couche poreuse. US 2001/055854 discloses a method of manufacturing a semiconductor element and a method of manufacturing a solar cell, the method comprising the step of transferring a semiconductor layer to the portion of a second element by separating the portion of a porous layer.

EXPOSÉ DE L'INVENTIONSTATEMENT OF THE INVENTION

La présente invention permet de remédier aux inconvénients de l'art antérieur.The present invention overcomes the disadvantages of the prior art.

Selon l'invention, on utilise la géométrie de la plaque supérieure et/ou de la plaque inférieure, due au chanfreinage, pour obtenir un détourage adapté. On utilise une solution de gravure choisie pour attaquer la plaque supérieure de la structure empilée. Cette attaque chimique peut être homogène sur toute la partie non collée de la plaque supérieure de la structure ou principalement localisée au niveau de la future couche mince.According to the invention, the geometry of the upper plate and / or the lower plate is used, due to chamfering, to obtain a suitable trimming. An etching solution chosen to attack the top plate of the stacked structure is used. This chemical attack can be homogeneous over the entire unglued part of the upper plate of the structure or mainly located at the level of the future thin layer.

L'invention a pour objet un procédé tel que défini par la revendication indépendante 1.The subject of the invention is a process as defined by independent claim 1.

Le procédé selon l'invention permet d'obtenir le détourage le plus faible possible par rapport à la géométrie des plaques. L'opération de détourage proprement dite (correspondant à l'étape b)) est une opération de gravure chimique et non une opération mécanique. Le procédé de l'invention est également plus simple que les procédés de l'art connu puisque certaines étapes sont supprimées.The method according to the invention makes it possible to obtain the lowest possible clipping with respect to the geometry of the plates. The actual clipping operation (corresponding to step b)) is a chemical etching operation and not a mechanical operation. The method of the invention is also simpler than the methods of the prior art since certain steps are eliminated.

Différentes variantes de réalisation sont définies par les revendications dépendantes.Different embodiments are defined by the dependent claims.

BRÈVE DESCRIPTION DES DESSINSBRIEF DESCRIPTION OF THE DRAWINGS

L'invention sera mieux comprise et d'autres avantages et particularités apparaîtront à la lecture de la description qui va suivre, donnée à titre d'exemple non limitatif, accompagnée des dessins annexés parmi lesquels :

  • les figures 1A à 1C, déjà décrites, illustrent un procédé classique de fabrication d'une structure BSOI ;
  • la figure 2, déjà décrite, montre une structure BSOI détourée selon par un procédé de l'art connu ;
  • les figures 3A à 3C illustrent un premier mode de mise en oeuvre du procédé selon l'invention ;
  • les figures 4A à 4D illustrent un deuxième mode de mise en oeuvre du procédé selon l'invention ;
  • les figures 5A à 5C illustrent un troisième mode de mise en oeuvre du procédé selon l'invention ;
  • la figure 6 est un diagramme représentant la vitesse de gravure d'une solution d'attaque chimique en fonction de la température ;
  • les figures 7A à 7C illustrent un quatrième mode de mise en oeuvre du procédé selon l'invention ;
  • la figure 8 illustre une étape d'un cinquième mode de mise en oeuvre du procédé selon l'invention ;
  • la figure 9 illustre une étape d'une variante du cinquième mode de mise en oeuvre du procédé selon l'invention.
The invention will be better understood and other advantages and particularities will appear on reading the following description, given by way of non-limiting example, accompanied by the appended drawings among which:
  • the Figures 1A to 1C , already described, illustrate a conventional method of manufacturing a BSOI structure;
  • the figure 2 , already described, shows a structure BSOI cut according to a method of the prior art;
  • the FIGS. 3A to 3C illustrate a first mode of implementation of the method according to the invention;
  • the Figures 4A to 4D illustrate a second embodiment of the method according to the invention;
  • the FIGS. 5A to 5C illustrate a third embodiment of the method according to the invention;
  • the figure 6 is a diagram representing the etching rate of a chemical etching solution as a function of temperature;
  • the Figures 7A to 7C illustrate a fourth embodiment of the method according to the invention;
  • the figure 8 illustrates a step of a fifth embodiment of the method according to the invention;
  • the figure 9 illustrates a step of a variant of the fifth embodiment of the method according to the invention.

EXPOSÉ DÉTAILLÉ DE MODES DE RÉALISATION PARTICULIERSDETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

Les figures 3A à 3C sont des vues en coupe transversale illustrant un premier mode de mise en oeuvre du procédé selon l'invention.The FIGS. 3A to 3C are cross-sectional views illustrating a first embodiment of the method according to the invention.

La figure 3A montre l'assemblage d'une première plaque 11 et d'une deuxième plaque 12 fixées l'une à l'autre selon des faces de contact. La plaque 11 est une plaque de silicium. La plaque 12 est une plaque de silicium 13 recouverte d'une couche d'oxyde de silicium 14. La fixation se fait par une technique d'adhésion moléculaire bien connue de l'homme de l'art. L'adhésion se fait par exemple à température ambiante, puis est renforcée par un traitement thermique, par exemple entre 900 et 1200°C pendant 2 heures. L'atmosphère du traitement thermique peut être de l'argon avec environ 2% d'oxygène (c'est-à-dire 98% d'argon et 2% d'oxygène en volume).The figure 3A shows the assembly of a first plate 11 and a second plate 12 fixed to one another according to contact faces. The plate 11 is a silicon wafer. The plate 12 is a silicon wafer 13 covered with a silicon oxide layer 14. The attachment is by a molecular bonding technique well known to those skilled in the art. The adhesion is for example at room temperature, then is reinforced by a heat treatment, for example between 900 and 1200 ° C for 2 hours. The heat treatment atmosphere may be argon with about 2% oxygen (i.e. 98% argon and 2% oxygen by volume).

La plaque 11 en silicium subit alors une désoxydation pour éliminer l'oxyde natif, par exemple par HF dilué à 10 %, et ensuite une attaque chimique par exemple par du TMAH (hydroxyde de tétraméthylammonium) ou par du KOH. On pourrait également procéder à une gravure sèche sélective. Toute la surface libre de la plaque 11 subit cette attaque chimique et en particulier la zone chanfreinée référencée 15 sur la figure 3A. L'attaque chimique est menée de manière à obtenir un piédestal 16 au niveau des faces de contact des deux plaques, le piédestal reposant entièrement sur la deuxième plaque 12 (voir la figure 3B). Si le collage est suffisamment fort, la largeur du piédestal correspond environ à la zone de collage des deux plaques. Comme détaillé plus loin, plus le collage est faible, plus le piédestal est étroit. Le piédestal peut être obtenu par une attaque chimique de la plaque 11 sur une épaisseur de l'ordre de 80 µm. Dans le cas de l'utilisation du TMAH comme produit d'attaque chimique, on peut utiliser le TMAH dilué à 25%, à une température de 80°C pendant 4 heures. Cette solution d'attaque présente l'avantage d'avoir une forte sélectivité (supérieure à 1000 entre le silicium et l'oxyde de silicium) et attaque donc très peu la couche d'oxyde 14 de la plaque 12.The silicon plate 11 is then deoxidized to remove the native oxide, for example by HF diluted to 10%, and then etching, for example by TMAH (tetramethylammonium hydroxide) or by KOH. One could also proceed to a selective dry etching. The entire free surface of the plate 11 undergoes this chemical etching and in particular the chamfered area referenced 15 on the figure 3A . The etching is carried out so as to obtain a pedestal 16 at the contact faces of the two plates, the pedestal resting entirely on the second plate 12 (see FIG. figure 3B ). If the bonding is strong enough, the width of the pedestal corresponds approximately to the bonding area of the two plates. As detailed below, the lower the gluing, the narrower the pedestal. The pedestal can be obtained by etching the plate 11 to a thickness of about 80 microns. In the case of using TMAH as a chemical etchant, TMAH can be used diluted to 25%, at a temperature of 80 ° C for 4 hours. This etching solution has the advantage of having a high selectivity (greater than 1000 between silicon and silicon oxide) and therefore very little attack the oxide layer 14 of the plate 12.

Une fois le piédestal obtenu, la plaque de silicium 11, déjà légèrement amincie par l'attaque chimique, est amincie par sa face libre, par exemple par une action mécanique. On peut pour cela utiliser un procédé rapide de rectification par meulage (ou « grinding » en anglais) avec une meule de grain de l'ordre de 50 µm (référence # 325) par exemple. Ce meulage est prolongé par un rodage fin qui consiste par exemple à roder la plaque amincie avec une meule de grain de l'ordre de 8 µm (référence # 2000), voire plus fine. Cette étape permet de retirer un maximum de la zone écrouie lors du meulage précédent. L'étape d'amincissement est menée jusqu'à atteindre le piédestal.Once the pedestal obtained, the silicon wafer 11, already slightly thinned by the etching, is thinned by its free face, for example by a mechanical action. It can be used for this purpose a rapid grinding process (or "grinding" in English) with a grinding wheel of the order of 50 microns (reference # 325) for example. This grinding is extended by a fine break-in which consists, for example, in honing the thinned plate with a grinding wheel of the order of 8 μm (reference # 2000), or even finer. This step removes a maximum of the area hardened during the previous grinding. The thinning stage is conducted until reaching the pedestal.

Une éventuelle étape de polissage final peut être utilisée pour préparer un état de surface compatible par exemple avec une épitaxie. Un tel état de surface est appelé « epi-ready » par l'homme de l'art.A possible final polishing step can be used to prepare a compatible surface state, for example with epitaxy. Such a surface condition is called "epi-ready" by those skilled in the art.

L'épaisseur restante après les opérations d'amincissement est déterminée en fonction de l'épaisseur nécessaire à l'application visée. L'épaisseur de la plaque 11 attaquée par la solution d'attaque chimique est donc fixée également en fonction de l'épaisseur de la couche mince 17 désirée (voir la figure 3C). Avantageusement, le piédestal aura donc, après l'étape de rectification rapide, une épaisseur supérieure à l'épaisseur de la couche mince 17. On constate alors que les bords de la structure SOI obtenue sont propres et bien définis.The remaining thickness after the thinning operations is determined according to the thickness required for the intended application. The thickness of the plate 11 attacked by the etching solution is therefore also fixed as a function of the thickness of the desired thin layer 17 (see FIG. figure 3C ). Advantageously, the pedestal will therefore have, after the rapid rectification step, a thickness greater than the thickness of the thin layer 17. It is then found that the edges of the SOI structure obtained are clean and well defined.

En variante de cet exemple, la première plaque peut être en germanium et la deuxième plaque en silicium oxydé ou non. Une attaque par H2O2 chauffé à 70 °C permet de graver le germanium pour constituer le piédestal (par exemple de 60 µm de hauteur). Cette attaque n'a pas d'effet sur la deuxième plaque en silicium. L'amincissement peut ensuite permettre d'obtenir une structure SGOI, par exemple comportant une couche mince de germanium de 10 à 40 µm d'épaisseur.In a variant of this example, the first plate may be made of germanium and the second plate made of silicon which may or may not be oxidized. An attack by H 2 O 2 heated to 70 ° C can burn the germanium to form the pedestal (for example 60 microns in height). This attack has no effect on the second silicon plate. Thinning can then make it possible to obtain an SGOI structure, for example having a thin layer of germanium 10 to 40 μm thick.

Les figures 4A à 4D sont des vues en coupe transversale illustrant un deuxième mode de mise en oeuvre du procédé selon l'invention.The Figures 4A to 4D are cross-sectional views illustrating a second embodiment of the method according to the invention.

La figure 4A montre l'assemblage d'une première plaque 21 et d'une deuxième plaque 22 fixées l'une à l'autre selon des faces de contact. La plaque 21 est une plaque de silicium 23 recouverte d'une couche d'oxyde de silicium 24. La plaque 22 est également une plaque de silicium 25 recouverte d'une couche d'oxyde de silicium 26. Les oxydes de silicium 24 et 26 sont soit tous les deux des oxydes thermiques, soit ils sont tous les deux déposés mais l'épaisseur de la couche d'oxyde 24 est donc plus faible que l'épaisseur de la couche d'oxyde 26. Les plaques 21 et 22 ont été fixées par une technique d'adhésion moléculaire à température ambiante. L'adhésion est renforcée par un traitement thermique, par exemple entre 900 et 1200°C pendant 2 heures. L'atmosphère du traitement thermique peut être de l'argon avec 2% d'oxygène (98% d'argon et de 2% d'oxygène en volume).The Figure 4A shows the assembly of a first plate 21 and a second plate 22 fixed to each other in contact faces. The plate 21 is a silicon plate 23 covered with a silicon oxide layer 24. The plate 22 is also a silicon plate 25 covered with a silicon oxide layer 26. The silicon oxides 24 and 26 both are thermal oxides, or they are both deposited but the thickness of the oxide layer 24 is therefore lower than the thickness of the oxide layer 26. The plates 21 and 22 have been fixed by a molecular adhesion technique at room temperature. The adhesion is reinforced by a heat treatment, for example between 900 and 1200 ° C for 2 hours. The heat treatment atmosphere may be argon with 2% oxygen (98% argon and 2% oxygen by volume).

On procède ensuite à une première attaque chimique pour désoxyder la surface libre de la plaque 21. On peut utiliser pour cela du HF dilué à 10%. On obtient la structure représentée à la figure 4B qui montre que les bords libres y compris les zones chanfreinées de la plaque 21 sont désoxydées.A first etching is then carried out to deoxidize the free surface of the plate 21. HF diluted to 10% can be used for this purpose. We obtain the structure represented in Figure 4B which shows that the free edges including the chamfered areas of the plate 21 are deoxidized.

On procède ensuite à une deuxième attaque chimique par du TMAH dilué à 25% par exemple pour diminuer l'épaisseur de silicium de la plaque 23. Toute la surface libre de la plaque de silicium 23 subit cette attaque chimique et en particulier la zone chanfreinée inférieure 27. L'attaque chimique est menée de manière à obtenir une partie 28 de piédestal au niveau des faces de contact des plaques 21 et 22, la partie 28 reposant entièrement sur la deuxième plaque 22 par l'intermédiaire de la couche d'oxyde 24 subsistante (voir la figure 4C). Ceci peut être obtenu par une attaque chimique du silicium 23 sur une épaisseur par exemple de 80 µm. Dans le cas de l'utilisation de TMAH comme produit d'attaque chimique, la solution d'attaque peut être à une température de 80°C et l'attaque peut durer 4 heures.A second chemical attack is then carried out using TMAH diluted to 25%, for example to reduce the silicon thickness of the plate 23. The entire free surface of the silicon wafer 23 undergoes this etching and in particular the lower chamfered zone. 27. The etching is carried out so as to obtain a pedestal portion 28 at the contact faces of the plates 21 and 22, the portion 28 lying entirely on the second plate 22 via the oxide layer 24. remaining (see figure 4C ). This can be obtained by etching the silicon 23 to a thickness of, for example, 80 μm. In the case of the use of TMAH as a chemical etchant, the etching solution can be at a temperature of 80 ° C and the attack can last 4 hours.

L'étape suivante consiste à amincir la plaque de silicium 23 déjà partiellement amincie chimiquement. On peut pour cela avoir prévu dans cette plaque une zone fragile enterrée, par exemple par implantation d'espèces gazeuses (par exemple de l'hydrogène) au niveau de la face à assembler avant collage. On procède alors à une fracture au niveau de cette zone fragile enterrée, par exemple par traitement thermique et/ou mécanique.The next step is to thin the silicon plate 23 already partially chemically thinned. This can be done by providing in this plate a buried fragile zone, for example by implantation of gaseous species (for example hydrogen) at the level of the face to be assembled before bonding. This fracture zone is then broken at the level of this buried fragile zone, for example by heat and / or mechanical treatment.

Comme précédemment, la surface libre de la première plaque amincie peut être ensuite polie pour obtenir un état de surface « epi-ready ». La figure 4D montre la structure obtenue où la référence 29 désigne la partie amincie de la première plaque.As before, the free surface of the first thinned plate can then be polished to obtain an "epi-ready" surface state. The figure 4D shows the structure obtained where the reference 29 designates the thinned portion of the first plate.

L'amincissement peut être également obtenu par diverses autres techniques choisies parmi les attaques chimiques ou des gravures sèches (ionique, ionique réactive, etc...), voire les techniques de « lift-off ».Thinning can also be obtained by various other techniques chosen from chemical attacks or dry etchings (ionic, reactive ionic, etc.), or even "lift-off" techniques.

Les figures 5A à 5C sont des vues en coupe transversale illustrant un troisième mode de mise en oeuvre du procédé selon l'invention.The FIGS. 5A to 5C are cross-sectional views illustrating a third mode of implementation of the method according to the invention.

La figure 5A montre l'assemblage d'une première plaque 51 et d'une deuxième plaque 52 fixées l'une à l'autre selon des faces de contact. La plaque 51 comprend un support 53, par exemple en silicium, supportant successivement une couche sacrificielle 54 et une couche mince 55. Si la couche mine 55 est en silicium, la couche sacrificielle 54 peut être en silicium poreux. La plaque 52 est une plaque de silicium 56 recouverte d'une couche de protection en oxyde de silicium 57. Les plaques 51 et 52 ont été fixées l'une à l'autre par une technique d'adhésion moléculaire à température ambiante, la couche mince 55 étant mise en contact avec la couche de protection 57.The Figure 5A shows the assembly of a first plate 51 and a second plate 52 fixed to one another according to contact faces. The plate 51 comprises a support 53, for example made of silicon, successively supporting a sacrificial layer 54 and a thin layer 55. If the mine layer 55 is made of silicon, the sacrificial layer 54 may be made of porous silicon. The plate 52 is a silicon plate 56 covered with a protective layer of silicon oxide 57. The plates 51 and 52 have been fixed to one another by a molecular adhesion technique at room temperature, the layer thin 55 being brought into contact with the protective layer 57.

La figure 5B montre la structure obtenue après l'attaque chimique destinée à former le piédestal. L'ensemble des éléments formant la plaque 51 a été attaqué. Cette figure montre que le piédestal de la première plaque 51 repose maintenant entièrement sur la face de contact de la deuxième plaque 52.The Figure 5B shows the structure obtained after the chemical attack to form the pedestal. All the elements forming the plate 51 has been attacked. This figure shows that the pedestal of the first plate 51 now rests entirely on the contact face of the second plate 52.

On procède ensuite à un amincissement de la première plaque par une technique de « lift-off », en gravant sélectivement la couche sacrificielle 54. Si la couche 54 est en silicium poreux et la couche mince 55 en silicium, la gravure de la couche sacrificielle 54 peut être obtenue par un mélange d'eau, de HF et de H2O2. On obtient la structure représentée à la figure 5C, la couche mince 55 pouvant encore être amincie, par exemple mécaniquement.The first plate is then thinned by a "lift-off" technique, selectively etching the sacrificial layer 54. If the layer 54 is made of porous silicon and the thin layer 55 is made of silicon, etching of the sacrificial layer 54 can be obtained by a mixture of water, HF and H 2 O 2 . We obtain the structure represented in Figure 5C the thin layer 55 can be further thinned, for example mechanically.

La température de la solution d'attaque chimique (par exemple une solution de TMAH à 25%) utilisée pour obtenir le piédestal peut être modifiée pour modifier la vitesse de gravure de la première plaque (par exemple en silicium). La figure 6 donne l'allure de la courbe de vitesse de gravure V du silicium par le TMAH en fonction de la température d'attaque T.The temperature of the etching solution (e.g., a 25% TMAH solution) used to obtain the pedestal can be modified to change the etching rate of the first (e.g., silicon) plate. The figure 6 gives the shape of the silicon etching rate curve V of the TMAH as a function of the attack temperature T.

Outre la température, la vitesse de gravure de la solution peut être modifiée si la composition de la solution d'attaque change. De même, les divers modes d'utilisation de cette solution d'attaque permettent de modifier la vitesse d'attaque (par exemple la recirculation plus ou moins importante de la solution dans un bac d'attaque, l'application de mégasons).In addition to the temperature, the etch rate of the solution can be varied if the composition of the etching solution changes. Similarly, the various modes of use of this etching solution make it possible to modify the attack speed (for example the more or less important recirculation of the solution in a tank of attack, the application of megasons).

La cote d'enlèvement du silicium (80 µm dans les exemples précédents) peut aller de quelques dizaines de micromètres à quelques centaines de micromètres. La cote minimale à atteindre lors de cet enlèvement est avantageusement de l'ordre de la cote à atteindre après l'amincissement rapide de l'une des plaques en vue de mettre en forme la partie amincie (ou couche mince) de cette plaque. Par exemple, la cote d'enlèvement peut être de 50 µm si la couche mince à obtenir doit être de 20 µm. Au minimum, l'opération d'amincissement fin est effectuée en ayant atteint le piédestal.The silicon removal dimension (80 μm in the previous examples) can range from a few tens of micrometers to a few hundred micrometers. The minimum dimension to be attained during this removal is advantageously of the order of the dimension to be attained after rapid thinning of one of the plates in order to shape the thinned portion (or thin layer) of this plate. For example, the removal dimension may be 50 μm if the thin layer to be obtained must be 20 μm. At a minimum, the fine thinning operation is performed by having reached the pedestal.

Dans le cas d'une fixation par adhésion moléculaire, la température du traitement thermique mis en oeuvre pour renforcer l'adhésion moléculaire peut être située dans une gamme très large, par exemple supérieure à 100°C. Diverses techniques de nettoyage de surface peuvent être employées avant l'adhésion : préparation chimique des surfaces, activation des surfaces par plasma, UV, ozone, en combinaison ou non. L'adhésion peut aussi être effectuée sous vide partiel.In the case of binding by molecular adhesion, the temperature of the heat treatment used to enhance the molecular adhesion can be located in a very wide range, for example greater than 100 ° C. Various surface cleaning techniques can be used before adhesion: chemical surface preparation, surface activation by plasma, UV, ozone, in combination or not. The adhesion can also be carried out under partial vacuum.

La pénétration latérale de la solution d'attaque au niveau de l'interface de collage peut être modifiée en modifiant l'énergie d'adhésion des deux plaques. Une énergie plus faible entraîne une pénétration plus importante de la solution d'attaque à l'interface de collage et donc engendre un détourage par gravure chimique plus important. La couche mince obtenue a alors un diamètre plus faible. L'énergie d'adhésion peut donc être utilisée comme moyen de contrôle de la largeur de détourage.The lateral penetration of the etching solution at the bonding interface can be modified by modifying the adhesion energy of the two plates. Lower energy results in greater penetration of the etching solution at the bonding interface and therefore results in a larger chemical etch pattern. The thin layer obtained then has a smaller diameter. The adhesion energy can therefore be used as a means of controlling the clipping width.

D'autre part, la nature de la couche de protection, un oxyde dans les exemples précédents, peut être modifiée et la solution d'attaque peut être adaptée pour effectuer l'attaque latérale.On the other hand, the nature of the protective layer, an oxide in the previous examples, can be modified and the attack solution can be adapted to perform the lateral attack.

On peut également choisir ces méthodes d'attaque pour la gravure de la couche de protection et/ou pour la réalisation du piédestal pour obtenir un bord de plaque spécifique requis pour l'application visée (rentrant ou saillant).These etching methods can also be chosen for etching the protective layer and / or for making the pedestal to obtain a specific plate edge required for the intended application (recess or salient).

Les figures 7A à 7C sont des vues en coupe transversale illustrant un quatrième mode de mise en oeuvre du procédé selon l'invention. Ces figures sont à comparer aux figures 4B à 4D. Dans le cas de la figure 7A, l'abaissement de l'énergie de collage entre la première plaque 31 et la deuxième plaque 32 (par exemple plaques de silicium initialement recouvertes d'une couche d'oxyde de silicium) permet une attaque latérale de la couche de protection (dans l'exemple, de la couche d'oxyde) par la première attaque chimique plus importante que pour la structure de la figure 4B. La suite du procédé est identique au deuxième mode de mise en oeuvre. On retrouve sur la figure 7B la partie 28 de piédestal obtenue à l'issue de la deuxième attaque chimique. On retrouve sur la figure 7C la partie amincie 39 de la première plaque.The Figures 7A to 7C are cross-sectional views illustrating a fourth embodiment of the method according to the invention. These figures are to be compared to Figures 4B to 4D . In the case of Figure 7A , the lowering of the bonding energy between the first plate 31 and the second plate 32 (for example silicon wafers initially covered with a layer of silicon oxide) allows a lateral attack of the protective layer (in of the oxide layer) by the first larger chemical attack than for the structure of the Figure 4B . The rest of the process is identical to the second embodiment. We find on the Figure 7B the pedestal portion 28 obtained at the end of the second etching. We find on the Figure 7C the thinned portion 39 of the first plate.

Un cinquième mode de mise en oeuvre du procédé selon l'invention consiste à ne retirer la couche de protection (la couche d'oxyde) de la première plaque que localement, par exemple au voisinage de l'interface de collage. C'est ce que montre la figure 8. Cette figure est une vue en coupe transversale d'une structure assemblée comprenant une première plaque 41 et une deuxième plaque 42 fixées l'une à l'autre selon des faces de contact. La plaque 41 est une plaque de silicium 43 recouverte d'une couche d'oxyde 44. La plaque 42 est une plaque de silicium 45 recouverte d'une couche d'oxyde 46.A fifth embodiment of the method according to the invention consists in removing the protective layer (the oxide layer) from the first plate only locally, for example in the vicinity of the bonding interface. This is what the figure 8 . This figure is a cross-sectional view of an assembled structure comprising a first plate 41 and a second plate 42 fixed to each other according to contact faces. The plate 41 is a silicon plate 43 covered with an oxide layer 44. The plate 42 is a silicon plate 45 covered with an oxide layer 46.

La couche d'oxyde 44 de la plaque 41 a été éliminée uniquement au voisinage de l'interface de collage, ce qui a permis de réaliser une zone de pénétration localisée pour la deuxième attaque chimique (attaque chimique du silicium 43). On peut également prévoir d'ouvrir localement la partie de la couche 46 en regard de la zone ouverte de la couche 44, c'est-à-dire de part et d'autre de l'interface de fixation. C'est ce que représente la figure 9. Un trempage latéral dans une solution de HF à 10% pendant un temps calculé permet de retirer l'oxyde de protection. La structure obtenue est alors prête pour l'étape d'amincissement par exemple mécanique.The oxide layer 44 of the plate 41 was eliminated only in the vicinity of the bonding interface, which made it possible to produce a localized penetration zone for the second etching (chemical etching of the silicon 43). It is also possible to open locally the portion of the layer 46 facing the open zone of the layer 44, that is to say on either side of the attachment interface. That's what the figure 9 . Lateral dipping in a 10% HF solution for a calculated time removes the protective oxide. The structure obtained is then ready for the thinning stage, for example mechanical.

Le procédé selon l'invention est adapté à la réalisation de structures empilées de type silicium-sur-isolant (SOI) avec des épaisseurs de film superficiel très minces (de l'ordre du micromètre à quelques micromètres) jusqu'à des épaisseur de plusieurs dizaines de micromètres, voire plusieurs centaines de micromètres.The method according to the invention is suitable for producing stacked structures of the silicon-on-insulator (SOI) type with very thin film thicknesses (of the order of a micrometer to a few micrometers) up to thicknesses of several tens of micrometers, even several hundred micrometers.

Le procédé selon l'invention est utilisable pour des plaques de silicium, mais aussi pour d'autres semiconducteurs (germanium, semiconducteurs III-V, etc...), pour des matériaux isolants (verre, quartz, céramique, etc...), pour des matériaux piézoélectriques (niobate de lithium, tantalate de lithium, etc...).The process according to the invention can be used for silicon wafers, but also for other semiconductors (germanium, III-V semiconductors, etc.), for insulating materials (glass, quartz, ceramic, etc.). ), for piezoelectric materials (lithium niobate, lithium tantalate, etc.).

Claims (15)

  1. Method for trimming a structure obtained by bonding a first wafer (11, 21, 31, 41) onto a second wafer (12, 22, 32, 42) by contact faces and thinning of the first wafer, at least one of the first wafer and the second wafer being chamfered and thus exposing the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer, wherein the method comprising the following steps:
    a) selection of the second wafer (12, 22, 32, 42) to allow step b) to be carried out, said selection consisting in choosing, for the second wafer, a wafer whose surface is made of a different material from that of the surface of the first wafer and that permits selective chemical etching of the first wafer with respect to the second wafer, or a wafer (12, 22, 32, 42) with a layer (14, 26) of at least one material forming a means of stopping the chemical etching planned in step b;
    b) after bonding of the first wafer to the second wafer, lateral chemical etching of the first wafer, at the level of the bonding interface, so as to form in the first wafer a pedestal resting entirely on the contact face of the second wafer, supporting the remaining of the first wafer and set back from the flanks of the second wafer;
    c) thinning of the first wafer until the pedestal is reached so as to provide a thinned part (17, 29, 39) of the first wafer.
  2. The method for trimming of claim 1, characterized in that the first wafer, or at least its surface, being made of silicon, the second wafer is chosen from the wafers made of quartz, SiC, sapphire or substituted silicon.
  3. The method for trimming of claim 1, characterized in that the first wafer being made of silicon, the second wafer is chosen from the silicon wafers having a layer of material forming the stopping means made of SiO2 or Si3N4.
  4. The method for trimming of claim 1, characterized in that the contact face of the first wafer (21, 31, 41) has a layer (24, 34, 44) which protects against the chemical etching for forming the pedestal, wherein this protective layer is situated so as not to prevent the pedestal from being formed.
  5. The method for trimming of claim 4, characterized in that said protective layer (24, 34, 44) is a layer that initially covers the surface of the first wafer (21, 31,41), wherein the method comprises, prior to the chemical etching step to form the pedestal, chemical etching of the accessible part of the protective layer.
  6. The method for trimming of claim 5, wherein the second wafer has a layer of at least one material forming stopping means for said chemical etching, characterized in that the layer of at least one material forming the stopping means for said chemical etching, on the second wafer, and the protective layer of the first wafer are identical in nature, the layer on the second wafer being thicker than the protective layer of the first wafer.
  7. The method for trimming of claims 5, wherein the second wafer has a layer of at least one material forming stopping means for said chemical etching, characterized in that the layer of at least one material forming the means of stopping said chemical etching, on the second wafer, and the protective layer of the first wafer are different in nature, the layer on the second wafer being, in step b), etched more slowly than the protective layer of the first wafer.
  8. The method for trimming of any one of claims 1 to 7, characterized in that the first wafer (11, 21, 31, 41) is bonded onto the second wafer (12, 22, 32, 42) by a molecular adhesion technique.
  9. The method for trimming of claim 8, characterized in that the bonding energy between the first wafer (31) and the second wafer (41) is to be taken into account to obtain a determined width of the lateral chemical etching of the first wafer at the contact faces.
  10. The method for trimming of claim 1, characterized in that the first wafer is bonded onto the second wafer by means of a layer of glue.
  11. The method for trimming of claim 10, wherein the layer of glue acts as a means of stopping the chemical etching.
  12. The method for trimming of claim 1, characterized in that, as the first wafer (41) has a protective layer (44) against the chemical etching for forming the pedestal, the method thus comprises, prior to the chemical etching for forming the pedestal, chemical etching for eliminating the part of the protective layer located at the level of the future pedestal.
  13. The method for trimming of claim 12, characterized in that, as the second wafer (42) also has a protective layer (46) against the chemical etching for forming the pedestal, said chemical etching to eliminate the protective layer of the first wafer also eliminates the part of the protective layer of the second wafer that is located at the level of the future pedestal in order to create an extension of the pedestal in the second wafer.
  14. The method for trimming of one of the preceding claims, characterized in that the thinning of the first wafer is achieved by mechanical and/or chemical etching and/or "lift-off" and/or dry etching means and/or fracture at a buried fragile zone of the first wafer.
  15. The method for trimming of one of claims 1 to 14, characterized in that a polishing step is included after the thinning step.
EP05825588.6A 2004-12-28 2005-12-22 Method for trimming a structure obtained by the assembly of two plates Active EP1831923B1 (en)

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FR0413979A FR2880184B1 (en) 2004-12-28 2004-12-28 METHOD OF SORTING A STRUCTURE OBTAINED BY ASSEMBLING TWO PLATES
PCT/FR2005/051128 WO2006070160A1 (en) 2004-12-28 2005-12-22 Method for trimming a structure obtained by the assembly of two plates

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EP1831923A1 EP1831923A1 (en) 2007-09-12
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JP (1) JP5197017B2 (en)
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FR (1) FR2880184B1 (en)
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JP2008526038A (en) 2008-07-17
SG159493A1 (en) 2010-03-30
KR20070110261A (en) 2007-11-16
CN101084577B (en) 2010-06-16
US8628674B2 (en) 2014-01-14
CN101084577A (en) 2007-12-05
FR2880184A1 (en) 2006-06-30
US20090095399A1 (en) 2009-04-16
JP5197017B2 (en) 2013-05-15
KR101291086B1 (en) 2013-08-01
WO2006070160A1 (en) 2006-07-06
EP1831923A1 (en) 2007-09-12
US20130078785A1 (en) 2013-03-28
US8329048B2 (en) 2012-12-11
FR2880184B1 (en) 2007-03-30

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