EP1810147A1 - Procede et dispositif pour commuter un mode et pour comparer un signal dans un systeme de calcul comprenant au moins deux unites de traitement - Google Patents

Procede et dispositif pour commuter un mode et pour comparer un signal dans un systeme de calcul comprenant au moins deux unites de traitement

Info

Publication number
EP1810147A1
EP1810147A1 EP05797173A EP05797173A EP1810147A1 EP 1810147 A1 EP1810147 A1 EP 1810147A1 EP 05797173 A EP05797173 A EP 05797173A EP 05797173 A EP05797173 A EP 05797173A EP 1810147 A1 EP1810147 A1 EP 1810147A1
Authority
EP
European Patent Office
Prior art keywords
comparison
signal
signals
processing units
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP05797173A
Other languages
German (de)
English (en)
Inventor
Bernd Mueller
Eberhard Boehl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE200410051952 external-priority patent/DE102004051952A1/de
Priority claimed from DE200410051950 external-priority patent/DE102004051950A1/de
Priority claimed from DE200410051992 external-priority patent/DE102004051992A1/de
Priority claimed from DE200410051964 external-priority patent/DE102004051964A1/de
Priority claimed from DE200410051937 external-priority patent/DE102004051937A1/de
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1810147A1 publication Critical patent/EP1810147A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Definitions

  • a method for detecting errors in a comparison mode is described in Wo 01/46806 A1.
  • the data is processed and compared in parallel in a processing unit with two processing units ALUs.
  • both ALUs work there independently of each other until the faulty data have been removed and a repeated (partially repeated) redundant processing can be carried out. This presupposes that both ALUs work synchronously with each other and that the results can be compared in exact time.
  • Voting systems are known from the aircraft industry, which can use inputs from standard computers and process them safely by a majority decision and thus trigger safety-relevant actions.
  • a system that combines inter-processing unit and inter-control-unit communication is the FME system, which maintains the system still operational by a high degree of redundancy even in the case of single or even multiple faults and by the DASA for Space has been developed (Urban, et al: A survivable avionics System for Space applications, Int. Symposium on Fault-tolerant
  • a method for switching and signal comparison is used in a computer system having at least two processing units, wherein switching means are provided and switched between at least two operating modes, wherein Comparison means are provided and a first mode of operation corresponds to a comparison mode and a second mode of operation a performance mode, characterized in that at least two analog signals of the processing units are compared by at least one analog signal is converted into at least one digital value.
  • a method is used in which at least two of the analog signals can be asynchronous.
  • a method is used in which the digital signal is temporarily stored for a predefinable time so that a direct comparison can take place.
  • a method is used in which the conversion of at least one signal is performed in at least one processing unit.
  • a method is used in which at least one analog signal is digitally converted, stored for a predefinable time, and reconverted back to an analog signal for comparison.
  • a method is used in which the digital value of each signal comprises several bits and, depending on a predefinable precision, a correspondingly definable number of bits are compared with one another.
  • a method is used in which the analog signals and their digital values are redundantly compared with one another.
  • a method is used in which, when converting to a digital value, an identifier is assigned to the analog signal.
  • a method is used in which the identifiers of two signals which are to be compared can be assigned, and only those signals and / or their digital ones - A -
  • a device for switching and for signal comparison is used in a computer system having at least two processing units, wherein switching means are provided and switched between at least two operating modes, wherein comparison means are provided and a first operating mode corresponds to a comparison mode and a second operating mode corresponds to a performance mode, characterized in that at least two analog signals of the processing units are compared, and an analog-to-digital converter is included, wherein at least one of the analog signals is converted into at least one digital value.
  • a device in which at least two of the analog signals can be asynchronous.
  • a device in which the digital signal is temporarily stored for a predefinable time, so that a direct comparison can take place.
  • a device in which the conversion of at least one signal is performed in at least one processing unit.
  • FIG. 1 shows the basic function of a switching and comparison unit for two processing units
  • FIG. 1a shows a generalized representation of a comparator
  • FIG. 1c shows an expanded representation of a comparator
  • Figure Ib shows a generalized representation of a switching and comparison unit
  • Figure 2 shows a more detailed representation of the switching and comparison unit for two processing units
  • FIG. 3 shows a possible realization of a switching and comparison unit for two
  • FIG. 4 shows a more detailed representation of a switching and comparison unit for more than two processing units
  • FIG. 5 shows a possible implementation of a switching and comparison unit for more than two processing units
  • FIG. 6 shows a possible realization of a control register
  • FIG. 7 shows a voting unit for central voting
  • FIG. 8 shows a voting unit for decentralized voting
  • FIG. 9 shows a synchronization element
  • Figure 10 shows a handshake interface
  • FIG. 11 shows a differential amplifier
  • FIG. 12 shows a comparator for positive voltage difference
  • FIG. 13 shows a comparator for negative voltage difference
  • Figure 14 shows a circuit for storing an error
  • FIG. 16 shows the representation of a digitally converted analog value with kung and analog bit
  • FIG. 17 shows the representation of a digital value as a digital word with digital bit
  • An execution unit or processing unit can in the following include both a processor / core / CPU and an FPU (floating point unit), DSP (digital signal processor),
  • Coprocessor or ALU (arithmetic logical unit).
  • a system of two or more processing units is considered. Basically, in safety-relevant systems, it is possible to use such resources either to increase performance, by providing the various processing units as possible with different tasks. Alternatively, some of the resources can also be used redundantly by providing them with the same task and detecting an error if the result is unequal. Depending on how many processing units there are, several modes are conceivable. In a two-tier system, the two modes “comparison" and "performance" exist as described above. In a threefold system, in addition to the pure performance mode, in which all three processing units work in parallel, and the pure comparison mode, in which all three processing units are redundantly calculated and compared, one can also implement a 2out3 voting mode, in which all three Processing units redundant computing and a majority selection is made. Further, one can also realize a mixed mode using e.g. two of the processing units are redundant to each other and the
  • Results are compared while the third processing unit is processing a different, parallel task. In a four or more processing unit system obviously further combinations are conceivable.
  • each processing unit should have one own cycle can work, ie the processing of the same tasks for the purpose of comparison and asynchronous to each other can work.
  • This object is achieved in that a universal, widely deployable IP is created, which allows switching of the operating modes (eg comparison, performance or voting mode) at arbitrary times without previously switching off the processing units and possibly the comparison or the voting of each other manages asynchronous data streams.
  • This IP may be implemented as a chip, or it may be integrated with one or more processing units on a chip. Further, it is not a prerequisite that this chip consists of only one piece of silicon, it is also quite possible that this is realized from separate components.
  • a WAIT signal is usually provided. If an execution unit does not have a wait signal, it can also have a wait signal
  • the synchronization signal (e.g., M140 in Fig. 2) is not routed to a wait input but is set to an interrupt.
  • This interrupt must have a sufficiently high priority over the processing program and also against other interrupts to interrupt normal operation.
  • the associated interrupt routine only executes a certain number of NOPs (empty commands with no effect on data) before jumping back into the interrupted program, thereby delaying further processing of the processing program. If necessary, the usual memory operations at the beginning and at the end must be carried out in the interrupt routine in order not to impair the normal program execution by the interrupt.
  • the advantage of the invention is that any commercially available standard structures can be used because no additional signals are needed (no interference in the hardware structure) and any output signals of these components can be monitored, which are used for example directly to control actuators.
  • Another advantage is that not all data has to be compared in a comparison or voting mode. Only the data to be compared or voted are synchronized with each other in the switching and comparison unit. The selection of these data is variable (programmable) by the targeted response of the switching and comparison unit and can be adapted to the respective processing unit architecture as well as to the application. Thus, the use of diverse ⁇ C or software parts is easily possible, since only results that can reasonably be compared, actually compared.
  • any access to a (e.g., external) memory can be monitored, or even just driving external I / O modules.
  • Internal signals can be checked via the software-controlled additional output to the switching module on the external data and / or address bus. All control signals for the comparison operations are generated in the preferably programmable switching and voting unit and the comparison also takes place there.
  • the processing units e.g., processors
  • whose outputs are to be compared with each other may use the same program, a duplicate program (which also allows memory access error detection), or a diversified program for detecting software errors. It is not necessary to compare all the signals provided by the processing units with each other, but it is also possible to provide certain signals for comparison by means of an identifier (address or control signals) or not. This identifier is evaluated in the switching and comparison device and thus controlled the comparison. Separate timers monitor deviations in the time response beyond a specifiable limit.
  • Some or even all modules of the switching and comparison unit can be integrated on a chip, be housed on a common board or spatially separated. In the latter case, the data and control signals are interconnected via suitable bus systems replaced. On-site registers are then described via the bus system and control the operations by means of the data and / or addresses / control signals stored therein.
  • FIG. 1 shows the basic function of the switching unit BO1 according to the invention for use in conjunction with two processing units BIO and BI1.
  • Various output signals such as data, control and address signals B20 and B21 of the processing units BIO and BIl are connected to the switching unit BOl.
  • there is at least one synchronization signal in an embodiment of the arrangement according to the invention, the two output signals B40 and B41, which are connected to one of the comparison units.
  • the switching unit includes at least one control register B 15 having at least one binary bit memory element (bit) B 16 which switches the mode of the comparison unit.
  • B16 can assume at least the two values 0 and 1 and can be set or reset either by the signals B20 or B21 of the processing units or by internal processes of the switching unit.
  • the changeover unit operates in comparison mode. In this mode, all the incoming data signals from B20 are compared with the data signals from B21, provided that certain predeterminable comparison conditions of the control and / or address signals from the signals B20 and B21 are met, the validity of the data and the intended comparison for this data signal.
  • processing unit Depending on which processing unit first provides data, it must wait until the other processing unit provides the corresponding comparison data with the further processing of its program or its processes.
  • one of the signals B40 or B41 can be dispensed with if it is always ensured that the associated processing unit does not provide comparison data before the other processing unit. If B16 is set to the second value, then the synchronization signals B20 and B21 and the error signal B 17 are always inactive, for example set to the value 0. There is no comparison and both processing units work independently.
  • the comparison component M500 can be two
  • the component M500 can be executed as a so-called TSC component (totally seif checking).
  • the error signal M530 is routed to at least two lines ("dual rail") to the outside, and it is ensured by internal design and fault detection measures that in every possible error case the
  • Comparison component of this signal is correct or recognizable incorrect.
  • a preferred embodiment in the use of the system according to the invention is to use such a TSC comparator.
  • a second class of embodiments may be distinguished as to what degree of synchronicity the two inputs M510, M511 (or M610, M611) must have.
  • One possible variant is characterized by intermittent synchronicity, ie the comparison of the data can be carried out in one cycle.
  • a slight change is caused by the fact that, in the case of a fixed phase offset between the inputs, a synchronous delay element is used which transmits the corresponding signals, for example, by integer or even half Clock periods delayed. Such a phase offset is useful to avoid common cause errors, ie, those that can simultaneously affect multiple processing units.
  • a phase offset is useful to avoid common cause errors, ie, those that can simultaneously affect multiple processing units.
  • component M640 which delays the previous input by the phase offset, is therefore inserted beyond the components in FIG.
  • this delay element is accommodated in the comparator to use this element only in the comparison mode.
  • intermediate buffers can be placed in the input chain. Preferably, these are designed as FIFO memory. If such a buffer exists, one can also tolerate asynchronisms up to the maximum depth of the buffer. In this case, an error signal must be output even if the buffer overflows.
  • the comparator embodiments it can be distinguished according to how the signal M520 (or M620) is generated.
  • a preferred embodiment is to put the input signals M510, M511 (or M610, M611) on the output and to make the connection interruptible by switches.
  • the particular advantage of this variant is that the same switches can be used to switch between the performance mode and possible different comparison modes.
  • the signals can also be generated from internal comparator buffers.
  • a final class of embodiments may be distinguished as to how many inputs are present on the comparator and how the comparator should react. With three inputs, a majority voting, a comparison of all three or a comparison of only two signals can be made. With four or more inputs, correspondingly more variants are conceivable. These variants are preferably to be coupled with the various operating modes of the overall system.
  • n signals N140,..., N14n go to the switching and comparison component N100. This can generate up to n output signals N160, ..., N16n from these input signals.
  • the "pure performance mode” all signals N14i are directed to the corresponding output signals N16i.
  • the "pure comparison mode” all signals N140, ..., N14n are directed to only one of the output signals N16i .
  • the logical component of a switching logic Nl 10 is included in this figure. The component does not have to exist as such, it is crucial that its function is present. It first determines how many output signals there are. Furthermore, the switching logic Nl 10 determines which of the input signals contribute to which of the output signals.
  • the circuit logic defines a function that assigns an element of the set ⁇ N160, ..., N16n ⁇ to each element of the set ⁇ N140, ..., N14n ⁇ .
  • the function of the processing logic N120 determines to which of the outputs N16i the form in which the inputs contribute to this output signal. Also, this component does not have to exist as a separate component. It is again crucial that the functions described are implemented in the system. By way of example, to describe the various possible variations, it is assumed without loss of generality that the output N 160 is generated by the signals N141, ..., N 14m. If m
  • a first possibility is to compare all signals and to detect an error in the presence of at least two different values, which can be optionally signaled.
  • a second possibility is to make a k out of m selection (k> m / 2). This can be realized by using comparators.
  • a k out of m selection k> m / 2.
  • Error signal are generated when one of the signals is detected as different.
  • a possibly different error signal can be generated if all three signals are different.
  • a third option is to apply these values to an algorithm. This may be, for example, the formation of an average, a median, or the use of a Fault Tolerant Algorithm (FTA).
  • FTA Fault Tolerant Algorithm
  • Such an FTA is based on eliminating extreme values of the input values and performing a kind of averaging over the remaining values. This averaging can be done over the entire set of residual values, or preferably over a subset that is easy to form in HW. In this In fact, it is not always necessary to actually compare the values. For example, averaging only adds and divides, FTM, FTA, or median require partial sorting.
  • an error signal can also optionally be output here if the extreme values are sufficiently large.
  • the task of the processing logic is thus to determine the exact shape of the comparison operation for each output signal - and thus also for the associated input signals.
  • Function value is the mode information and this sets the mode. This information is of course multivalued in the general case, i. not just a logical bit. Not all the theoretically conceivable modes are useful in a given implementation, it is preferable to restrict the number of modes allowed. It should be emphasized that in the case of only two execution units, where there is only one compare mode, all the information can be condensed to only one logical bit.
  • Switching from a performance mode to a comparison mode is characterized in the general case by the fact that execution units that are displayed in the performance mode on different outputs are mapped in the compare mode to the same output.
  • this is realized by being a subsystem of
  • Execution units are in which in the performance mode, all input signals N14i, which are to be considered in the subsystem, are switched directly to corresponding output signals N16i, while in the comparison mode, all are mapped to an output. Alternatively, such switching can also be realized by changing pairings. It is represented by the fact that in the general case of the
  • Performance mode and the compare mode although in a given aspect of the invention, one can constrain the set of allowed modes such that this is the case. However, one can always speak of switching from the performance to the comparison mode (and vice versa). Between these modes can be controlled by software, dynamically switched during operation. The switching is triggered, for example, by the execution of special switching instructions, special instruction sequences, explicitly marked instructions or by the access to specific addresses by at least one of the execution units of the multiprocessor system.
  • FIG. 2 shows a detailed two-processor or two ⁇ C system with a switching and comparison unit M100 according to the invention, in which optionally also different signals can be dispensed with. It consists of two processing units (Ml 10, Ml I l) and a switching and comparison unit M100.
  • data signals (M120, M121) and address / control signals (M130, M131) go to the switching unit, and each processing unit optionally also receives data from the switching unit (M150, M151) and control signals (M140, M141).
  • the unit M100 outputs data (M160, M161) and status information M169 and receives signals such as data (M170, M171) and control signals M179, which can also be forwarded to the processing units.
  • the operating mode of the unit M100 can be set independently of the processing units; Similarly, the processors via the outputs M120, M121 (eg data bus) and the control and address signals M130, M131 (eg Write) in the unit M100 set the operating mode - eg performance mode (without comparison) or comparison mode (with
  • the outputs M120, M121 are forwarded to the outputs M 160, M161 if necessary in connection with control signals, and conversely the inputs M170, M171 to M150, M151.
  • the outputs are compared and advantageously forwarded to M 160, M 161 only in the error-free case, where either both outputs are used, or only one of them.
  • a check of input data M 170, M171 is possible, which are forwarded to the processing units.
  • an error signal is generated and -. using double-rail signals: fail-safe - signaled to the outside (component of status information M169).
  • the status M169 can also be the
  • Operating mode or information about the time offset of the signals of the execution units include.
  • the error signal is also activated.
  • the outputs M 160, M161 can be disabled (fail silent behavior). This can affect both digital and analog signals.
  • these output driver stages can also output the instantaneous (non-buffered) output signals M120, M121 of a processing unit, with the possibility of subsequent error detection. This is tolerated by a safety-relevant system as long as the fault tolerance time is not exceeded, ie the time that a (sluggish) system not yet catastrophically reacts to errors and therefore there is still the possibility of correction.
  • output signals M 180, Ml 81 which are not led to the UVE and internal signals of a processing unit can be compared, at least with respect to their calculated value, by outputting this value on the outputs M120, M121 for the purpose of comparison. The same can be done with input signals Ml 90, Ml 91, which do not come via M100.
  • FIG. 3 shows one possible implementation of the switching and comparison unit M100
  • the unit M100 contains a control register M200 with at least one bit representing the mode (performance / comparison) and a status register M220 with at least one bit representing the error status in comparison mode.
  • the wait and interrupt signals are controlled by further bits in the control register for both processing units. It is also possible between different
  • Distinguish interrupts such as for synchronization purposes, to prepare for the operation mode switching and error handling.
  • control registers e.g. M240, which contains the maximum allowed time difference (in number of clock periods) between the processing units for controlling an internal or external watchdog, as well as M241 with the
  • Time difference value (clock cycle number), from which the fastest processor is to be temporarily stopped or delayed by means of WAIT or interrupt signals, for example to prevent an overflow of data registers.
  • status register M220 e.g. In addition to the error bit also stored, how large the clock offset between the processing units is currently. For this purpose, e.g. at least one
  • Timer M230 is always started by a processing unit when a data item specially marked (via address and control signals, eg specific address range) is first provided and the value of the timer is always transferred to the status register when the corresponding data value is provided by the second processing unit.
  • the timer is preferably set so that even with different program sequences according to the WCET (worst case execution time) all processing units must supply a date. If the preset value is exceeded by the timer, an error signal is output.
  • the outputs M120, M121 of the processing units are in M100 in particular for the
  • this memory may be implemented as a FIFO. If this memory has only a depth of 1 (register), then e.g. Wait signals are used to delay the output of further values until the comparison has been made in order to avoid data loss.
  • comparison unit M210 which compares the digital data from the input memories M250, M251, the direct inputs M120, M121 or M170, M171.
  • This comparison unit may also compare serial digital data (e.g., PWM signals), e.g. in the memory unit M250, M251 can receive the serial data and convert it into parallel data, which are then compared in M210.
  • asynchronous digital input signals M 170, M 171 can be synchronized via additional memory units M270, M271.
  • the input signals 120, 121 they are preferably buffered in a FIFO. Switching between performance and compare modes is accomplished by setting or resetting the mode bit in the control register, causing e.g.
  • Synchronicity can be achieved by comparing the digital outputs of the processing units (data, address and control signals) as described above and maintaining the processing unit too fast.
  • the digital signals which are processed as the source of the analog signals in the processing unit, can also be supplied via the outputs M120, M121 to the unit M100, although these signals are otherwise not needed externally.
  • This redundant comparison in addition to the comparison of the analog signals ensures that an error in the calculation can be detected earlier and also facilitates the synchronization of the processing units.
  • the comparison of the analog signals causes additional error detection for the DAC (digital to analog converter) of the processing unit.
  • FIG. 4 shows a multiprocessor system with at least n + 1 processing units, wherein each of these components may in turn also consist of several sub-processing units (CPUs, ALUs, DSPs with corresponding additional components).
  • CPUs central processing units
  • ALUs central processing units
  • DSPs digital signal processors
  • Processing units are also connected to a switching and comparison unit, as described in the two-person system of FIG. All components and signals in this figure therefore have the same meaning in terms of content as the corresponding components and signals in FIG. 2.
  • the M300 switching and comparison unit can differentiate between the performance mode in the multiprocessor system (all
  • Processing units perform different tasks), different comparison modes (the data of two or more processing units are to be compared and in case of deviations an error should be signaled) and different voting modes (majority decision in case of deviation according to different predefinable algorithms). For Each processing unit can be decided separately in which mode it works and with which other processing units together they may operate in these modes. Exactly how the switchover takes place is subsequently explained further in the description of the control register according to FIG.
  • FIG. 5 shows a possible implementation of a switching unit for a multiprocessor system with n + 1 processing units.
  • at least one control register M44i is provided in the control unit of the switching and comparison module.
  • a preferred set of control registers is shown and described in detail in FIG. M44i corresponds to the control register Ci.
  • control register It may be described by appropriate bit combinations whether to use an error detection or fault tolerance pattern. Depending on the effort involved in the M300 unit, it is also possible to specify which type of fault tolerance pattern (2 out of 3, median, 2 out of 4, 3 out of 4, FTA, FTM 7) you want to use. Next you can make it configurable, which output one goes through. One can then also form embodiments, which components for which date can influence this configuration.
  • the output signals of the processing units involved are then compared with one another in the switching unit. Since the signals are not necessarily processed clock-accurate, a caching of the data is required. In this case, data can also be compared in the switching unit, which are given with a larger time difference from the various processing units to the switching unit.
  • an intermediate memory eg designed as FIFO memory: first in-out-of-memory or else in a different buffer form
  • a plurality of data can initially also be received by one processing unit, while other processing units do not yet provide any data.
  • a measure of the synchronicity of the two processing units is the fill level of the FIFO memory.
  • the processing unit furthest advanced in the processing is temporarily stopped either by an existing WAIT signal or by suitable interrupt routines, in order to wait for the slower processing units progressing in the processing.
  • the monitoring should be extended to all externally available signals of a processing unit; this also includes analog signals or PWM signals. In the switching unit to structures are provided which a comparison of such Allow signals. In addition, it is proposed to specify a maximum time deviation between the data to be compared and to monitor it by means of at least one timer.
  • Processing units require a control register. A specific embodiment of these control registers is explained in FIG.
  • the (n + 1) lower bits B500x to B50nx of the respective control register Cx are uniquely assigned to the n + 1 processors / processing units.
  • the bit B514x of the control register Cx switches between compare / vote on the one hand and parallel work on the other hand, and corresponds to the value of B16 of Figure 1.
  • the bit B513x indicates whether the processing unit concerned is ready for comparison, which controls bit B512x the synchronization signal (WAIT or INTERRUPT) and the bit B511x can be used to prepare the corresponding processing unit x for the comparison by an interrupt. Accordingly, the B5110x bit controls an interrupt that causes the
  • Processing unit switches back to parallel mode.
  • B50ik and B50kk of the control register Ck are set to one (0 ⁇ i, k ⁇ n).
  • a special type of vote or even a majority comparison can be determined, as already enumerated in the explanation for picture M4.
  • all bits B50ik for the processing units i to be compared / voted must be set (in the control register Ck) if the voting result is to be output at the output k of the UVE. Parallel output on other outputs is possible.
  • a one in B50ii of the control register i (0 ⁇ i, ⁇ n) indicates that the output i of the comparison unit should be active. Carry all control registers Ci only in the appropriate
  • the bit B514i in the control register Ci is set to activate the comparison or the voting. This bit may be set by the processing unit itself as well as by the switching and comparing unit depending on certain system conditions, timing conditions or other conditions (such as accessing particular memory areas, errors or implausibilities).
  • the UVE When B514i sets bits B50ii and B5 (M), the UVE automatically sets bits B51 Ii and B51 Ik, thereby triggering interrupts in processing units i and k These interrupts cause the processing units to jump to a particular program location Initiate initialization steps for the transition to the comparison mode and then issue a feedback (Ready) to the switching and comparison unit
  • the Ready signal causes an automatic resetting of the interrupt bit B511i in the respective control register Ci of the processing unit and simultaneously setting the wait bit B512i When all the wait bits of the involved processing units are set, they are simultaneously reset by the switchover and compare unit 16.
  • the processing units then start to process the program parts to be monitored Bit B514i is prevented by interlocking (HW or SW).
  • a change in the control register Ci is possible only after resetting the bit B514i.
  • This reset causes interrupts in the respective processing units by setting bits B510x in the control registers of all involved processing units to transition to normal mode (parallel operation).
  • the consistency of all control registers relative to one another is monitored in accordance with user specifications, and in the event of an error, an error signal is generated which forms part of the
  • Status information is. For example, it may not happen that one processing unit is used concurrently for multiple independent comparison or voting processes, because then the synchronization is not guaranteed. It is conceivable, however Comparison of multiple processing units without an output of the data signals, but only for the purpose of generating an error signal inequality.
  • the entry is to be made identically in several or all control registers of the processing units involved in a comparison or a voting, i. the corresponding bits of these processing units are to be set there identically, with the possible exception of their own bit i, which controls the output.
  • FIG. 7 shows the voting unit Q100 for central voting. Voting can be carried out both by means of suitable hardware and by software.
  • the voting algorithm (for example, bit-precise voting) is to be specified.
  • the voting unit Q100 receives several signals Q1, Q1, Q1, and Q112, and from these forms an output signal Q 120, which is produced by voting (for example, an m out of n selection).
  • the error bit is set in the respective control register. In a voting, the date of the processing unit concerned is ignored; in a simple comparison the output is locked.
  • a decentralized voting unit Q200 is controlled by a control unit Q210. It is connected via bus systems Q221, Q222, receives data via these bus systems and also outputs them there.
  • the reset of the comparison and voting bits in a control register with active output bit causes an interrupt in the participating processing units, which are then returned to a parallel operation.
  • each processing unit may have a different entry address, which is managed separately.
  • the program execution can also take place from the same program memory.
  • the accesses are separate and usually to different addresses. If the security-relevant part is small in comparison to the parallel modes, it must be weighed whether a separate program memory with duplicated security part may be less expensive.
  • the data memory can also be shared in performance mode.
  • Processing units work with the same or derived clocks, which are in constant phase relation to each other. If clocks of different oscillators and generators are used for the processing devices, in which the phase relationships change, then one must synchronize the signals thus generated when they change the clock domain.
  • a synchronization element M800 is shown in FIG. 9 for this purpose.
  • synchronization devices M800 are required, which can be attached anywhere in the signal flow. These once ensure the storage of data M820 with the clock M830 of the processing unit that provides this data. For reading, the clock is then used with which the date M840 is further processed.
  • Such a synchronization stage M800 can be developed as a FIFO in order to store a plurality of data (see FIG. 9). In the general case, the synchronization of the data alone is not sufficient, but it is also the sync signal of the data to synchronize with the receive clock. For this purpose, moreover, a handshake interface is required ( Figure 10) that through
  • Request signals M850 and acknowledgment signals M880 guarantees the transfer. Such an interface is necessary whenever the clock domain changes to ensure secure transmission of data from one clock domain to another.
  • the data M820 from the area Q305 are provided synchronized with the clock M830 in the register cells M800 and a write request signal M850 shows the
  • This write request signal is taken from the area Q306 with the clock M860 in a memory element M801 and as a synchronized signal M870 it indicates the provision of the data. With the next active clock edge of clock M860, the synchronized data M840 is then accepted and in the process an acknowledgment signal M880 is sent back. This confirmation signal is synchronized by the clock M830 in another memory element M801 to the signal M890 and thus the provision of the data is terminated. New data can then be written to the relevant register.
  • Such interfaces are state of the art and known and can be used in special embodiments by an additional coding work very fast, without having to wait for an acknowledgment signal.
  • the memory elements M800 are designed as FIFO memories (first-in, first-out).
  • the circuits for comparing analog signals of Figure 11 to Figure 14 assume that the processing units that provide the analog signals to be compared, are synchronized with each other so that the comparison makes sense.
  • the synchronization can be achieved by the corresponding signals B40 and B41 of FIG.
  • FIG. 11 shows a differential amplifier. With the help of this element two voltages can be compared.
  • BlOO is an operational amplifier, to the negative input BlOl a signal B 141 is connected, which is connected via a resistor Bl 10 with the value R 1n to the input signal BlI l, at which the voltage value Vi is present.
  • the positive input B 102 is connected to the
  • Signal B 142 connected via the resistor B 120 with the value R 1n to the input B 121, at which the voltage value V 2 is applied.
  • the output B 103 of this operational amplifier is connected to the output signal B 190 having the voltage value V 0Ut .
  • the signal B190 is f B140 via the resistor of value R connected to the signal and the signal B141 B142 B130 is f via the resistor of value R with the
  • V 0nJ R f Z R j n (V 2 - V 1 ).
  • the analog ground V agn ( j is a voltage between the operating voltage and the digital ground, usually the mean potential.) If the two analog input voltages Vi and V 2 only slightly different, the output voltage V out will have only a small difference V ⁇ ff to the analog ground (positive or negative).
  • the input signal B221 is connected via the resistor B150 with the value Ri to the signal B242, which is connected to the positive input B202 of the operational amplifier B200 is connected. Furthermore, the signal B242 is connected via the resistor B 160 with the value R 2 to the signal B231, which is used as the digital reference potential V dgng .
  • the negative input B201 of the operational amplifier is connected to the input signal 211, which carries the voltage value of a reference voltage V ref .
  • the output B203 of the operational amplifier B200 is connected to the output signal B290, which is the
  • the input signal B321 is connected through the resistor B 170 of the value R 3 to the signal B342 which is connected to the negative input B301 of the operational amplifier B300.
  • This signal B342 is further connected via the resistor B 180 with the value R4 to the signal B331, which is also the digital
  • Reference potential V dgnd carries.
  • the positive input B302 of the operational amplifier B300 is connected to the input signal B311 which carries voltage value of a reference voltage V ref .
  • the output B303 of the operational amplifier B300 is connected to the output signal B390, which is the voltage value
  • V ref (V agnd + V 1U a) * R 2 / (R 1 + R 2 ) (2)
  • V- ( - VdM) * R / (R 3 + R 4 ) (3)
  • V d i ff ((V 2max - V lmin ) * R f / R ta ) - V agnd (4)
  • V 2max denotes the maximum tolerated voltage value of V 2 at signal B 121 and Vi m i n the minimum tolerated voltage value of Vi at signal Bl I l.
  • the reference voltage source can be provided externally, or by an internally realized bandgap (temperature compensated and operating voltage independent
  • the maximum tolerated difference V d i ff is determined from the maximum positive deviation V 2max and the associated maximum negative deviation Vi n J n , ie (V 2max - Vi n J n ) is the maximum tolerated voltage deviation of redundant analog Signals to each other to be compared with each other.
  • V o ben or Vun te n If one of the voltage values at the two signals B290 or B390 (V o ben or Vun te n) becomes positive, there is a greater deviation of the analog signals than it should be tolerated. Insofar as the processors which supply these analog signals are synchronized, there is thus an error which must be stored and possibly leads to the switching off of the output signals.
  • the synchronicity is given, for example, when the ready signal in the control register of the corresponding processing units is active, or certain digital signals are sent to the UVE, which signal a particular state of the relevant analog signal and thus also the value to be compared in the sense of an identifier.
  • a circuit which stores the error is shown in FIG. In this circuit are the two input signals
  • NOR circuit logical OR circuit with subsequent inversion
  • This signal B411 is combined with the input signal B421 in another NOR element B420 to the output signal B421.
  • This signal B421 is linked in an OR circuit B430 with the signal B401 to the signal B431, which serves as an input signal for the memory element (D flip-flop) B400.
  • the output signal B401 of this element B400 indicates an error with the value 1.
  • the D flip-flop B400 stores with the clock B403 is a 1 if one of the two voltage values V, thus contributes positively bottom or V at the top on the signals B390 or B290 as a digital signal the value is high, the signal B421 is not active and no reset signal B402 is present. The error remains stored until the signal Reset was active at least once.
  • Signal B402 resets a previous error and therefore allows a new comparison.
  • Figure 15 shows an ADC.
  • This ADC may vary depending on the existing requirements, e.g. in terms of conversion speed, accuracy, resolution, noise immunity, linearity and
  • Frequency spectrum can be realized with the various known conversion methods. For example, one can choose the principle of successive approximation, where one compares the analog signal with a generated signal from a digital-to-analog converter (DAC) by means of a comparator, wherein the digital input bits of the DAC systematically from the MSB (most significant bit - most significant bit) to LSB (least significant bit) is set to high as a test and reset immediately if the DAC's analog output signal is higher than the analog input signal (the signal to be converted).
  • the DAC controls with its digital bits from the LSB to the MSB either resistors or capacitances with the weights 1, 2, 4, 8, 16, ...
  • converters can be used according to the counting principle, for example, by means of the input voltage or the input current cause a corresponding constant charging or discharging a capacitor connected to an integrator.
  • the time required for this is measured and set in relation to the time required in the opposite direction to discharge or charge the same capacitor (integrator) by means of a reference voltage source or a corresponding reference current.
  • the time unit is measured in cycles and the number of clocks required is a measure of the analog input value.
  • Such a method is, for example, the dual-slope method in which the one slope is determined by the discharge corresponding to the analog value and the second edge is determined by the recharge according to the reference value (see also http://www.exstrom.com /journal/adc/dsadc.html).
  • the ADC B600 of FIG. 15 is controlled by a trigger signal B602, which is typically an output signal of the processor providing the analog signal and optionally an identifier B603 which provides information about the type of analog signal being provided to distinguish it from allow multiple analog signals.
  • a trigger signal B602 is typically an output signal of the processor providing the analog signal and optionally an identifier B603 which provides information about the type of analog signal being provided to distinguish it from allow multiple analog signals.
  • the converted analog word is transferred to the memory area B640 as
  • Digital value is taken into a register B610 and optionally together with the identifier B603, which is stored in B620 and possibly an additional signal B604 (which is 1 for the marking of an analogue value), which is stored in the memory B630.
  • the memory area B640 can advantageously also be realized as a FIFO (first-in, first-out) if a plurality of values are to be stored and the first stored value is also to be re-evaluated first.
  • Both B602 and B603 are part of the digital output data O 1 of a processor i.
  • the parts of the stored digitized analog value are shown separately as they are stored in the Speichj er Scheme.
  • B710 is the digitized analog value itself
  • B720 is the associated identifier
  • B730 is the analog bit, which in this case is to be stored as 1.
  • FIG. 17 shows a variant of a digital value stored in the same memory area.
  • the digital value itself is stored, in B820 an optiona option is provided which, for example, indicates whether the digital value is to be compared at all or whether it may also contain further conditions for the comparison.
  • the value 0 is then stored to indicate that it is a digital value.
  • the sequence of the storage and possibly the A bit (B730 or B830) as well as the identifier B720 or B820 in conjunction with the converted digital value B710 or the digital value B810 are checked.
  • the comparison is then event-controlled: whenever a value of a processor is transmitted to the UVE, it is checked whether the other participating processors have already provided such a value. If this is not the case, the value is stored in the corresponding FIFO or memory, in the other case, the comparison is carried out directly, in which case the
  • FIFO can serve as memory. For example, a comparison is always completed if the FIFOs involved are not empty. If there are more than two processors or comparison signals involved, it can be determined by a voting whether all signals are permitted for distribution (fail silent behavior) or whether the error status is signaled only by an error signal.

Abstract

L'invention concerne un procédé et un dispositif pour commuter et pour comparer un signal dans un système de calcul comprenant au moins deux unités de traitement, des organes de commutation étant utilisés et la commutation étant effectuée entre deux modes de fonctionnement. Les organes de comparaison sont utilisés et un premier mode de fonctionnement correspond à un mode de comparaison et un second mode de fonctionnement correspond à un mode de performances. Ledit procédé et le dispositif sont caractérisés en ce qu'au moins deux signaux analogiques des unités de traitement peuvent être comparés, au moins un signal analogique pouvant être modifié en une valeur numérique.
EP05797173A 2004-10-25 2005-10-25 Procede et dispositif pour commuter un mode et pour comparer un signal dans un systeme de calcul comprenant au moins deux unites de traitement Ceased EP1810147A1 (fr)

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DE200410051952 DE102004051952A1 (de) 2004-10-25 2004-10-25 Verfahren zur Datenverteilung und Datenverteilungseinheit in einem Mehrprozessorsystem
DE200410051950 DE102004051950A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Taktumschaltung bei einem Mehrprozessorsystem
DE200410051992 DE102004051992A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Verzögerung von Zugriffen auf Daten und/oder Befehle eines Mehrprozessorsystems
DE200410051964 DE102004051964A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Überwachung einer Speichereinheit in einem Mehrprozessorsystem
DE200410051937 DE102004051937A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Synchronisierung in einem Mehrprozessorsystem
DE102005037242A DE102005037242A1 (de) 2004-10-25 2005-08-08 Verfahren und Vorrichtung zur Umschaltung und zum Signalvergleich bei einem Rechnersystem mit wenigstens zwei Verarbeitungseinheiten
PCT/EP2005/055517 WO2006045789A1 (fr) 2004-10-25 2005-10-25 Procede et dispositif pour commuter un mode et pour comparer un signal dans un systeme de calcul comprenant au moins deux unites de traitement

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