Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/1629—Error detection by comparing the output of redundant processing systems
  • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/1695—Error detection or correction of the data by redundancy in hardware which are operating with time diversity
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
  • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
  • G06F11/184—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30181—Instruction operation extension or modification
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30181—Instruction operation extension or modification
  • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
  • G06F2201/845—Systems in which the redundancy can be transformed in increased performance
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
  • G06F2201/86—Event-based monitoring

Definitions

• ABS system is switched off.
• Essential components of a microcontroller are on the one hand memory modules (for example RAM, ROM, cache), cores and the input / output interfaces, the so-called peripherals (e.g.
• a / D converter, CAN interface Since memory elements can be effectively monitored with check codes (parity or ECC), and peripherals are often monitored application specific as part of a sensor or actuator signal path, another redundancy approach is doubling the cores of a microcontroller alone.
• Such microcontrollers with two integrated cores are also known as dual-core architectures. Both cores execute the same program segment redundantly and in isochronous mode (lockstep mode), the results of the two cores are compared, and an error is then detected in the comparison for consistency. This configuration of a dual-core system may be referred to as a compare mode.
• Dual-core architectures are also used in other applications to increase performance, ie to increase performance. Both cores execute different programs, program segments, and instructions, which can improve performance, so this configuration of a dual-core system can be referred to as a performance mode. This system is also referred to as a symmetric multiprocessor system (SMP).
• SMP symmetric multiprocessor system
• SMP Multiprocessor System
• a method for switching in a computer system having at least two execution units, wherein at least two operating modes are switched and the operating modes correspond to states of the computer system, wherein a first state corresponds to a comparison mode and a second state corresponds to a performance mode in which events can occur which can get the computer system in an otherwise undefined state characterized in that upon occurrence of each such event, the second state corresponding to a performance mode is adopted.
• a further method is used, characterized in that the second state is determined by a content of a memory, in particular a register, and when such an event occurs, this content of the memory is evaluated.
• a method is additionally used, characterized in that the content of the memory corresponds to at least one bit, wherein a value of the at least one bit is ensured by hardware measures and is thereby retained or restored even in an otherwise undefined state.
• one further uses a method in which a switchover takes place during operation of the computer system.
• a method is used in an above form in which the event by which an undefined state can be achieved is an event triggering a reset of at least one execution unit or the computer system.
• a method is used in an above form in which the event, by which an undefined state can be achieved, is an event that triggers the starting or restarting of at least one execution unit or the computer system.
• a method is used in an above form in which the event by which an undefined state is achievable is an event in which an identification of at least one execution unit of the computer system fails when switching from the first state to the second state ,
• a device for switching over in a computer system having at least two execution units, wherein at least two operating modes are switched over and the operating modes correspond to states of the computer system, wherein a first state is a comparison mode and a second state is one - A -
• Performance mode corresponds, whereby events may occur, by which the computer system can reach an otherwise undefined state, characterized in that there are means which are designed such that upon occurrence of each such event, the second state is taken, which corresponds to a performance mode.
• one further uses a device which contains a memory, in particular a register, and in which the second state is determined by a content of the memory and when such an event occurs, this content of the memory is evaluated.
• a device is used for switching between at least two operating modes of a computer system which corresponds to a state machine.
• FIG. 1 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a comparison unit G20, a switching unit G50 and a unit for switching request recognition G40.
• FIG. 2 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a combined comparison and switching unit G70 comprising a comparison unit G20 and a switching unit G50 and a unit for switching request recognition G40.
• FIG. 3 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a combined switchover request recognition, comparison and switchover unit G80 consisting of a comparison unit G20 and a switching unit G50 and a unit for switching request recognition G40.
• FIG. 4 shows a multiprocessor system G200 with two execution units G210a, G210b of a switching and comparison unit G260.
• FIG. 5 shows in a flow chart a method which, within a specific pipeline stage G230a, G230b, exchanges a special undefined bit combination with a NOP or other neutral bit combination.
• FIG. 6 shows a multiprocessor system H200 with two execution units H210a, H210b and a switching and comparison unit H260.
• FIG. 7 shows in a flow chart a method which shows how, with the aid of the unit ID, the program flow can be changed from one comparison mode to another
• Performance mode can be separated in a multiprocessor system with 2 execution units.
• FIG. 8 shows a possible method, such as the program flow when changing from a comparison mode to a performance mode in one using the unit ID
• Multiprocessor system can be separated with 3 execution units.
• FIG. 9 shows in a flow chart a method which synchronizes the execution units when switching from the performance mode to the comparison mode.
• FIG. 10 shows a state machine which represents the switching between a performance and a comparison mode.
• FIG. 11 shows a multiprocessor system G400 with two execution units and two interrupt controllers G420a, G420b including interrupt masking registers contained therein
• G430a, G430b and various interrupt sources G440a to G440n are provided.
• FIG. 12 shows a multiprocessor system with two execution units, a switching and comparison unit and an interrupt controller with three register sets.
• FIG. 13 shows the simplest form of a comparator.
• Figure 14 shows a comparator with a unit to compensate for a phase offset.
• FIG. 15 describes the basic behavior of the preferred component M700 (switching and comparison unit) in the comparison mode.
• FIG. 16 describes the basic behavior of the preferred component M700 (switching and comparison unit) in the performance mode.
• FIG. 17 shows an embodiment of the switching and comparison unit.
• FIG. 18 shows a further embodiment of the switching and comparison unit.
• a switching and comparing unit which generates a mode signal is shown.
• FIG. 20 shows a general representation of a switching and comparison unit.
• Figure 21 shows a general representation of a switching and comparing unit which generates a general mode and a general error signal.
• FIG. 22 shows the question of response communication with an external unit.
• FIG. 23 shows the communication with an intelligent actuator.
• both a processor, a core, a CPU, as well as an FPU (floating point unit), a DSP (digital signal processor), a coprocessor or an ALU (arithmetic logical unit) may be referred to as the execution unit.
• the execution unit 1 shows a multiprocessor system G60 with two execution units GlOa, GlOb a comparison unit G20, a switching unit G50 and a unit for Umschalt whyerkennung G40 shown.
• the invention relates to a multiprocessor system G60 shown in FIG. 1, FIG. 2,
• FIG. 3 with at least two execution units GlOa, GlOb, a comparison unit G20, a switching unit G50 and a unit for Umschalttiererkennung G40.
• the switching unit G50 has at least two outputs to at least two system interfaces G30a, G30b. Registers, memories or peripherals such as digital outputs, D / A converters and communication controllers can be controlled via these interfaces. This
• Multiprocessor system can be operated in at least two modes of operation, a comparison mode (VM) and a performance mode (PM).
• VM comparison mode
• PM performance mode
• each execution unit GlOa, GlOb is connected to a system interface G30a, G30b.
• the execution unit GlOa is connected to the system interface G30a and the execution unit GlOb is connected to the system interface G30b.
• comparison mode identical or similar instructions, program segments or programs are executed in both execution units GlOa, GlOb. Conveniently, these commands are executed isochronously, but it is also a processing with asynchrony or a defined clock skew conceivable.
• the output signals of the execution units GlOa, GlOb are compared in the comparison unit G20. If there is a difference, an error is detected and suitable measures can be taken. These measures can trigger an error signal, initiate error handling, operate switches or a combination of these and other conceivable measures.
• the switching unit G50 is configured in a variation such that only one signal is connected to the system interfaces G30a, G30b. In another configuration, the
• the switchover request detection G40 detects a switchover to another mode, regardless of the currently active mode.
• FIG. 2 shows a multiprocessor system G60 with two execution units GlOa, GlOb of a combined comparison and switching unit G70 comprising a comparison unit G20 and a switching unit G50 and a unit for switching request recognition G40.
• the switching unit G50 and the comparison unit G20 can be used to form a common switching and comparison unit
• UVE G70 be summarized, as shown in Figure 2. This common component G70 then takes over the tasks of the individual components G50, G20. In FIG. 15, FIG. 16, FIG. 17, FIG. 18 and FIG. 19, variant embodiments of UVE G70 are shown.
• Umschaltkyerkennung G40, the comparator G20 and the switching unit G50 be combined in a common component G80.
• the switching request recognition G40 and the comparator G20 can be combined in a common component.
• a summary Umschaltmenterkennung G40 with the switch G50 in a common component is also conceivable.
• n signals N 140,..., N14n go to the switching and comparison component N100. This can be up to n output signals N160, ..., N16n from these
• the "pure performance mode” all signals N14i are directed to the corresponding output signals N16i.
• the "pure comparison mode” all signals N140, ..., N14n are directed to only one of the output signals N16i .
• the switching logic Nl 10 first determines how many output signals there are. It also determines which of the input signals contribute to which of the output signals. An input signal can contribute to exactly one output signal.
• the circuit logic defines a function that assigns an element of the set ⁇ N160, ..., N16n ⁇ to each element of the set ⁇ N140, ..., N14n ⁇ .
• the processing logic N120 determines to each of the outputs N16i how the inputs contribute to that output signal. Also, this component does not have to exist as a separate component. It is again crucial that the functions described are implemented in the system.
• a first possibility is to compare all signals and to detect an error in the presence of at least two different values, which can be optionally signaled.
• a second possibility is to make a k out of m selection (k> m / 2). This can be realized by using comparators.
• an error signal can be generated if one of the signals is detected as deviating.
• a possibly different error signal can be generated if all three signals are different.
• a third option is to apply these values to an algorithm.
• This may be, for example, the formation of an average, a median, or the use of a Fault Tolerant Algorithm (FTA).
• FTA Fault Tolerant Algorithm
• Such an FTA is based on eliminating extreme values of the input values and a way of averaging over the remaining values make. This averaging can be done over the entire set of remaining values or preferably over a subset that is easy to form in HW. In this case, it is not always necessary to actually compare the values. For example, averaging only adds and divides, FTM, FTA, or median require partial sorting. If necessary, an error signal can optionally also be output at sufficiently large extreme values.
• the task of the processing logic is thus to determine the exact shape of the comparison operation for each output signal - and thus also for the associated input signals.
• the combination of the information of the switching logic Nl 10 (i.e., the above-mentioned function) and the processing logic (i.e., the determination of the comparison operation per output signal, i.e. per function value) is the mode information and sets the mode. This information is of course multivalued in the general case, i. not just a logical bit. Not all the theoretically conceivable modes are useful in a given implementation, it is preferable to restrict the number of modes allowed.
• Switching from a performance mode to a comparison mode is characterized in the general case by the fact that execution units that are displayed in the performance mode on different outputs are mapped in the compare mode to the same output. This is preferably realized in that there is a subsystem of execution units in which in the performance mode all input signals N14i to be considered in the subsystem are switched directly to corresponding output signals N16i, while in the comparison mode they are all mapped to one output. Alternatively, such switching can also be realized by changing pairings.
• the switching is triggered either by the execution of special Switching instructions, special instruction sequences, explicitly marked instructions or by accessing specific addresses by at least one of the execution units of the multiprocessor system.
• the error circuit logic N 130 collects the error signals, for example from the
• Comparators are generated, and optionally the outputs N16i passively switch, for example, by interrupting them via a switch.
• the switching between the modes can be coded by various methods.
• special switching commands are to be used, which are detected by the switching request recognition unit G40.
• Another possible method for coding the switching is defined by the access to a special memory area which again detects the unit for switching request recognition G40.
• the following describes a method that uses unused bit combinations in the existing instruction set of the processor.
• a particular advantage of this method is that existing development environments (assembler,
• Compiler, linker, debugger can continue to be used.
• FIG. 4 shows a multiprocessor system G200 with two execution units G210a, G210b and a switching and comparison unit G260.
• undefined bit combinations of the at least two execution units G210a, G210b are used in the assembler.
• Undefined or undefined bit combinations in this sense are to be understood as meaning all bit combinations which are specified as undefined or illegal in the description of the instruction set. These are e.g. Illegal Operand, Illegal Instruction, Illegal Operation. General characteristic of these undefined bit combinations is that a normal
• Execution unit in the execution of such a bit combination either generates an error signal or shows an undefined behavior. So these bit combinations are not needed to represent the semantics of an ordinary program.
• the previous development environment can be used, as it exists for single-processor systems. This can be realized, for example, by defining a macro "SWITCH MODE TO PM" and a macro "SWITCH MODE TO VM", which inserts appropriate undefined 5-bit combinations at the appropriate place in the code in the sense defined above.
• SWITCH switchover mode
• the switchover request is coded by a bit combination not defined in the instruction set. These may not be processed in the usual way within an execution unit G210a, G210b. For this reason, an additional pipeline stage
• REPLACE stage G230a, G230b, which recognizes the corresponding bit combinations and replaces them for further processing by neutral bit combinations. Conveniently, this is done using the "NOP" (No Operation) command, which is characterized by the fact that it does not change the internal state of the execution unit, except for the O_instruction pointer, the REPLACE stage G230a, G230b being after the first one Stage, the FETCH stage G220a G220b and before the remaining pipeline stages G240a, G240b are inserted in the assembler undefined bit combinations, which are summarized here in one unit.
• NOP No Operation
• Umschaltky-erkennung G40 as a special pipeline stage G230a, G230b in a pipeline unit G215a, G215b, generate additional signals G250a, G250b when a corresponding bit combination was detected for switching, which signals a separate switching unit and comparison unit G260 that a change of O processing mode is performed.
• the REP stages G230a, G230b are preferably arranged between the FET G220a, G220b and the remaining pipeline stages G240a, G240b in the pipeline units G215a, G215b of the execution units G210a, G210b. Recognize REP levels G230a, G230b in this case, the corresponding bit combinations and in this case forward NOP commands to the remaining stages G240a, G240b. At the same time, the respective signal G250a or G250b is activated. In all other cases, the REP stages G230a, G230b behave neutrally, ie all other commands are passed on unchanged to the remaining stages G240a, G240b.
• FIG. 5 shows in a flow chart a method which, within a specific pipeline stage G230a, G230b, exchanges a special undefined bit combination with a NOP or other neutral bit combination.
• an instruction i. a bit combination fetched from the memory.
• block G310 a distinction is made as to whether the fetched bit combination corresponds to the specific undefined bit combination which encodes a switchover. If this is not the case, in the next step G320 the bit combination is transferred without change to the remaining pipeline stages G340 for further processing. If the particular bit combination encoding a switch was detected in step G310, in step G330 it is replaced with the NOP bit combination and then passed to the further pipeline stages G340 for further processing.
• the blocks G310, G320, G330 represent the functionality of a REPLACE stage G230a, G230b according to the invention, which may also contain further functionality.
• FIG. 6 shows a multiprocessor system H200 with two execution units H210a, H210b and a switching and comparison unit H260.
• the components H220a, H220b, H240a, H240b have the same meaning as G220a, G220b, G240a, G240b.
• the unit for switching request recognition G40 described here by the special pipeline stages H230a, H230b, this has in addition to the signals H250a,
• the pipeline units H215a, H215b of the execution units H210a, H210b each have a signal input H280a, H280b, with which the processing can be stopped. This signal is used by the H260 switching and comparison unit
• Pipeline H215a or H215b set which has first detected a switching command and thus the signal H250a or GH50b has activated. Only when both pipeline units H215a, H215b of the execution units H210a, H210b have recognized the switchover command and have synchronized their internal states by means of software or other hardware measures this signal H280a, H280b withdrawn. When switching from the comparison mode to the performance mode, the H280a, H280b are not needed because no synchronization is necessary.
• each execution unit can determine its individual number or unit ID.
• ID unit a unit or method by which each execution unit can determine its individual number or unit ID.
• one execution unit can determine the number 0 for itself and the other the number 1.
• the numbers are assigned or determined accordingly. This ID does not differentiate between one
• the ID unit may be included in the respective execution units, for example implemented as a bit or bit combination in the processor status register or as a separate register or as a single bit or as an external unit to the execution units which provides a corresponding ID upon request.
• the comparison unit is no longer active, but the execution units still execute the same instructions. This is because the instruction pointers that mark the location in the program where an execution work is currently working or is currently working in the next step are not affected by the switchover. So that the execution units can subsequently execute different software modules, the program sequence of the execution units must be separated. Accordingly, the instruction pointers in the performance mode generally have different values, since according to the invention independent instructions, program segments or
• Programs are processed.
• the separation of the program flows is done in the proposal described here by determining the respective execution unit number.
• the execution unit executes a specific software module. Since each execution unit has an individual number or ID, the program flow of the participating execution units can thereby be reliably separated.
• FIG. 7 shows in a flow chart a method which shows how, with the aid of the unit ID, the program flow can be changed from one comparison mode to another Performance mode can be separated in a multiprocessor system with 2 execution units.
• the units ID or execution unit number G510 are queried by both execution units.
• the execution unit 0 is assigned the execution unit number 0, the execution unit 1 the execution unit number 1.
• the determined execution unit number is compared with the number 0. If these are the same, the execution unit moves in step G520 This comparison succeeded, with the code for execution unit 0 gone.
• the execution unit for which this comparison was unsuccessful continues in G530 with the comparison with the number 1. If this comparison is successful, the execution unit 1 code continues in G540. If this comparison is unsuccessful, an execution unit number not equal to 0 and 1 was determined for the corresponding execution unit. This represents an error and continues with G550.
• FIG. 8 describes a possible method for 3 execution units. After performing the switchover from a compare mode to a performance mode H500, the units ID or execution unit number H510 is queried by the execution units. According to the invention, for example, the execution unit 0, the execution unit number 0 received, the execution unit 1 the
• Execution unit number 1 and execution unit 2 the execution unit number 2.
• the determined execution unit number is compared with the number 0. If these are the same, in step H520 the execution unit for which this comparison was successful moves with the code for execution unit 0 continued. The execution units for which this comparison was unsuccessful continue to compare with # 1 in H530. In the execution unit for which this comparison is successful, the code for execution unit 1 in H540 is continued. The execution units for which this comparison was unsuccessful continue to compare with number 2 in H535. The execution unit for which this comparison succeeds continues with the execution unit 2 code in H536. If this comparison was unsuccessful, an execution unit number not equal to 0.1 and 2 was determined for the corresponding execution unit. This is an error and H550 will continue. Alternatively to the comparison with a number, the determined execution unit number can also be used directly as an index in a jump table.
• this method can also be used for multiprocessor systems with more than 3 execution units.
• FIG. 9 shows in a flow chart a method which synchronizes the execution units when switching from a performance mode to a comparison mode.
• Step G600 preferably all interrupts are disabled. This is not only important because the interrupt controllers for the compare mode must be reprogrammed accordingly. Software should also be used to adjust the internal status of the execution units. However, if an interrupt is triggered during the preparation for switching to the comparison mode, then an adjustment is no longer possible without further effort.
• Step G610 If the two execution units have separate caches, the contents of the caches must also be adjusted before the switchover in order to prevent a cache hit in the comparison mode for an address for the one execution unit and a cache miss for another execution unit occurs. If this is not done independently by the cache hardware, this can be done by marking all cachelines as invalid, for example. It must wait until the cache (or caches) are completely invalid. If necessary, this is by a holding pattern in the program code sure. This can also be achieved by other means, it is crucial that after this step, the caches are in the same state.
• step G620 the write buffers of the execution units are emptied so that no activities of the execution units take place after the switchover, which are still from the
• step G630 the state of the pipeline stages of the execution units is synchronized. For this purpose, for example, one executes an appropriate number of NOP (No Operation) instructions before the switching sequence / switching command.
• NOP No Operation
• NOP Number of pipeline stages and are thus dependent on the respective architecture. Which instruction is suitable as a NOP instruction is also architecture-dependent. If the execution units have an instruction cache, it must be ensured that this instruction sequence is aligned with the boundaries of a cacheline (alignment). Since the instruction cache has been marked as invalid prior to the execution of these NOPs, these NOPs must first be cached. If this command sequence starts at a cache line boundary, data transfer from memory (e.g., RAM / ROM / Flash) to the cache is complete before the switch command occurs. Again, this must be taken into account when determining the necessary number of NOPs.
• memory e.g., RAM / ROM / Flash
• step G640 the command step for switching to the comparison mode is actually performed.
• step G650 the contents of the respective register files of each execution unit are equalized.
• the registers are to be loaded with identical contents before or after the changeover. It is important that after switching the contents of a register in the execution units is identical before the register contents are transferred to external and thus compared by the comparison unit.
• step G660 the interrupt controllers are reprogrammed so that an external
• Interrupt signal at all interconnected execution units triggers the same interrupt.
• step G670 the interrupts are released again. If it is not clear from the program flow when to switch to the comparison mode, the participating execution units must be informed about the intended switchover. For this purpose, an interrupt is preferably initiated, for example by SW, in the interrupt controllers belonging to the respective execution units.
• Interrupt handling then causes execution of the interconnect sequence described above.
• FIG. 10 shows a state machine which represents the switching between a performance and a comparison mode (and vice versa).
• the system is started, caused by "Power On” or reset (software or hardware), the system is set to state G700 via transition G800.
• the system is capable of an Undefined event that is capable , to initiate a reset, always starts to work in state G700.
• Examples events which can trigger a reset are external signals, problems in the power supply or internal fault events, the one
• the state G700 of the switching and comparison unit G70 and also of the multiprocessor system G60, in which work is carried out in the performance mode, is thus the default state of the system. In all cases in which, as described above, an otherwise undefined state would be assumed, the default state G700 is taken. This default position of the state G700 is through
• the system state or the state of the switching and comparison unit G60 can be encoded in a register, in a bit of a register, by a bit combination in a register or by a flip-flop. It is then ensured by hardware that the state G700 is always assumed after a reset or power on. This is ensured by, e.g. the reset signal or the "Power On" signal is routed to the reset input or the set input of the flip-flop or the register.
• state G700 the system operates in a performance mode.
• the execution units GlOa, GlOb work with different commands, programs or program pieces.
• a switchover request can be recognized, for example, by an execution unit GlOa, GlOb executing a special switchover command. Other possibilities include detection by accessing a specific memory address, by an internal signal or by an external signal. As long as there is no switchover request, the multiprocessor system G60 and therefore also the switching and comparison unit G70 remain in state G700. In addition, the changeover request designates the recognition of a switchover condition, which is identified as a changeover request is identified in this special system. The remaining in the state G700 is represented by the transition G810. Is from the
• Execution unit GlOa detected a switching request, then the switching and comparison unit G70 is transferred via the transition G820 in the state G710.
• the state G710 thus designates the situation that the execution unit GlOa has detected a switchover request and waits until the execution unit GlOb also recognizes a switchover request. As long as this is not the case, the switching and comparison unit G70 remains in
• the transition G840 takes place when in the state G710 the execution unit GlOb also recognizes a switchover request.
• the switching and comparison unit G70 thus assumes the state G730. This state indicates the situation when both execution units GlOa, GlOb have detected a switchover request. In state G730 find the
• Synchronization process instead, with which the two execution units GlOa, GlOb are synchronized with each other to then work in the comparison mode.
• the switching and comparison unit G70 remains in state G730, which is represented by the transition G890. If a switchover request is first recognized by the execution unit GlOb in the state G700, the transition is made to the state G720 via the transition G860.
• the state G720 thus designates the situation that the execution unit GlOb has recognized a switchover request and waits until the execution unit GlOa also recognizes a switchover request. As long as this is not the case, the switching and comparison unit G70 remains in state G720, which is represented by the transition G870.
• transition G880 takes place when in the state G720 the execution unit GlO a also recognizes a switchover request.
• the switching and comparison unit thus assumes the state G730. If both execution units GlOa, GlOb simultaneously recognize a switchover request in state G700, state G730 is immediately entered. This case represents transition G850.
• both execution units GlOa, GlOb have recognized a switching request.
• the internal states of the execution units GlOa, GlOb are synchronized to operate in comparison mode after completion of these synchronization operations.
• the transition G900 takes place during this synchronization work. This transition indicates the end of synchronization.
• the execution units GlOa, GlOb operate in comparison mode.
• the completion of the synchronization work can be signaled by the execution units GlOa, GlOb itself. This means that transition G900 takes place when both execution units GlOa, GlOb have signaled that they are ready to work in compare mode.
• the termination can also be signaled for a set time. This means that in the switching and comparison unit G70 is permanently coded how long in the state G730 remains. This time is set so that both execution units GlOa, GlOb have finished their synchronization work safely. After this time the transition G900 is initiated. In another
• the switching and comparison unit G70 monitor the states of the execution units GlOa, GlOb and even recognize when both execution units GlOa, GlOb have completed their synchronization work. After detection, transition G900 is then initiated.
• the multiprocessor system G60 remains in compare mode, represented by transition G910. If a changeover request is detected in state G740, the changeover and comparison unit is set to state G700 via transition G920. As already described, the system operates in state G700 in the performance mode. The separation of the program flows at the transition from the state
• G740 in the state G700 can then be carried out as described in the method.
• FIG. 11 shows a multiprocessor system G400 with two execution units G410a, G410b and two interrupt controllers G420a, G420b including interrupt masking registers G430a, G430b contained therein and various interrupt sources G440a to G440n. Also shown is a switch and compare unit G450 having a special interrupt mask register G460.
• each execution unit G410a, G410b has its own interrupt controller G420a, G420b in order to simultaneously handle two interrupts in the performance mode.
• the interrupt sources G440a to G440n are advantageously connected in the same way to both interrupt controllers G420a, G420b in each case. This type of connection causes, without further action on both execution units G410a, G410b the same interrupt is triggered.
• the interrupt controllers G420a, G420b are programmed so that the corresponding interrupt sources G440a to G440n are appropriately divided among the various execution units G410a, G410b according to the application. This is done by means of a suitable programming of the interrupt masking registers G430a, G430b.
• the mask registers look for each
• Interrupt source G440a to G440n one bit in the register. If this bit is set, the interrupt is disabled, so it is not forwarded to the connected execution unit G410a, G410b.
• a given interrupt source G440a to G440n is processed by exactly one execution unit G410a or G410b.
• this is true for at least some of the interrupt sources. It can thus be achieved that several interrupt sources G440a to G440n can be processed simultaneously without an interrupt nesting (an interrupt processing is interrupted by a second interrupt) or interrupt pending (the processing of the second is postponed until the processing of the first is ended is) takes place.
• G430b are identical. This synchronization is described in FIG. 9 in step G660. This synchronization can be done by software by programming both interrupt masking registers G430a, G430b with the same value accordingly. It is proposed to use a special register G460 to speed up the switching process. In one embodiment, this register G460 is in the
• Switching and comparison unit G460 arranged, but it can also be included in the Umschaltyerkennung G40, in a combined Umschalt mechanismerkennung, in the comparator, in the switching unit G80, as well as in all combinations. It is also conceivable that this register is arranged outside of these three components at another suitable location. Register G460 contains the interrupt masking that is in the
• the switching and comparison unit G450 receives from the switching request recognition G40 a signal for switching from a performance to a comparison mode. After the interrupts can be disabled in step G600, the interrupt masking registers G430a, G430b of the interrupt controllers G420a, G420b be reprogrammed. This is now performed by hardware from the switching and comparison unit G450 in parallel with the other synchronization steps after the switching signal has been received and the interrupt controllers G420a, G420b have been disabled. Conveniently, the interrupt masking registers G430a, G430b in the compare mode are not individually reprogrammed, but always the central register G460. This is then transmitted synchronously by hardware to the two interrupt masking registers G430a, G430b.
• G430a, G430b can be transmitted.
• FIG. 12 shows a multiprocessor system GlOOO with two execution units GlOlOa, GlOlOb, a switchover and comparison unit G 1020, and an interrupt controller G1030 with three different register sets G1040a, G1040b, G1050.
• a special interrupt controller G1030 is proposed, as shown in FIG. This is used in a multiprocessor system GlOOO, which in the example with two execution units GlOlOa, GlOlOb, and a switching and comparison unit G 1020, which can switch between a comparison and a performance mode, is shown.
• the register sets G 1040a, G 1040b are used.
• the interrupt controller G1030 operates as well as two interrupt controllers G420a, G420b. This behavior is shown and described in FIG.
• the register set G 1040a is assigned to the execution unit GlOlOa and the register set G 1040b to the execution unit G 101 Ob.
• the interrupt sources G 1060a to G 106On are appropriately distributed by masking to the execution units GlOlOa, GlOlOb.
• the switch and compare unit G1020 When switching from a performance mode to a compare mode, the switch and compare unit G1020 generates a signal G1070. This signals to the interrupt controller G1030 that the system is switched to comparison mode or that the system is operating in comparison mode from this point in time.
• the interrupt controller G1030 then uses the register set
• G1050 is permitted and a write to the register sets G1040a, G1040b is prevented.
• FIG. 13 shows the simplest form of a comparator M500, G20.
• An essential component in a multiprocessor system G60 having at least two execution units GlOa, GlOb with a switchover between a performance mode and a
• Comparison mode is the comparator M500.
• the comparison component M500 can receive two input signals M510 and M511. It then compares these to equality, in the context presented here, preferably in the sense of a bit-wise equality.
• the value of the input signals M510, M511 is given to the output signal M520 and the error signal M530 does not become active, i. it signals the "good" state. If it detects inequality, the error signal M530 is activated.
• the signal M520 can then optionally be deactivated.
• fault containment ie other components that lie outside of the execution units are not corrupted by the potentially faulty signal, but there are also systems in which the signal This is the case, for example, if only fail-silence is required at the system level, for example, the error signal can then be routed externally.
• the component M500 can be executed as a so-called TSC component (totally seif checking).
• the error signal M530 is routed to at least two lines ("dual rail") to the outside, and it is ensured by internal design and fault detection measures that in any possible error case of the comparison component this signal is correct or discernible incorrect
• Signal provides a binary signal over two lines available, preferably so that the two lines are inverted to each other in error-free case.
• a preferred variant in the use of the system according to the invention is to use such a TSC comparator.
• a second class of embodiments may be distinguished as to what degree of synchronicity the two inputs M510, M511 (or M610, M611) must have.
• One possible embodiment is characterized by intermittent synchronicity, ie the comparison of the data can be carried out in one cycle.
• phase offset is useful to avoid common cause errors, i. such error causes that can affect several processing units simultaneously and similarly.
• FIG. 14 therefore describes another embodiment.
• the components and signals M600, M610, M611, M620, M630 have the same meaning as the corresponding components and signals M500, M510, M511, M520, M530 of Figure 13.
• component M640 is inserted beyond these components , which delays the earlier input by the phase offset.
• this delay element is accommodated in the comparator to use it only in the comparison mode.
• intermediate buffers M650, M651 can be placed in the input chain in order to be able to tolerate asynchronisms which are not pure clock or phase offsets.
• These intermediate buffers are preferably designed as FIFO memories (first-in, first out).
• Such a memory has an input and an output and can store several memory words. An incoming memory word is shifted in its place upon arrival of a new memory word. After the last digit (the depth of the buffer) it will be moved "out of memory.” If such a buffer exists, you can as well
• Tolerate asynchronisms up to the maximum depth of the buffer. In this case, an error signal must be output even if the buffer overflows.
• comparator embodiments it can be distinguished according to how the signal M520 (or M620) is generated.
• a preferred embodiment is the input signals
• M510, M511 or M610, M611
• the output and make the connection interruptible by switch.
• the particular advantage of this embodiment is that for switching between performance mode and possible different comparison modes the same switches can be used.
• the signals can also be generated from internal comparator buffers.
• a final class of embodiments may be distinguished as to how many inputs are present on the comparator and how the comparator should react. With three inputs, a majority voting, a comparison of all three or a comparison of only two signals can be made. With four or more inputs, correspondingly more embodiments are conceivable. A detailed description of the possible embodiments is included in the description of FIG.
• a comparator or a more general voting / processing / sorting element (hereinafter always referred to as a comparator for the sake of simplicity).
• a comparator it is necessary or advantageous to deactivate or make passive a comparator or a more general voting / processing / sorting element (hereinafter always referred to as a comparator for the sake of simplicity).
• a comparator it is necessary or advantageous to deactivate or make passive a comparator or a more general voting / processing / sorting element (hereinafter always referred to as a comparator for the sake of simplicity).
• a preferred Variant of the implementation is therefore to combine these two parts in one component.
• This is a component with at least the input signals (output execution unit 1, output execution unit 2), at least the output signals (Output 1, Output 2), a logic output signal "Output total” (can physically match Output 1 or Output 2) and a comparator
• the component has the
• an error signal to signal a detected fault a mode signal to signal the mode in which that component is located, and control signals to and from the component.
• the two or more execution units in the performance mode are connected as a master to a processor-internal bus.
• the comparison unit is deactivated or the error signal which is generated in the case of a different behavior of the execution units in one of the possible comparison modes is masked. This means that the switching and comparison unit is transparent to the software.
• the physical execution units to be compared are treated as a logical execution unit on the bus, i. there is only one master on the bus.
• the error signal of the comparator is activated.
• the switching and comparison unit separates all but one execution unit via switches from the processor-internal bus, duplicates the inputs of the one logical execution unit and makes them available to all execution units involved in the comparison mode. When writing to the bus, the outputs in the compare unit are compared, and if equal, this data is written over the one available access to the bus.
• FIG. 15 and FIG. 16 describe the basic behavior of the preferred component M700 (switching and comparison unit, corresponds to G70). For the sake of simplicity, this figure is drawn only for two execution units.
• FIG. 15 shows the status of the component in the comparison mode, FIG. 16 in the performance mode.
• the various switch positions in these modes are implemented by M700 through the M760 control.
• the two execution units M730, M731 can first write in the performance mode on the data and address bus M710 when the switches M750 and M751 are closed, as shown in FIG. It is assumed that possible write conflicts will be resolved either via the bus protocol or through other, not drawn components. in the Comparative mode, the behavior is another, at least from a logical point of view. As shown in FIG. 15, the switches M750, M751 are then opened and thus the direct access possibilities are interrupted. In contrast to FIG. 16, however, the switches M752, M753 are then closed in FIG. The signals M740, M741 of the execution units M730, M731 are passed to the comparison component M720. This is at least as constructed as drawn in Figure 13, but it can also extensions, as shown in Figure 14, include.
• FIG. 17 shows a variant of the switching and comparison unit. Even for a simple system with only two execution units GlOa, GlOb, there are many variants of the implementation of a switching and comparison unit. Another, which is particularly advantageous when no buffers are to be used in the comparator, is shown in FIG. As in FIG. 15, FIG. 16, there are the signals M840, M841 of the execution units. The latter are in this
• mode logic M810 which specifies the mode of the component.
• the performance mode closes the switch M831, in comparison mode it opens it.
• the mode signal to the comparator M820.
• the switch In the performance mode the switch is always closed, in comparison mode always when there is no error. Of course, even if an error has been detected, the switch will remain open until a corresponding reset occurs.
• FIG. 18 shows a further embodiment of the switching and comparison unit.
• Mode logic M910 which specifies the mode of the component. In performance mode, it closes switch M931 and opens switches M932, M933. Thus, the comparison component M920 is not loaded with data in this mode. This allows longer buffer times for asynchronisms, or lower buffer depths in one implementation. In performance mode, the M930 switch is always closed. In comparison mode, component M910 closes the
• the M910 mode logic can still communicate the mode to the M920 comparator.
• the switch M930 is closed in error-free case.
• the comparison component M920 interrupts the forwarding of the signal M940 to the bus by opening the switch M930.
• a preferred implementation of this component is thus characterized by the fact that there are several processing units that can write output signals to the bus (e.g., address / data bus). What is essential is that the component can process (e.g., compare, but possibly also vote or sort) at least two of the output signals of the execution units and that the component can affect at least one switch that breaks at least one of the direct bus accesses. This is especially useful if the execution units are machine cores. Furthermore, it is advantageous if the state of the influenceable switch characterizes the operating mode of the arithmetic unit.
• the system properties are then implemented particularly well if the component can apply a signal to the address data bus.
• this is a through connection of one of the output signals of one of the execution units.
• this may arise from the processing of various output signals of the various execution units.
• this mode information may vary depending on the implementation even explicitly exist in a subcomponent.
• this signal may also be routed out of the component and made available to other parts of the system.
• N100, N10, N120, N130, N140, N141, N142, N143, N14n, N160, N161, N162, N163, N16n have the same meaning as in Fig. 20.
• the mode signal is N150 and the error signal is N170 drawn in this figure.
• the optional error signal is generated by fault circuit logic N130, which collects the error signals, and is either a direct forwarding of the single error signals or a bundling of the error information contained therein.
• the mode signal Nl 50 is optional, but its use outside of this component can be beneficial in many places.
• the combination of the information of the switching logic NI10 (i.e., the function described in the description of Figure 20) and the processing logic (i.e., the determination of the comparison operation per output, i.e., per function value) is the mode information and sets the mode.
• This information is of course multivalued in the general case, i. not just a logical bit. Not all the theoretically conceivable modes are useful in a given implementation, it is preferable to restrict the number of modes allowed.
• the mode signal then brings the relevant mode information to the outside.
• An HW implementation is preferably shown so that the externally visible mode signal can be configured.
• the processing logic and circuitry are also configured to be configurable. Preferably, these configurations are coordinated. Alternatively, one can give only or additionally changes of the mode signal to the outside. This has advantages, especially in a two-party configuration.
• this mode signal is protected.
• An implementation in the two-system is illustrated in Figure 19, for example, based on the implementation illustrated in Figure 17.
• the signal M850 is led out of the switching and comparison unit.
• this information can be represented logically over one bit.
• a hedge can then preferably be displayed via a dual-rail signal.
• the signal can also be protected by a doubling, which is optionally inverted.
• one can also generate a parity which is preferably internally generated intrinsically safe, or use a CRC (cyclic redundancy check) or ECC (error correcting code).
• the mode signal can be used outside the component. Initially, it can be used to self-monitor the operating system.
• this signal can optionally also be used in other data sinks of a ⁇ C (or more general arithmetic unit).
• a memory protection unit MPU
• MPU memory protection unit
• An MPU is a unit that can ensure that only permitted accesses are made to the data / address bus, for example by blocking access to certain address spaces for certain program sections.
• An essential further purpose is the evaluation of the mode signal outside of the arithmetic unit.
• a direct application is the evaluation in a decrementing watchdog.
• Such a “watchdog” consists of at least one (counter) register, which can be set by the microprocessor to an integer value After setting this register, the "watchdog” automatically decrements the value of the register with a fixed period , If the value of the register is zero or if an overflow occurs, the watch dog generates an error signal, if the error signal is not to be generated, the microprocessor must reset the value of the register in good time. If the microprocessor executes the software correctly, it is assumed that in this case also the "Watch-Dog" is no longer correctly operated and thus an error signal from the "Watch-Dog” is generated.
• the integrity of the hardware and data structures can be reliably verified in a compare mode, but it must be ensured that the microprocessor regularly returns to this.
• the task of the "watchdog" described here is therefore not only to generate an error signal if it is no longer reset within a defined period, but also if the microprocessor within a defined
• Period does not return to the defined comparison mode.
• the "watchdog” can only be reset if the signal mode indicates the defined comparison mode of the arithmetic unit, thus ensuring that the arithmetic unit periodically switches back to this mode.
• the value in the register of the "watchdog" decrements only when certain interrupts at
• Microprocessor be triggered.
• the external interrupt signals of the ⁇ C must also be coupled to the watchdog.
• the watchdog stores which interrupts switch the ⁇ C to the defined comparison mode.
• the watchdog is "pulled up” as soon as such an interrupt comes, it is reset by the presence of the correct mode signal.
• N300 is a computational unit that can send such a mode signal. This may be, for example, a ⁇ C with multiple execution units and another component that can generate this mode signal. For example, this other component may be realized as in FIG. 19 or FIG. N300 gives this signal N310 to the
• N330 e.g., other computational unit, other ⁇ C or ASIC. This can ask about the N320 signal to N300 questions which N300 has to answer via N321. Such a question may be a computational task whose correct result is to be delivered via N321 from N300 within a defined time interval. N330 can check the correctness of this result independently of N300. For example, the results are stored in N330 or
• N330 can calculate it yourself. If an incorrect value is detected, an error is detected.
• the special feature of the proposed question-answer communication is that a parallel to the response, the mode signal is observed.
• the questions are to be asked so that to answer by N300, they must adopt certain modes. This can be reliably verified that all mode changes are functional, and that provided in the program flow mode changes are also performed. Especially when initializing a system, but also during operation, this can serve as an essential component of a security concept.
• An arithmetic unit N400 which has the invention, sends an actuating command via the connection N420 to an (intelligent) actuator or an actuator control N430. In parallel, it sends the mode signal to this actuator via the N410 connection.
• Actuator N430 uses the mode signal to check if the
• Control is enabled and optionally returns an error status via signal N440. If the drive is faulty, it assumes the non-critical fail-silence state in the system.

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