WO2006045781A3 - Verfahren und vorrichtung zur umschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten - Google Patents
Verfahren und vorrichtung zur umschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten Download PDFInfo
- Publication number
- WO2006045781A3 WO2006045781A3 PCT/EP2005/055508 EP2005055508W WO2006045781A3 WO 2006045781 A3 WO2006045781 A3 WO 2006045781A3 EP 2005055508 W EP2005055508 W EP 2005055508W WO 2006045781 A3 WO2006045781 A3 WO 2006045781A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- modusums
- chaltung
- ausführungseinheiten
- bei einem
- verfahren zur
- Prior art date
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1695—Error detection or correction of the data by redundancy in hardware which are operating with time diversity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
- G06F11/184—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/845—Systems in which the redundancy can be transformed in increased performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/86—Event-based monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Quality & Reliability (AREA)
- Multimedia (AREA)
- Computer Hardware Design (AREA)
- Hardware Redundancy (AREA)
- Executing Machine-Instructions (AREA)
- Multi Processors (AREA)
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2005800365762A CN101048757A (zh) | 2004-10-25 | 2005-10-25 | 在拥有至少两个执行单元的计算机系统中切换的方法和装置 |
EP05801429A EP1805618A2 (de) | 2004-10-25 | 2005-10-25 | Vorrichtung und verfahren zur modusumschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten |
JP2007537293A JP2008518301A (ja) | 2004-10-25 | 2005-10-25 | 少なくとも2つの実行ユニットを有する計算機システムで切替を行うための方法および装置 |
US11/666,404 US20080288758A1 (en) | 2004-10-25 | 2005-10-25 | Method and Device for Switching Over in a Computer System Having at Least Two Execution Units |
Applications Claiming Priority (12)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004051952.8 | 2004-10-25 | ||
DE200410051992 DE102004051992A1 (de) | 2004-10-25 | 2004-10-25 | Verfahren und Vorrichtung zur Verzögerung von Zugriffen auf Daten und/oder Befehle eines Mehrprozessorsystems |
DE102004051992.7 | 2004-10-25 | ||
DE102004051937.4 | 2004-10-25 | ||
DE102004051950.1 | 2004-10-25 | ||
DE200410051937 DE102004051937A1 (de) | 2004-10-25 | 2004-10-25 | Verfahren und Vorrichtung zur Synchronisierung in einem Mehrprozessorsystem |
DE102004051964.1 | 2004-10-25 | ||
DE200410051950 DE102004051950A1 (de) | 2004-10-25 | 2004-10-25 | Verfahren und Vorrichtung zur Taktumschaltung bei einem Mehrprozessorsystem |
DE200410051952 DE102004051952A1 (de) | 2004-10-25 | 2004-10-25 | Verfahren zur Datenverteilung und Datenverteilungseinheit in einem Mehrprozessorsystem |
DE200410051964 DE102004051964A1 (de) | 2004-10-25 | 2004-10-25 | Verfahren und Vorrichtung zur Überwachung einer Speichereinheit in einem Mehrprozessorsystem |
DE102005037225.2 | 2005-08-08 | ||
DE200510037225 DE102005037225A1 (de) | 2005-08-08 | 2005-08-08 | Verfahren und Vorrichtung zur Umschaltung bei einem Rechnersystem mit wenigstens zwei Ausführungseinheiten |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006045781A2 WO2006045781A2 (de) | 2006-05-04 |
WO2006045781A3 true WO2006045781A3 (de) | 2006-07-06 |
Family
ID=36072087
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2005/055508 WO2006045781A2 (de) | 2004-10-25 | 2005-10-25 | Verfahren und vorrichtung zur umschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten |
Country Status (6)
Country | Link |
---|---|
US (1) | US20080288758A1 (de) |
EP (1) | EP1805618A2 (de) |
JP (1) | JP2008518301A (de) |
KR (1) | KR20070085278A (de) |
CN (1) | CN101048757A (de) |
WO (1) | WO2006045781A2 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006048169A1 (de) * | 2006-10-10 | 2008-04-17 | Robert Bosch Gmbh | Verfahren zur Überwachung einer Funktionsfähigkeit einer Steuerung |
DE102006050715A1 (de) * | 2006-10-10 | 2008-04-17 | Robert Bosch Gmbh | Verfahren und System zum Erzeugen eines gültigen Signals |
DE102008001806A1 (de) * | 2008-05-15 | 2009-11-19 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Fehlerüberwachung eines Rechnersystems |
US8275977B2 (en) * | 2009-04-08 | 2012-09-25 | Freescale Semiconductor, Inc. | Debug signaling in a multiple processor data processing system |
JP5796311B2 (ja) | 2011-03-15 | 2015-10-21 | オムロン株式会社 | 制御装置およびシステムプログラム |
WO2019049980A1 (ja) * | 2017-09-11 | 2019-03-14 | 日本電気株式会社 | 再構成回路 |
CN111413897B (zh) * | 2020-03-18 | 2021-05-14 | 四川中微芯成科技有限公司 | 一种安全的任意切换芯片工作模式的方法和芯片 |
CN111694339B (zh) * | 2020-05-29 | 2021-07-06 | 东风汽车集团有限公司 | 一种组合开关模拟器、车身控制器测试系统及方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4823256A (en) * | 1984-06-22 | 1989-04-18 | American Telephone And Telegraph Company, At&T Bell Laboratories | Reconfigurable dual processor system |
US20020073357A1 (en) * | 2000-12-11 | 2002-06-13 | International Business Machines Corporation | Multiprocessor with pair-wise high reliability mode, and method therefore |
US6615366B1 (en) * | 1999-12-21 | 2003-09-02 | Intel Corporation | Microprocessor with dual execution core operable in high reliability mode |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5408649A (en) * | 1993-04-30 | 1995-04-18 | Quotron Systems, Inc. | Distributed data access system including a plurality of database access processors with one-for-N redundancy |
DE19815263C2 (de) * | 1998-04-04 | 2002-03-28 | Astrium Gmbh | Vorrichtung zur fehlertoleranten Ausführung von Programmen |
US6640313B1 (en) * | 1999-12-21 | 2003-10-28 | Intel Corporation | Microprocessor with high-reliability operating mode |
US6625749B1 (en) * | 1999-12-21 | 2003-09-23 | Intel Corporation | Firmware mechanism for correcting soft errors |
DE102005037222A1 (de) * | 2004-10-25 | 2007-02-15 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Auswertung eines Signals eines Rechnersystems mit wenigstens zwei Ausführungseinheiten |
WO2006045773A2 (de) * | 2004-10-25 | 2006-05-04 | Robert Bosch Gmbh | Vorrichtung und verfahren zur modusumschaltung bei einem rechnersystem mit wenigstens zwei ausführungseinheiten |
US20080270746A1 (en) * | 2004-10-25 | 2008-10-30 | Bernd Mueller | Method and Device for Performing Switchover Operations and for Comparing Signals in a Computer System Having at Least Two Processing Units |
JP2008518297A (ja) * | 2004-10-25 | 2008-05-29 | ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング | 少なくとも2つの実行ユニットを有する計算機システムで切替を行うための装置および方法 |
US20080313384A1 (en) * | 2004-10-25 | 2008-12-18 | Ralf Angerbauer | Method and Device for Separating the Processing of Program Code in a Computer System Having at Least Two Execution Units |
KR101017444B1 (ko) * | 2004-10-25 | 2011-02-25 | 로베르트 보쉬 게엠베하 | 적어도 2개의 처리 유닛들을 갖는 컴퓨터 시스템에서 모드전환 및 신호 비교를 위한 방법 및 장치 |
-
2005
- 2005-10-25 WO PCT/EP2005/055508 patent/WO2006045781A2/de active Application Filing
- 2005-10-25 CN CNA2005800365762A patent/CN101048757A/zh active Pending
- 2005-10-25 JP JP2007537293A patent/JP2008518301A/ja active Pending
- 2005-10-25 KR KR1020077009126A patent/KR20070085278A/ko not_active Application Discontinuation
- 2005-10-25 US US11/666,404 patent/US20080288758A1/en not_active Abandoned
- 2005-10-25 EP EP05801429A patent/EP1805618A2/de not_active Ceased
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4823256A (en) * | 1984-06-22 | 1989-04-18 | American Telephone And Telegraph Company, At&T Bell Laboratories | Reconfigurable dual processor system |
US6615366B1 (en) * | 1999-12-21 | 2003-09-02 | Intel Corporation | Microprocessor with dual execution core operable in high reliability mode |
US20020073357A1 (en) * | 2000-12-11 | 2002-06-13 | International Business Machines Corporation | Multiprocessor with pair-wise high reliability mode, and method therefore |
Also Published As
Publication number | Publication date |
---|---|
US20080288758A1 (en) | 2008-11-20 |
KR20070085278A (ko) | 2007-08-27 |
WO2006045781A2 (de) | 2006-05-04 |
JP2008518301A (ja) | 2008-05-29 |
EP1805618A2 (de) | 2007-07-11 |
CN101048757A (zh) | 2007-10-03 |
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