EP1798712B1 - Procédé et appareil pour le contrôle du niveau de puissance d'un dispositif d'affichage - Google Patents

Procédé et appareil pour le contrôle du niveau de puissance d'un dispositif d'affichage Download PDF

Info

Publication number
EP1798712B1
EP1798712B1 EP20060123240 EP06123240A EP1798712B1 EP 1798712 B1 EP1798712 B1 EP 1798712B1 EP 20060123240 EP20060123240 EP 20060123240 EP 06123240 A EP06123240 A EP 06123240A EP 1798712 B1 EP1798712 B1 EP 1798712B1
Authority
EP
European Patent Office
Prior art keywords
value
power level
power
picture
video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
EP20060123240
Other languages
German (de)
English (en)
Other versions
EP1798712A1 (fr
Inventor
Carlos Correa
Cédric Thebault
Rainer Zwing
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Licensing SAS
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP05292386A external-priority patent/EP1785974A1/fr
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Priority to EP20060123240 priority Critical patent/EP1798712B1/fr
Publication of EP1798712A1 publication Critical patent/EP1798712A1/fr
Application granted granted Critical
Publication of EP1798712B1 publication Critical patent/EP1798712B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • G09G3/2944Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge by varying the frequency of sustain pulses or the number of sustain pulses proportionally in each subfield of the whole frame
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/06Adjustment of display parameters
    • G09G2320/0626Adjustment of display parameters for control of overall brightness
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/16Calculation or use of calculated indices related to luminance levels in display data

Definitions

  • the invention relates to a method for power level control of a display device and an apparatus for carrying out the method.
  • the invention is closely related to a kind of video processing for improving the picture quality of picture which are displayed on display devices like plasma display panels (PDP) and all kind of display devices based on the principle of duty cycle modulation (pulse width modulation) of light emission.
  • the invention is also used for reducing the average power dissipation in the plasma display panels.
  • the Plasma technology makes possible to achieve flat colour panel of large size (out of the CRT limitations) and with very limited depth without any viewing angle constraints.
  • CRT Cathode Ray Tube
  • PDP is a technology that generates its own light.
  • both technologies use a power management (or brightness regulation) circuit which allows a higher peak white brightness value than a full white value.
  • the CRT screens use a so called ABL (for Average Beam-current Limiter) circuit, which is implemented by analog means usually in the video controller, and which decreases video gain as a function of average luminance usually measured over an RC stage.
  • ABL Average Beam-current Limiter
  • the plasma display panels use a so called APL (for Average Power Level) control circuit that generates less or more sustain pulses as a function of the average power level of the displayed picture.
  • APL Average Power Level
  • the APL control starts from the reflection that for larger peak white luminance values in plasma displays more sustain pulses are necessarily required.
  • more sustain pulses correspond also to a higher power consumption of the PDP.
  • Such an APL control circuit is described in the international patent application WO 00/46782 . For pictures having relatively low picture power, i.e.
  • a mode will be selected which uses a high number of sustain pulses to create the different video levels because the overall power consumption will be limited due to a great amount of pixels with low luminance value.
  • a mode will be selected which uses a low number of sustain pulses to create the different video levels because the overall power consumption will be high due to a great amount of pixels with high luminance value.
  • the APL control is implemented as follows: first the average video level of the input signal after de-gamma is computed. This value is a good estimation of the total luminance power required for reproducing the input picture. Secondly, by means of a look-up table, the total number of sustain pulses that can be generated for the input picture to keep the power consumption in an authorized range is determined and a corresponding subfield organisation is simultaneously selected. As described in the international patent application WO 00/46782 , the sub-field organisations can vary in respect to one or more of the following characteristics:
  • this APL control circuit allows a higher peak-white value without overloading the set power supply.
  • this solution is not optimal in some operation conditions. For example, if the PDP is connected to a video source where the video range is inferior to the nominal range (for instance if the input video range is 0 to 160 and the nominal range is 255 for an 8-bit range), there are some video levels that are never used and some supply power is so wasted in generating sustain pulses that produce no light. Indeed, as the sustain pulses are generated simultaneously for the whole panel, even if a subfield is never used, it consumes energy.
  • An average power circuit for determining a power value which is characteristic of the power level of the picture to be displayed is already known from US-B1-6 380 943 .
  • the basic idea behind the new power level control method is to generate only the required amount of sustain pulses that effectively produce light and to avoid generating unnecessary sustain pulses.
  • the video range of the input video is increased in order to be equal to the nominal range and a power level mode with a reduced number of sustain pulses is selected to keep constant the brightness of the image.
  • a video gain is applied to the video levels of the picture.
  • the inventive method is a method for power level control in a display device having a plurality of luminous elements corresponding to the pixels of a picture, wherein the time duration of a video frame is divided into a plurality of subfields during which each luminous element can be activated for light emission in small pulses, called hereinafter sustain pulses, corresponding to a subfield code word representative of the video level of the corresponding pixel, wherein a set of power level modes is provided for subfield coding wherein to each power level mode a characteristic subfield organization belongs, the subfield organizations being variable in respect to the number of sustain pulses during a frame.
  • the inventive method comprises
  • Fig.1 shows a block diagram of a power level control device of a Plasma display Panel of the prior art.
  • the principle implemented by this device is to compute the average power of a given picture and to select an appropriate power level mode (corresponding to a subfield organization) for sub-field coding.
  • the input video signals RED[7:0], GREEN[7:0], BLUE[7:0] are provided to an Average Power Level computation circuit 10 after a de-gamma processing 20.
  • the APL computation circuit 10 outputs a 10-bit APL signal, called APL[9:0], that is representative of the total luminance power required for displaying the input picture.
  • the average power value APL[9:0] of a picture can be calculated by simply summing up the pixel values for all video input data and dividing the result through the number of pixel values multiplied by three.
  • the signal APL[9:0] is then used by an APL mode decoder 30 for converting it into a power level mode, called APL_MODE[9:0], representing a subfield organization.
  • APL mode decoder 30 is a simple Look Up Table. Different examples of power level modes are given here :
  • the number of sustain pulses of a power level mode given in this example is identical to the mode number.
  • the sustain pulses are distributed among the different subfields of the video frame. This distribution is not described because it does not have consequences on the power consumption.
  • the input video signals RED[7:0], GREEN[7:0], BLUE[7:0] are also provided to a PDP display engine 40 after being delayed by a frame delay circuit 50 and a de-gamma processing 60.
  • input video signals have to be de-gammed by because the PDP display engine 40 has a linear gamma transfer function (the displayed brightness is proportional to number of generated sustain pulses). They also have to be delayed from a frame duration in order that the power level mode APL_MODE[9:0] determined by the decoder 30 corresponds to the video data supplied to the PDP display engine 40.
  • the linear display engine 40 receives three 16-bit de-gammed input video signals RED[15:0], GREEN[15:0], BLUE[15:0] and the 10-bit APL mode value APL_MODE[9:0] that controls the number of sustain pulses to be generated.
  • the subfield organization selected by the signal APL_MOOE[9:0] is used by the display engine 40 for coding the video signals RED[15:0], GREEN[15:0], BLUE[15:0] and the signals outputted by the display engine 40 are then provided to the PDP drivers 70 for displaying the corresponding images.
  • this device does not take into account the fact that when the video range of the input video is reduced, some supply power is wasted for generating sustain pulses that do not produce light.
  • the video range of the input video is increased in order to be equal to the nominal range (255 for a 8-bit coding) and a power level mode with a reduced number of sustain pulses is selected to keep constant the brightness of the image.
  • a video gain is applied to the video levels of the picture.
  • Fig.1 shows a block diagram of a power level control device of a Plasma display Panel according to the invention.
  • Fig.2 shows a block diagram of a power level control device of a Plasma display Panel according to the invention.
  • the same reference signs are used in two figures for the identical circuit blocks.
  • the input video signals RED[7:0], GREEN[7:0], BLUE[7:0] are first provided de-gamma circuits 20 and then to a circuit 10' for computing the average power level APL[9:0] of the input video image and for determining the maximum video value MAX[7:0] of said image.
  • These two signals APL[9:0] and MAX[7:0] are then converted by a power control mode and gain control circuit 30' into a power level mode APL_MODE[9:0] representing a subfield organization and a gain value GAIN[9:0] to be applied to the video input.
  • the power level mode APL_MODE[9:0] is selected as a function of the two signals APL[9:0] and MAX[7:0] and the gain value GAIN[9:0] is selected as a function of the maximum value MAX[7:0].
  • An example of power level mode and gain value will be given in reference to Fig.4 .
  • the input video signals RED[7:0], GREEN[7:0], BLUE[7:0] that are used by the PDP display engine 40 for displaying the picture are first delayed by a frame delay circuit 50, de-gammed by de-gamma circuits 60 and amplified by the selected gain value GAIN[9:0] by means of multiplier circuits 80. So the linear display engine 40 receives three 16-bit amplified input video signals RED[15:0], GREEN[15:0], BLUE[15:0] and the power level mode value APL_MODE[9:0] that controls the number of sustain pulses to be generated.
  • the subfield organization selected by the signal APL_MODE[9:0] is used by the display engine 40 for coding the amplified video signals RED[15:0], GREEN[15:0], BLUE[15:0] and the signals outputted by the display engine 40 are provided to the PDP drivers 70 for displaying the corresponding images.
  • Fig.3 shows a possible block diagram of the power level mode and gain control circuit 30' of the device of Fig.2 . It comprises 2 series-connected subcircuits :
  • Fig.4 shows a possible block diagram of the smooth circuit 31. It receives the signals APL[9:0] and MAX [7:0] and outputs signals APL_SMOOTH[9:0] and MAX _SMOOTH[7:0].
  • the signal APL[9:0] is processed by a hysteresis circuit 310 whose behavior is shown at Fig.6 for generating the smoothed signal APL_SMOOTH[9:0].
  • the principle of the smoothing principle on value MAX[7:0] is the following: - If the value MAX[7:0] is increasing no smoothing is applied. If this were not the case, the maximum video value would be higher than the measured value, which means that the video input range would exceed the measured range, and most probably there would be part of the picture that would be clipped above. - If MAX[7:0] value is decreasing, smoothing is applied.
  • the top half part of the circuit 31 evaluates a value STEP[7:0] which is a function of a APL frame difference which is the difference between two consecutive values APL_SMOOTH[9:0] of to two consecutive frames. Said APL frame difference is calculated by a difference circuit 312 and a frame delay 313 is required.
  • STEP[7:0] is evaluated by multiplying the APL frame difference by a control value SMOOTH_CTRL[7:0] by the means of a multiplier circuit 314. If SMOOTH_CTRL[7:0] is small, STEP[7:0] will be small and the circuit 31 will perform maximum smoothing. If SMOOTH_CTRL[7:0] is high, STEP[7:0] will also be high, and the circuit 31 will perform little or no smoothing effect. STEP[7:0] represents the maximum allowed negative discontinuity on the smoothed value MAX_SMOOTH[7:0] over a frame.
  • Fig.5 shows a possible implementation of the mode selection circuit 32. It comprises a first LUT 320 which receives the value APL_SMOOTH[9:0] coming from the smooth circuit 31 and outputs a number of the sustain pulses corresponding to said value APL_SMOOTH[9:0]. This number of sustain pulses is then multiplied by the value MAX_SMOOTH [7:0] divided by 256 by means of a multiplier circuit 321.
  • the value MAX_SMOOTH [7:0] is then converted by a gain Look Up Table 322 into the gain value GAIN[9:0] to be applied to the video levels of the pictures. For a maximum video level of x, the gain is equal to 255/x.
  • the number of sustain pulses outputted by the multiplier 321 is converted back into an APL value APL_MOOE[9:0] that is representative of a power level mode by means of a LUT 323 that has a function inverse to the LUT 320
  • the mode selection 32 comprises means 324 for selecting the maximum value between the value MAX_SMOOTH [7:0] and a low limit value LOW_LIMIT [7:0] in order that the number of sustain pulses outputted by the multiplier 321 is equal to or greater than the lowest number of sustain pulses of the different power level modes i.e the mode corresponding to the full-white mode.
  • This value LOW_LIMIT [7:0] is depending on the number of sustain pulses outputted by the LUT 320.
  • this value is also outputted by the LUT 320.
  • the minimum amount of sustain pulses is 200.
  • a factor F is given. It is just a calculation factor and denotes the lowest multiplication factor that does not produce a final number of sustain pulses inferior to 200.
  • This value APL_MOOE[9:0] will be used by the PDP display engine 40 for coding the amplified video levels of the picture with a power level mode having a total number of sustain pulses of 267.
  • the gain range might go from 1 (no amplification) up to a maximum of about 4. Indeed, the gain should never be higher than the ratio between peak white value and full white value.
  • the invention presented here is an extension to the classical PDP power management circuit which - improves the picture quality because on average, the number of discrete video levels available for coding the video input is higher; and - considerably reduces the PDP average power dissipation by eliminating generating unnecessary sustain pulses that do not directly translate into produced output light. This is in particular true for pictures with a low average power.
  • the invention can be used for all kinds of displays which are controlled by using a PWM like control of the light emission for grey-level variation.

Claims (10)

  1. Procédé de commande de niveau de puissance dans un dispositif de visualisation comportant une pluralité d'éléments lumineux correspondant aux pixels d'une image, dans lequel la durée d'une image vidéo est divisée en une pluralité de sous-zones pendant lesquelles chaque élément lumineux peut être activé pour l'émission de lumière dans de petites impulsions, ci-après désignés par impulsions d'entretien, correspondant à un mot de code de subdivision représentatif du niveau vidéo du pixel correspondant, dans lequel un ensemble de modes de niveau de puissance est réservé au codage de subdivision dans lequel à chaque mode de niveau de puissance appartient une organisation de sous-zones caractéristique, ces organisations étant variables en fonction du nombre d'impulsions d'entretien pendant la durée d'une image,
    caractérisé en ce qu'il comporte les étapes suivantes :
    - une étape de détermination d'une valeur de puissance qui est caractéristique du niveau de puissance de l'image à visualiser et d'une valeur vidéo maximale qui est caractéristique du niveau vidéo maximal de ladite image, et
    - une étape d'augmentation de ladite valeur vidéo maximale sensiblement jusqu'à la valeur nominale (255) et une étape de sélection du mode de niveau de puissance en fonction de ladite valeur de puissance et de ladite valeur vidéo maximale, ledit mode de niveau de puissance comportant un nombre réduit d'impulsions d'entretien de façon à ce que l'émission de lumière de chaque pixel soit maintenue.
  2. Procédé selon la revendication 1, dans lequel la valeur vidéo maximale de l'image est augmentée jusqu'à la valeur nominale (255) en appliquant un gain aux niveaux vidéo de l'image à visualiser.
  3. Procédé selon la revendication 1 ou 2, dans lequel la valeur de la puissance d'une image est la valeur moyenne de la puissance de ladite image.
  4. Procédé selon n'importe laquelle des revendications 1 à 3, dans lequel ladite valeur de puissance est une valeur lissée des valeurs de puissance d'une pluralité d'images et/ou dans lequel ladite valeur vidéo maximale est une valeur lissée des valeurs vidéo maximales de la dite pluralité d'images.
  5. Appareil de commande de niveau de puissance dans un dispositif de visualisation comportant une pluralité d'éléments lumineux correspondants aux pixels d'une image, dans lequel la durée d'une image vidéo est divisée en une pluralité de sous-zones pendant lesquelles chaque élément lumineux peut être activé pour l'émission de lumière dans de petites impulsions, ci-après désignés par impulsions d'entretien, correspondant à un mot de code de subdivision représentatif du niveau vidéo du pixel correspondant, dans lequel un ensemble de modes de niveau de puissance est réservé au codage de subdivision dans lequel à chaque mode de niveau de puissance appartient une organisation de sous-zones caractéristique, ces organisations étant variables en fonction du nombre d'impulsions d'entretien pendant la durée d'une image, et comportant
    - un circuit de calcul de la moyenne de la puissance d'image (10') qui détermine une valeur de puissance caractéristique du niveau de puissance de l'image à visualiser,
    caractérisé en ce qu'il comporte
    - un circuit de calcul de valeur vidéo maximale (10') qui détermine une valeur vidéo maximale caractéristique du niveau vidéo maximal de l'image à visualiser,
    - un circuit de commande du niveau de puissance (30') qui augmente la dite valeur vidéo maximale jusqu'à une valeur nominale (255) et sélectionne un mode de niveau puissance en fonction de ladite valeur de puissance et de ladite valeur vidéo maximale, ledit mode de niveau de puissance ayant un nombre réduit d'impulsions d'entretien de façon à ce que l'émission de lumière de chaque pixel soit maintenue.
  6. Appareil selon la revendication 5, dans lequel le circuit de commande de niveau de puissance (30') compote un circuit (31) qui lisse les valeurs de puissance et les valeurs vidéo maximales d'une pluralité d'images et un circuit de sélection de mode (32) qui sélectionne le mode de niveau de puissance en fonction desdites valeurs lissées de puissance et vidéo maximale et une valeur de gain en fonction de ladite valeur vidéo maximale lissée.
  7. Appareil selon la revendication 5, dans lequel le circuit de commande de niveau de puissance (30') ne comprend qu'un circuit de sélection de mode (32) pour sélectionner un mode de niveau de puissance en fonction de la valeur de puissance et de la valeur vidéo maximale et une valeur de gain en fonction de ladite valeur vidéo maximale.
  8. Appareil selon la revendication 6 ou 7, caractérisé en ce que le circuit de sélection de mode comporte :
    - un premier circuit (320) de transformation de la valeur de puissance de l'image à visualiser en un premier nombre d'impulsions d'entretien,
    - un deuxième circuit (322) de transformation de la valeur vidéo maximale en une valeur de gain à appliquer aux niveaux vidéo de ladite image,
    - un troisième circuit (321) de multiplication dudit premier nombre d'impulsions d'entretien par le rapport entre ladite valeur vidéo maximale et la valeur nominale; ledit circuit générant un deuxième nombre d'impulsions d'entretien et
    - un quatrième circuit (323) de transformation dudit deuxième nombre d'impulsions d'entretien en un mode de niveau de puissance.
  9. Appareil selon la revendication 8, caractérisé en ce que les premier, deuxième et quatrième circuits (320, 322, 323) sont des tables à consulter.
  10. Appareil selon les revendications 5 à 9, qui est incorporé dans un dispositif de visualisation, en particulier un dispositif de visualisation à plasma.
EP20060123240 2005-11-10 2006-10-31 Procédé et appareil pour le contrôle du niveau de puissance d'un dispositif d'affichage Expired - Fee Related EP1798712B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP20060123240 EP1798712B1 (fr) 2005-11-10 2006-10-31 Procédé et appareil pour le contrôle du niveau de puissance d'un dispositif d'affichage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05292386A EP1785974A1 (fr) 2005-11-10 2005-11-10 Procédé et appareil pour le contrôle du niveau de puissance d'un dispositif d'affichage
EP20060123240 EP1798712B1 (fr) 2005-11-10 2006-10-31 Procédé et appareil pour le contrôle du niveau de puissance d'un dispositif d'affichage

Publications (2)

Publication Number Publication Date
EP1798712A1 EP1798712A1 (fr) 2007-06-20
EP1798712B1 true EP1798712B1 (fr) 2009-01-21

Family

ID=38039071

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20060123240 Expired - Fee Related EP1798712B1 (fr) 2005-11-10 2006-10-31 Procédé et appareil pour le contrôle du niveau de puissance d'un dispositif d'affichage

Country Status (1)

Country Link
EP (1) EP1798712B1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6380943B1 (en) * 1998-09-18 2002-04-30 Matsushita Electric Industrial Co., Ltd. Color display apparatus
EP1026655A1 (fr) * 1999-02-01 2000-08-09 Deutsche Thomson-Brandt Gmbh Procédé pour commande de niveau de puissance d'un dispositif d'affichage et dispositif pour sa mise en oeuvre
JP3695737B2 (ja) * 1999-07-01 2005-09-14 パイオニア株式会社 プラズマディスプレイパネルの駆動装置

Also Published As

Publication number Publication date
EP1798712A1 (fr) 2007-06-20

Similar Documents

Publication Publication Date Title
US9830846B2 (en) Image display device capable of supporting brightness enhancement and power control and method thereof
US8188966B2 (en) Image display device and method capable of adjusting brightness
US6674429B1 (en) Method for power level control of a display and apparatus for carrying out the method
TW503667B (en) White balance correction circuit and correction method for display apparatus that displays color image by controlling number of emissions or intensity thereof in accordance with plurality of primary color video signals
US8279214B2 (en) Method and apparatus for power level control of a display device
EP2037441A2 (fr) Dispositif et procédé d'affichage d'images à faible puissance
JP2005292804A (ja) 制御装置及び画像表示装置
EP2194524B1 (fr) Dispositif d'affichage et procédé correspondant de contrôle de la luminosité
US7515119B2 (en) Method and apparatus for calculating an average picture level and plasma display using the same
JP5744815B2 (ja) 制御方法及び制御装置
US7982730B2 (en) Method and apparatus for power control in a display device
JP2003255884A (ja) 表示装置及びその画像信号処理装置及び駆動制御装置
EP1798712B1 (fr) Procédé et appareil pour le contrôle du niveau de puissance d'un dispositif d'affichage
JP2003177697A (ja) 映像表示装置
KR100339594B1 (ko) 디스플레이 구동 장치 및 그 구동 방법
EP1798713B1 (fr) Procédé et dispositif pour le contrôle du niveau de puissance dans un dispositif d'affichage
JP2005128544A (ja) プラズマディスプレイパネルの残像減少方法および装置
JP2002244615A (ja) Pdp装置
EP1798714A1 (fr) Procédé et appareil pour le contrôle de la puissance dans un dispositif d'affichage
KR100684728B1 (ko) 플라즈마 표시 장치 및 그 구동 방법
JP2005195905A (ja) 画像表示装置の駆動装置

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR MK YU

17P Request for examination filed

Effective date: 20071214

AKX Designation fees paid

Designated state(s): DE FR GB

17Q First examination report despatched

Effective date: 20080201

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 602006004954

Country of ref document: DE

Date of ref document: 20090312

Kind code of ref document: P

REG Reference to a national code

Ref country code: GB

Ref legal event code: 746

Effective date: 20090224

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20091022

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 10

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20151022

Year of fee payment: 10

Ref country code: GB

Payment date: 20151026

Year of fee payment: 10

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20151026

Year of fee payment: 10

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602006004954

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20161031

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20170630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170503

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20161102

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20161031