EP1797588A2 - Method for producing mixed stacked structures, different insulating areas and/or localised vertical electrical conducting areas - Google Patents

Abstract

The invention relates to a method for producing a semiconductor structure consisting in forming in a controlled manner through a mask (31) at least one first area made of an insulating material (36) in a first substrate (30) made of a semiconductor material to the level of the mask lower surface (35) prior to and after removing the mask.

Description

 PROCESS FOR THE CONSTRUCTION OF MIXED STACK STRUCTURES

VARIOUS INSULATING AREAS AND / OR CONDUCTION ZONES

LOCAL VERTICAL ELECTRICITY

DESCRIPTION

TECHNICAL FIELD AND PRIOR ART

The invention relates to the field of semiconductor-on-insulator type structures, for example silicon-on-insulator structures also known as SOI.

In these technologies a material substrate, generally semiconductor, supports a buried insulator film, for example silicon dioxide, and a film of superficial semiconductor material.

The realization of such semiconductor on insulator structures is possible by several technologies, such as for example described in the book of Q. Y. Tong and U. Gδsele, Semiconductor Wafer Bonding, Science and Technology, Ed. The Electrochemical Society Series, 1999:

by processes based on the implantation of oxygen in semiconductor material and one or more heat treatment (s) at high temperature (SIMOX type processes),

- by methods based on molecular bonding and with, for example, either:

Mechanical and / or chemical thinning (BSOI type processes), Mechanical thinning and etching with a stop on a sacrificial layer (BESOI type processes),

An embodiment, prior to molecular bonding, of one or more porous zone (s) of embrittlement for subsequent separation,

• a prior implantation to the molecular bonding of gaseous species in a semiconductor plate to generate a weakened zone for a subsequent fracture.

The invention relates primarily to the field of molecular bonding processes and structures made by such methods. Various needs have been expressed:

1) The possibility of having in the same semiconductor structure 230, illustrated in FIG. 2B, zones 233 with a vertical conduction (similar in its behavior to a solid semiconductor, epitaxial, etc.), which separate zones 232a, 232b electrically insulated from the substrate,

2) The possibility of having, as illustrated in FIG. 1B, locally very thin SOI 30 with buried oxide zones 32a, 32b, 32c and SOI with zones 34a, 34b of thicker buried oxide.

3) The possibility of locally having vertical conduction zones, SOI zones with fine buried oxides, and SOI zones with thicker buried oxides and varying thicknesses. 4) The possibility of having SOI with more than two thicknesses of buried oxide. Document FR-2847077 discloses the possibility of producing surface-structured silicon wafers, so that zones comprising, for example, thick oxides 34a, 34b (FIG. 1A) alternate with thin oxide zones 32a, b, c or that oxide zones 232a, 232b alternate with zones 233 without oxide, that is, virgin silicon (FIG. 2A).

According to an exemplary method described in the document FR - 2 847 077, insulating zones or layers are produced in a first semiconductor substrate (silicon will be taken for example) (the example will be taken of the oxide silicon SiO ₂ ) 32a, 32b, 32c, 34a, 34b having different thicknesses. Different techniques can be implemented for the realization of these insulating zones. They will be described later, in connection with FIGS. 3A and following.

Such structured plates can then be glued by molecular bonding onto virgin silicon plates 40 or oxidized silicon plates, the oxide layer 47 of which is of small thickness.

More specifically, in the second semiconductor substrate 40 is carried out an atomic or ion implantation, forming a thin layer 42 which extends substantially parallel to a surface 41 of the substrate 40. In fact is thus formed a layer or an embrittlement plane or fracture delimiting, in the volume of the substrate 40, a lower region 45 intended to constitute a thin film and a region This implantation is generally a hydrogen implantation, but can also be done using other species, or with H / He co-implantation.

The two substrates 30 and 40 thus prepared are then assembled by a "wafer bonding" type technique or by adherent type contact, for example by molecular adhesion or by bonding. As regards these techniques, reference may be made to Q. Y. Tong and U. Gosele Semiconductor Wafer Bonding (Science and Technology), Wiley Interscience Publications.

Part of the substrate 40 is then detached by a treatment to cause a fracture along the embrittlement plane 42. An example of this technique is described in the article by A. J. Auberton-Hervé et al. "Why can Smart-Cut change the future of microelectronics? Published in International Journal of High Speed Electronics and Systems, Vol. 10, No. 1 (2000), p. 131-146.

A component or a semiconductor element or a semiconductor structure according to FIG. 1B is thus formed. According to yet another embodiment illustrated in FIGS. 2A and 2B, a first substrate is a semiconductor substrate 230 (for example: of silicon), in which areas of insulation (for example: SiO 2) 232a, 232b are performed next to raw silicon areas. In a second substrate 240, there is created by atomic implantation or ions, for example hydrogen ions, an embrittlement layer 242 similar to the layer 42 described above. This embrittlement layer delimits, in the volume of the substrate 240, the thin layer 245.

The two substrates 230 and 240 thus prepared are then assembled by one of the techniques already mentioned above ("wafer bonding" or bonding or contact-type contact, for example by molecular adhesion).

The portion of the substrate 240, located on the side opposite to the substrate assembly face 241, is then removed or detached, as already described above in connection with FIG. 1B.

Thus formed is a component or a semiconductor element or a planar mixed semiconductor structure according to the structure of Figure 2B, having an alternation (or any other form of juxtaposition or distribution) of zones 232a, 232b of insulation ( here: oxide SiO2), which can have different thicknesses from each other and semiconductor zones or raw silicon.

Various electronic components can then be produced in the surface layers 45, 245 of semiconductor or silicon, in particular in the part of the layer located above the zones of insulator or of silicon oxide.

Obtaining the structures such as the substrate 30 of FIG. 1A and the substrate 230 of FIG. 2A, according to the teaching of the document FR No. 2,847,077, in particular the following steps illustrated in FIGS. 3A-3E or 4A-4C.

In FIG. 3A, zones 532a, 532b of silicon dioxide are produced on a substrate 530 by LOCOS ("Locally Oxide Silicon") growth through a mask 531. These zones can have the shape pellets or strips or more complex shapes.

The mask is then removed (FIG. 3B), leaving the zones 532a, 532b of silicon oxide.

A planarization step by chemical-mechanical polishing (FIG. 3C) is then carried out, which leads to a substrate having silicon dioxide zones 534a, b juxtaposed with silicon of the substrate itself. This substrate is for example the one used in FIG. 2A.

According to a variant (FIG. 3D), a surface oxidation layer 533 of the substrate is made from the structure of FIG. 3B and then (FIG. 3E) the assembly is planarized by chemical mechanical polishing, to leave a layer 535 of superficial oxidation.

A layer of a few hundred nm (for example 300 nm) can thus be removed, leaving a juxtaposition of areas of silicon dioxide of different thicknesses. This type of substrate is used in Figure IA above.

Another method that can be implemented illustrated in FIGS. 4A-4C. In FIG. 4A trenches 632a, 632b are etched, for example by dry etching through a mask 634, in a silicon substrate 630.

The mask is then removed (FIG. 4B), then the substrate is thermally oxidized on the surface, or a layer of silicon dioxide is deposited, forming a layer 636 of silicon dioxide.

A planarization step by chemical-mechanical polishing (FIG. 4C) is then carried out, which leads to a substrate having zones 634a, b of silicon dioxide juxtaposed with silicon 633 of the substrate itself. This substrate is for example that used in Figure 2B.

According to a variant (FIG. 4D), the assembly of FIG. 4B is flattened, but less than in the case of FIG. 4C, leaving a layer 638 of silicon dioxide remaining. A juxtaposition of silicon dioxide zones of different thicknesses at the surface of the silicon substrate 630 is thus performed. This type of substrate is used in FIG. 1A above.

To summarize, these techniques implement:

a first lithography step for producing a mask (for example nitride) with a view to localized oxidation of the plate,

a second step of oxidation of the open zones in the mask (FIG. 3A), and possibly also of the other zones (FIG. 4B), by oxidative heat treatment, a third step of reducing the surface topology by a chemical mechanical polishing technique. This step is stopped depending on the structure to be achieved, according to whether one seeks to obtain, on the surface of the silicon wafer, an alternation of zones with a fine oxide and zones with a thicker oxide, or alternation of virgin silicon and silicon oxide.

Whichever of these processes is used, it requires thinning by chemical mechanical polishing, which turns out to be a critical step.

As illustrated in FIG. 5A, this step can induce a lack of homogeneity of thickness at various points of the plate. This lack of homogeneity is proportional in particular to the thickness removed.

This problem is encountered when a substrate such as that of Figure 3B or 3D or that of Figure 4B is subjected to a chemical-mechanical polishing.

It is therefore difficult, with this polishing thinning technique, to find operating conditions which make it possible to obtain zones with a fine oxide whose thickness is homogeneous over the entire silicon wafer or even simply at various points of the wafer. silicon plate.

In addition, this chemical mechanical polishing step is also critical when it is performed at the same time on two different materials, for example silicon and silicon oxide, as in the case of the substrate of FIG. 3B or FIG. 4B to arrive at the structure of Figure 3C or 4C respectively.

Indeed, as illustrated in FIG. 5B, it is then difficult to avoid differential polishing ("dishing" in English terminology) between the zones 633 presenting on the surface a semiconductor and the zones 634a, 634b presenting oxide. on the surface: the level of these different zones is not uniform. In FIG. 5B, the oxide zones are "recessed" with respect to the zones of semiconductor material. In the case where the semiconductor is silicon and the oxide of SiO2, on the contrary, "hollows" in the silicon will be obtained because the chemical mechanical polishing is more effective on Si than on SiO2. In both cases, this results in a surface that may pose a problem with regard to any molecular bonding.

The problems discussed above in the case of a SiO2 silicon / silicon oxide system also arise with other semiconductor materials and other insulating materials.

This raises the problem to produce such semiconductor material plates having a structured surface, thus having either varying thicknesses of insulation as in Figure IA, either insulating material alternations and semi ^¬ conductor, as in Figure 2A, and compatible with subsequent molecular bonding.

In particular, it is sought that the thickness homogeneity of the insulating films in the end insulating zones be good. It is also sought that a minimum of topology is present on the surface (and therefore a minimum of "dishing" or of difference of levels between the zones of insulator and the zones of semiconductor, as explained above), especially when there is alternation, on the surface, virgin semiconductor and insulator.

There is the problem of making such structures without resorting to a long chemical mechanical polishing step which poses the problems set out above in connection with FIGS. 5A and 5B.

STATEMENT OF I / INVENTION

The invention firstly relates to a method for producing a semiconductor structure, comprising, the controlled formation, in a first substrate made of a semiconductor material, through a mask, at least a first zone in one insulating material, up to the level of the lower surface of the mask, before or during the removal of the mask. This method does not implement any step of thinning by chemical mechanical polishing, and in particular after removal of the mask, and thus allows to obtain the desired structures without encountering the problems of flatness explained above. Surface cleaning is sufficient to then remove hydrocarbon contaminants, or particles.

The formation of the insulation may comprise a step of controlled growth of an insulating material, up to the level of the lower surface of the mask, and then the removal of the mask. Alternatively, the formation of the insulation may comprise a step of controlled growth of an insulating material, up to the level of the lower surface of the mask. It is then possible to bring the upper surface of the insulation down to the lower surface of the mask.

Alternatively, the upper surface of the insulation is brought to an intermediate level, above the lower surface of the mask, so as to maintain a residual layer of insulation above that surface.

This residual layer can be removed at least partly during the removal of the mask and / or at least partly during the removal of a surface layer covering the mask.

The removal of the residual layer or the thinning of the insulation can be carried out by etching. The substrate may further comprise an insulating layer on the surface, which may optionally be removed after growth or formation of the insulating zone to form an alternation of conductive zones, and / or semiconductors and / or insulating zones.

This insulating layer may have a thickness of, for example, between 1 nm and 50 μm.

The substrate may further comprise, on the surface, a conductive layer, for example made of silicide or metal, optionally covered with a protective layer not removed after removing the mask.

The first substrate may be previously etched in the area in which at least a portion of the insulation is formed, thereby forming an etched area in the semiconductor material.

The area etched in the semi ^¬ conductive material may have a depth of between for example, 1 nm to 10 microns. Depending on the possible layers deposited on the substrate, the etching may also be an etching of an insulating layer of surface and / or of a conductive layer, and possibly a protective layer of this conductive layer. The removal of the mask is preferably performed selectively with respect to the insulating material.

If this shrinkage is not selective, an overgrowth of the insulating material above the level of the lower surface of the mask can be achieved, as already explained above, overgrowth then compensated by a thinning step, as already explained ci above, during the removal of the mask or a step of removing a surface layer covering the mask.

The invention also relates to a method for producing a semiconductor component, comprising:

- formation or controlled growth, in a first zone of a semiconductor substrate, and up to the level of the lower surface a mask covering at least a second zone of the substrate or covering an insulating layer or a conductive layer or a protective layer of such a conductive layer covering at least a second zone of the substrate, an insulation through the mask,

- An attack of the insulation, selective with respect to the mask, and an attack of the mask, selective with respect to the insulator, in order to bring back the upper surface of the insulator to the level defined by the lower surface of the mask.

The attack of the insulation may leave a residual layer of insulation above the level defined by the lower surface of the mask. The residual layer may be removed at least in part during the attack of a surface layer covering the mask and / or at least partly during the attack of the mask.

The substrate may be previously etched in the area in which at least a portion of the insulation is formed, thereby forming an etched area in the semiconductor material.

The area etched in the semi ^¬ conductive material may have a depth of between for example, 1 nm to 10 microns.

The semiconductor material may be silicon or Sil-XGex (0 <x <1) or any other semiconductor material.

The insulating material may be SiO ₂ , or Al ₂ O ₃ , or AlN, or SiON, or Si ₃ N ₄ , or diamond, or HfO ₂ , or a dielectric material with high dielectric constant.

The mask may be, for example, of Si3N4 nitride, or of Al2O3 or AlN. The resulting component can hearth assembled, in particular by molecular bonding with a second substrate, eg also in semiconductor material ^¬ driver, and which may comprise a layer of insulating, e.g. Si02 at its surface. It is then possible to carry out a step of thinning the first and / or second substrate, for example by forming a layer of porous material or by implantation of ions, such as hydrogen ions and possibly helium ions, or by rectification , or by polishing or engraving.

The two substrates may be of different conductivity types.

The first and / or second substrate may include at least one first conductivity area and a second surface conductivity area.

In particular, the second substrate may comprise at least one circuit part or surface component. The material of the first substrate can in turn have electrical conduction zones and / or zones with different dopings.

The formation of insulation through the mask may comprise at least partly a thermal oxidation of the semiconductor substrate, and / or possibly additionally a deposit of insulator or oxide. The reiteration of a method according to the invention makes it possible to produce several insulating zones in the same semiconductor substrate, these different zones being of different geometrical characteristics and / or compositions.

Thus, the invention also relates to a method for producing a semiconductor structure comprising the formation of: a) a first insulating zone in a semiconductor substrate, b) - then the formation of at least a second zone insulating in the same substrate, steps a) and b) being performed according to a method as described above. Steps a) and b) can be performed with different masks.

At least two of the formed insulating zones may have different depths and / or widths in the substrate and / or be formed of different insulating materials.

An insulating film can be made on at least one of the two substrates.

The invention also relates to a semiconductor device, comprising a semiconductor substrate, at least one insulating zone in this substrate, a surface of this insulating zone flush with the surface of the semiconductor material with an accuracy of less than + 5 nm.

It also relates to a semiconductor device, comprising a semiconductor substrate, at least one insulating zone in this substrate, a layer conductive on the substrate, outside the insulating zones, this conductive layer possibly being covered with a protective layer, a surface of the insulating zone flush with the surface of the conductive layer or possibly the protective layer.

The conductive layer may be silicide or metal.

The surface of the insulating zone can be flush with the surface of the conductive layer or possibly the protective layer with an accuracy of less than +5 nm.

A layer of an insulating material may cover the insulating area and the substrate or conductive layer or layer covering the conductive layer.

The semiconductor material may be silicon or Si _x Ge _x (CK x).

The insulating material of the insulating zone may in turn be SiO ₂ , or Al ₂ O ₃ , or AlN, or SiON, or Si ₃ N ₄ , or diamond, or HfO ₂ , or in one dielectric material having a high dielectric constant and / or a combination comprising at least one of these materials.

BRIEF DESCRIPTION OF THE DRAWINGS

- Figures IA - 5B represent known techniques and the problems posed by these techniques, Figures 6A - 6J and 7A - 7D represent steps of a method according to the invention, FIGS. 8A - 8h and 9A - 9E show steps of another method according to the invention,

FIGS. 10A and 10B represent another type of substrate that can be used in the context of the present invention, with a conductive layer,

- Figures HA - HE represent another type of substrate used in the context of the present invention, with a conductive layer and protective layer,

FIGS. 12A to 12C show variant steps of a method according to the present invention,

FIGS. 13A and 13B show a component according to the invention with an insulating layer on the surface,

FIG. 14 represents a component according to the invention with two different insulating zones. FIGS. 15A-18H show examples of methods according to the invention and variants of these examples.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

Figures 6C-6E show a first embodiment of a method according to the invention.

Starting from a substrate 30 (FIG. 6C) made of semiconductor material, in which a trench 34 has been etched through a mask 31, FIG.

6D) growth or formation of an insulating material 36 in a controlled manner, from the cavity 34, so that the surface of this material reaches the interface 35 between the mask and the substrate 30.

The mask 31, which forms a barrier protecting the semiconductor material during growth or formation of the insulator, is then removed, leaving the insulating material flush with the surface of the material 30 (Fig. 6E). The accuracy of the alignment between the two surfaces is compatible with good subsequent molecular bonding, for example this accuracy is less than + 10 nm or + 5 nm. For example, for a Si / SiO 2 mixed surface, it is better than 10 nm (+ 5 nm), especially if it undergoes a chemical cleaning, which leaves them hydrophilic.

The surface of the plate or of the substrate 30 is then flat and constituted by an alternation of semiconductor zones 40, 48 and zones 37 of insulator (FIG. 6E).

The semiconductor plate thus structured can then be cleaned, for example with a view to molecular adhesion with a plate, for example also semiconductor ^¬ virgin or structured material. The adhesion of the plates can be enhanced for example by heat treatment, then at least one of the two plates can be thinned (examples of thinning techniques will be given later).

Such a method does not require a step of thinning by polishing before assembly, unlike in particular the method of the prior art described in connection with Figures IA - 5B. At most, as we shall see later, a slight Polishing can be performed to remove or reduce roughness or surface roughness, for example for molecular bonding.

According to one variant, the insulator 36 increases to a level 39 (FIG. 6D) situated at a height h

(for example between 1 nm and the thickness of the mask 31) above the interface 35 between the mask 31 and the substrate 30, again with very good accuracy. An etching is then performed, preferably selective with respect to the mask 31, at a controlled speed, making it possible to bring the surface of the insulator back to or near the mask 31 - substrate interface 30, with a precision lower than + 10 nm or + 5 nm.

The mask may then be removed (FIG. 6E) and the surface of the substrate 30 may be cleaned, for example with a view to bonding by molecular adhesion. No mechanochemical polishing step is required to bring an insulator level, greater than a semiconductor level of more than 30 nm, to the semiconductor level.

Both the growth of the insulation and its possible etching are carried out at controlled speed.

The growth rate or formation is for example between 0.1 nm / min and 5 nm / min or 10 nm / min.

The etching rate is for example between 0.01 nm / min and a few tens of nm / min, for example 50 nm / min. The realization of a trench in the semiconductor substrate 30 can be obtained, starting from a virgin substrate (for example in silicon, FIG. 6A) by a deposit of a film 32, for example a nitride film, and then engraving of this film.

For example, photosensitive resin is spread on the surface of the film 32.

Then, photolithography is transferred to the resin on the surface of the film 32. After the photosensitive resin has been exposed, an ionic etching step, for example of reactive ionic etching RIE type, is used.

(reactive ion etching) to etch the film 32 and form the mask 31 with the desired patterns. Then the semiconductor plate 30 is itself etched, for example again by ion etching, according to the patterns of the mask 31 (Figure 6C).

According to a variant of the invention, the semiconductor plate 30 is not etched. From the structure of FIG. 7A (layer 32 on semiconductor substrate 30, structure identical to that of FIG. 6A), it is possible to form mask 31 (FIG. 7B) by etching layer 32, and then thermal oxidation of the semiconductor plate 30 through the mask 31 (Figure 7C), but without etching of the semiconductor substrate. The oxidation can take place up to a level 39 higher than that of the mask-semiconductor interface 30. The mask 31 is then removed (FIG. 7D). We then obtains a structure similar to that of Figure 6E.

The surface of the plate or of the substrate 30 is then flat and constituted by an alternation of semiconductor zones 40, 48 and zones 37 of insulator (FIG. 7D, structure similar to that of FIG. 6E) again with a very good accuracy (less than + 10 nm or + 5 nm).

The thus structured plate can be cleaned for molecular bonding.

By cleaning is meant here, and more generally throughout this document, any surface preparation to obtain hydrophilic or hydrophobic all or part surfaces, this preparation may include heat treatments, and / or wet or dry chemical treatments. or in plasma, or even by outcropping of CMP (chemical-mechanical polishing aiming at attenuating the surface microroughness, of less than 20 nm or 30 nm, without risk of causing "dishing", and this step is not intended to thin an excess thickness greater than 20 nm or 30 nm).

In order to obtain a first type of stacked structure, the thus structured and cleaned plate may be glued for example to a second plate 50, for example virgin semiconductor (FIG. 6F) also cleaned for molecular bonding. To increase the adhesion of the plates, the stacked structure is for example subjected to a heat treatment. One of the plates can then be thinned to obtain the superficial film thickness. wanted (Figure 6G). This structure makes it possible alternately to arrange vertical conduction zones and zones comprising an insulator 36 (SOI zones in the case where the layer 52 is made of Si, the zone 36 made of SiO2 and the substrate 30 made of Si).

According to a variant (FIGS. 61, 6J), it is the substrate 30 which, from the structure of FIG. 6F, is thinned, a part - 2 of this substrate being eliminated, leaving the other part 30 - 1 in which the insulation 36 is made. A thin film 30 - 1 of variable thickness is thus obtained.

According to another variant, and in order to obtain a second type of stacked structure, the structured plate of FIG. 6E or 7D and cleaned is bonded for example to a second plate 60, for example in semiconductor, supporting an insulating film surface

(For example a layer 62 of SiO2 oxide) and also cleaned for molecular bonding (Figure 6H).

In the latter approach, the insulating film, for example of oxide 62, of the second plate will advantageously be of thin thickness, for example between a few nm and 50 nm.

To increase the adhesion of the plates, the stacked structure is for example subjected to a heat treatment.

One of the plates is then thinned. If it is the plate 60 which is thinned, we obtain an alternation of zones with variable insulation thickness (alternating between the thickness of the film 62 and that of this film plus that of the zone 36). If it is the structured plate which is thinned, an alternation of zones of variable thin film thickness is obtained (similar to the case of FIG. 6J). Whatever the variant envisaged, the reduction of a part of the thickness of one of the two bonded plates can be done for example by one of the following techniques:

mechanical thinning, for example of the grinding type,

chemical mechanical polishing (but, again, this step only polishes the surface and is not a thinning over a large thickness, for example greater than 20 or 30 nm), thinning by ion etching and / or chemical,

- inclusion before bonding of a zone of weakening buried in the plate to thin

(such as a porous zone or by implantation of gaseous species in one of the substrates, for example hydrogen ions or a hydrogen - helium mixture), and fracture at this weakened zone. or any combination of at least two of these techniques. In the method described above, in connection with FIGS. 6A - 6E or 7A - 7D, the step of growth or formation of the insulator, or the step of growth or formation and then etching of the insulator prior to the step of removing the mask 31. However, it is possible, as illustrated in FIG. 12A, that the growth of the insulator 36 Affects the surface of the mask by forming a surface layer 311 on the mask. For example, in the case of a growth achieved by oxidation, the oxidation can form a surface layer 311 on the mask 31. It is then sought to eliminate this layer 311 before eliminating the mask, since the techniques of elimination of these two elements are generally not the same.

But the removal of the layer 311 on the surface of the mask may eliminate some of the insulation 36.

Therefore, during the growth of the insulator, the growth of the insulator is increased, or the growth thereof is increased to a level higher than that of the mask interface 31 - semi - substrate. conductor, as in Figure 6D or 7C (level 39).

During the removal of the layer 311, a portion of the insulator 36, whose overgrowth (the height h above the plane 35) has been calculated, will also be eliminated so that, during this step, the upper surface of the the insulation is brought near or at the substrate-mask interface.

The adaptation of the height h is possible because of the controlled nature, and in particular the controlled speed, during the growth and etching of the insulation. For example, the layer 311 is removed by HF etching for a time proportional to its thickness. During this same time, the HF burns at a known speed the thickness h of insulation 36 (for example, 1% of severe HF at 6 nm / min.

SiO2 thermal).

After growth of the insulator 36 up to level 39, the following steps are carried out: (i) elimination, for example by etching, of the insulator 36 to reduce its level 39 surface to a first intermediate level 391 (figure

12A),

(ii) the elimination, for example by etching, of the layer 311 and the height h of residual insulation,

(iii) removal of the mask. The two steps i) and ii) can take place in reverse order (ii) and then i)). It is also possible that the elimination of the mask 31 results in the elimination of a part of the insulation 36.

Here again, therefore, the growth of the insulator 36 is preceded by an overgrowth of the latter, or by a growth thereof, so as to reach a level higher than that of the mask interface 31 - substrate semiconductor, as in the case of Figure 6D

(level 39). During the removal of the mask 31, a portion of the insulator 36, the overgrowth (the height h above the plane 35), will also be eliminated so that, during this step, the upper surface of the The insulator reaches the level of the substrate-mask interface. The adaptation of the height h is possible because of the controlled nature, and in particular the controlled speed, during the growth and etching of the insulation. For example, for the removal of an 80 nm mask of Si3N4 with H3PO4 acid at 160 ^° C., it is known that 4 nm of thermal SiO 2 oxide are consumed.

After growth of the insulator 36 to the level 39, it is thus proceeded:

(i) an elimination, for example by etching, of the insulator to bring its surface from level 39 back to an intermediate level 392 (FIG. 12B),

(ii) during the removal or removal of the mask 31, the removal, for example by etching, of the insulation residue located between the level 392 and the level 35, so as to bring the surface of this insulator 392 level at level 35.

Both problems, on the one hand the formation of a surface layer 311 on the mask during the growth of the insulator, on the other hand the elimination of a part of the insulator 36 during the elimination of the mask, can combine. The overgrowth h of the insulator 36 is then adjusted according to the thickness of this insulator which will be consumed, both during the removal of the layer 311 and during the removal of the mask 31.

After growth of the insulator 36 up to level 39, it is then proceeded (FIG. 12C):

(i) elimination, for example by etching, of the insulator to bring its level 39 surface back to a first intermediate level 393, leaving thus remaining a residual thickness (low compared to the initial extra thickness of the insulation),

(ii) removing, for example by etching, the layer 311, which brings the surface of the level 393 insulation back to a second intermediate level 394, thereby reducing the residual layer of insulation,

(iii) during the removal or removal of the mask 31, the elimination, for example by etching, of the insulation residue located between the second intermediate level 394 and the level 35.

The two steps i) and ii) can take place in reverse order (ii) and then i)).

In the 3 cases discussed above in connection with FIGS. 12A-12C, it may be that the insulator was initially grown above the level 35 only to account for an attack of the insulation. during the removal of a layer 311 and / or during the removal of the mask, therefore only until level 391, 392 or 393. Step i) is then deleted.

Overgrowths vary in thickness depending on the growth and shrinkage processes used. Typically, for an Si3N4 nitride mask and an SiO2 insulator, for example, the levels 391 and 393 can be estimated at about 20 nm and the level 392 at about 5 nm above the interface 35.

To simplify the process as much as possible, and to limit the successive steps of removing the overgrowth of the insulation, the mask 31 is selected from a material having an etching selectivity with respect to the insulator 36.

Preferably, the ratio of the etching rate of the mask to the etching rate of the insulator is greater than 2 or 5 or 10 or 100. It is 20 in the case of etching with H3PO4 at 160 ^° C. for Si3N4 mask and thermal SiO2 as insulator.

We now take the example of silicon as a semiconductor material of the substrate 30, thermal silicon dioxide as an insulating material 36 and silicon nitride as a material of the mask 31. The method is that of FIGS. 6A - 6J. In this example, the silicon nitride is advantageous because it constitutes a good oxidation barrier for the silicon and therefore the underlying zones of this mask. For example 10 nm may be sufficient to ensure this barrier effect. SiO2 thermal oxide 36 can therefore be generated in the etched patterns of silicon (FIG. 6D).

During thermal oxidation, the oxygen atoms penetrate the silicon mesh, which causes the silicon to swell. Thanks to this swelling, the surface of the forming oxide approaches the surface of the nitride of the mask 31.

It can be considered that the oxide height generated is approximately twice as large as the height of silicon subjected to oxidation. The rate of formation of the oxide being controlled, it can be stopped when the height generated oxide reaches the level of the interface 35 between the silicon 30 and the nitride mask 31.

In a variant (FIG. 6D), the oxide is formed above the substrate-mask interface 31. The surface 39 of the oxide is then above the silicon-nitride interface. This is the case for example when the etching depth does not allow to obtain the sufficient height of oxide by simply filling the etched area. A selective rate controlled thinning process is then used to stop the surface of the oxide 37 near or at the silicon nitride interface. For example, this thinning process is a chemical etching with hydrofluoric acid diluted to 1%, the attack rate of the thermal oxide SiO 2 is of the order of 6 nanometers per minute, while it does not attack the nitride of the mask 31. More generally, it is possible to use etching, for example chemical etching, at a speed of between 0.01 nm / min and a few tens of nm / min, for example 30 nm / min. or 50 nm / min.

When the surface of the oxide is returned to the silicon nitride interface, the mask 31 can be removed, for example using etching with orthophosphoric acid, for example at 160 ^° C. This attack can be considered as very little active for thermal oxide (a selectivity greater than 20 has been measured). In a variant where the surface of the nitride mask 31 is not attacked by ortho phosphoric acid (especially if this surface has been oxidized during the oxidation of silicon, the case of FIG. 12A), a first attack with a solution of hydrofluoric acid may be considered before the attack by orthophosphoric acid. An oversize h of the oxide above the silicon / nitride interface is then provided, with an allowance corresponding to that which will be removed by the hydrofluoric acid etching. The formation of the oxide being carried out at controlled speed, this extra thickness is also controlled.

Alternatively, where the orthophosphoric acid would attack the silicon oxide 36 (for example at a different solution temperature or dilution), again by controlling the rate of formation of the oxide 36, an extra thickness of this oxide above the silicon-nitride interface, the thickness corresponding to that which will be removed by the attack with orthophosphoric acid.

More generally, an extra thickness of the insulation can therefore be achieved, in the case where the removal of the mask would lead to an attack or a withdrawal of this insulation.

The oxidation is carried out under conditions such that the thermal oxide is formed at a low speed, which makes it possible to easily control the level reached by the oxide pad 36. For example, the oxidation is carried out under a humid atmosphere, for example "steam" or steam water, at a temperature, for example, between 65O ⁰ C and 115O ⁰ C, or between 900 ⁰ C and 1000 ⁰ C. Under these conditions, the oxide is formed at a speed of between a few tenths of a nm / min and a few nm / min as a function of the oxidation temperature, which makes the process quite controllable. This rate is about 5 nm / min at 95O ⁰ C. It also depends on the oxidation time. For more precision on these speeds, reference can be made to conventional microelectronic works such as the Handbook of Semiconductor Technology, Ed W. VS . O 'Mara, Noyes Publications (1990).

According to another example, the oxidation is carried out under a dry oxide atmosphere, at a low temperature, for example between 700 ^° C. and 800 ^° C. or between 700 ^° C. and 1200 ^° C. Under these conditions, the oxide is formed at a speed of about a few tenths of nm / min to a few nm / min. The process remains quite controllable with, for example, a speed of the order of 0.5 nm / min at 900 ⁰ C.

Finally, the surface of the plate is flat and formed by alternating zones 40, 48 of silicon and zones 37 of thermal oxide (FIG. 6E), the alignment accuracy between the surfaces being able to be less than + 10 nm or + 5 nm. The thus structured silicon wafer can be cleaned for molecular bonding.

What is meant by cleaning has already been indicated above. In order to obtain a first type of stacked structure, the silicon plate thus structured and cleaned can be glued for example on a second plate of virgin silicon (Figure 6F) also cleaned for molecular bonding, so as to form a structure called "silicon on insulator partial" (PSOI in English).

In a first gluing mode, the plates are cleaned to render the areas of bare silicon hydrophobic. In a second method of bonding, the plates are cleaned to render the areas of bare silicon hydrophilic, which then have a very fine surface oxide, typically less than 2 nm. To increase the adhesion of the plates, the stacked structure is for example subjected to a heat treatment. In particular in the case of hydrophilic surface bonding, and advantageously, the heat treatment may be used to remove the very thin film of oxide generated by the cleaning.

One of the plates can then be thinned to obtain the desired silicon film thickness 52 (FIG. 6G). This structure makes it possible to alternately have vertical conduction zones and SOI zones.

According to a variant (FIGS. 61, 6J), it is the substrate 30 which is thinned, a part - 2 of this substrate being eliminated, leaving the other part 30 - 1 in which the insulator 36 is formed. Thus, an alternation of thin film 30 - 1 with variable thickness is obtained.

According to another variant, and in order to obtain a second type of stacked structure, the structured and cleaned silicon plate is glued, for example on a second oxidized silicon plate 60 (oxide layer 62) and also cleaned for molecular bonding, so as to form a structure called "multiple silicon on insulator" (MSOI in English, Figure 6H).

In the latter approach, the oxide film 62 of the second plate will advantageously be of thin thickness, for example between a few nm, for example 5 nm, and 50 nm. To increase the adhesion of the plates, the stacked structure is for example subjected to a heat treatment.

One of the plates is then thinned.

If it is the plate 60 of oxidized silicon which is thinned, an alternation of SOI areas with variable oxide thickness (alternating between the thickness of the film 62 and that of this film plus that of the zone 36) is obtained.

In addition, if the structured silicon plate is thinned, an alternation of SOI areas with variable thin film thickness (similar to the case of FIG. 6J) is obtained.

The reduction of a part of the thickness of one of the two bonded plates can be done for example by one of the techniques already mentioned above (mechanical thinning, for example of grinding type, and / or chemical mechanical polishing on a very small thickness (less than 20 nm or 30 nm), and / or thinning by ion etching and / or chemical etching, and / or inclusion before bonding of a zone of embrittlement buried in the plate to thin then fracture).

In the example above, only SiO2 thermal oxide is used. It is also possible to produce a thermal oxide up to a certain level, and / or to make a deposit of another insulator, deposited for example by PECVD in the trench 34.

In this case, however, a thin film of this other insulator may also be deposited on the mask, in which case a preparative CMP type polishing of the surface of the mask 31 may be carried out.

A second embodiment of a method according to the invention will be described with reference to FIGS. 8A-8E. Starting from a substrate 30 (FIG. 8C) made of semiconductor material, covered with an insulating layer 33, in which a trench 34 has been etched through a mask 31, a growth of a material is produced (FIG. 8D). insulation 36 in a controlled manner, for example in the range of speeds between 0.1 nm / min and a few nm / min, for example 5 nm / min or 10 nm / min so that the surface 37 of this material reaches the interface 41 between the mask 31 and the insulator 33. The mask 31 is then removed, leaving the insulating material 36 of the trench flush with the surface of the insulating layer 33 (Figure 8E), and with a tolerance compatible with the molecular bonding, for example with a "dishing" less than about 5 nm. The surface of the plate or of the substrate 30 is then flat and constituted by alternating zones 70, 78 of thin insulation and zones 37 of thicker insulation (FIG. 8E). The semiconductor plate thus structured can then be cleaned, for example for molecular bonding.

It can be assembled with a plate of semiconductor material, virgin or structured. The adhesion of the plates can be enhanced for example by heat treatment, then at least one of the two plates can be thinned (examples of thinning techniques have been given above).

Such a method therefore does not require a step of thinning by mechanochemical polishing before assembly, unlike the prior art. At most, when preparing the plates for bonding by molecular bonding, a slight polishing, allowing to remove asperities of the order of 20 nm or 30 nm at most, can be practiced, but this step is not likely to cause the problems encountered in the prior art and discussed in connection with FIGS. 5A and 5B.

According to one variant, the insulator 36 increases to a level 39 (FIG. 8D) situated at a height h above the mask interface 31 - insulator 33.

An etching is then carried out, preferably selective with respect to the mask 31, at a controlled speed, making it possible to bring the surface of the insulator near or at the level 41 of the mask interface 31 - insulator 33 and with a tolerance compatible with molecular bonding, for example with a "dishing" of less than about 5 nm.

The mask can then be removed (FIG. 8E) and possibly cleaned of the surface of the insulator 33, for example with a view to bonding by molecular adhesion. Again, no thinning step by chemical mechanical polishing is necessary. The homogeneity of the surface obtained is less than 5% or 4% or 3%. Both the growth of the insulator and its possible etching are carried out at a controlled rate, for example as already indicated above, between 0.1 nm / min and a few nm / min, for example 5 nm / min or 10 nm / mn. The realization of the structure of the figure

8C is obtained as follows.

Before depositing or forming the film or the layer 32, a film 331 of initial insulation of a certain thickness, obtained, in the case of SiO ₂ , for example by a high temperature thermal oxidation of a plate, is produced. of silicon (Figure 8A).

The following steps take into account the presence of this insulating film, which is etched (FIG. 8B) after etching the film 32 and before etching the substrate 30 (FIG. 8C), to transfer the patterns defined during the lithography step. .

According to a variant of the invention, the semiconductor plate 30 is not etched. From the structure of FIG. 9A (layers 33 and 32 on semiconductor substrate 30, structure identical to that of FIG. 8A), it is possible to proceed with the formation of the mask 31 (FIG. 9B) by etching of the layer 32, without etching of the layer 33, then by a thermal oxidation of the semiconductor plate 30 through the mask 31

(Figure 9C). The oxidation takes place up to a level 39 higher than that of the interface 41 mask-layer 33.

It is then proceeded to the etching of the insulation thickness, to bring the surface thereof close or at level 41 (Figure 9D), and the removal of the mask 31 (Figure 9E). A structure similar to that of FIG. 8E is then obtained, with the same characteristics of homogeneity.

The surface of the plate or of the substrate 30 is then flat and constituted by alternating zones 70, 78 of thin insulation and zones of thicker insulator (FIG. 9E, structure similar to that of FIG. 8E).

The thus structured plate can be cleaned for molecular bonding.

The term cleaning has already been explained above and is repeated here in the same sense. In particular, a possible chemical mechanical polishing may be practiced, in order to reduce the surface microroughness, of less than 20 nm or 30 nm, without risk of causing the problems posed by the prior art (see FIGS. ) and not in order to thin an excess thickness greater than 20 nm or 30 nm).

In order to obtain a first type of stacked structure, the thus structured and cleaned plate can be glued for example on a second plate 50, for example virgin semiconductor (Figure 8F) also cleaned for molecular bonding. To increase the adhesion of the plates, the stacked structure is for example subjected to a heat treatment.

One of the plates can then be thinned, for example the plate 50 is thinned down to a plane 51, so as to obtain the superficial film thickness

52 wanted (Figure 8F). This structure makes it possible alternately to arrange vertical conduction zones and zones comprising an insulator 36 (SOI zones in the case where the layer 52 is Si, the insulating zones are made of SiO 2 and the substrate 30 is Si).

According to a variant (FIG. 8H), it is the substrate 30 which, from the structure of FIG. 8F, is thinned, a part - 2 of this substrate being eliminated, leaving the other part 30 - 1 in which the insulator 36 is made. A thin film 30 - 1 of variable thickness is thus obtained.

According to another variant, and in order to obtain a second type of stacked structure, the structured plate of FIG. 8E or 9E is cleaned is glued for example on a second plate 60 (FIG.

8G), for example in semiconductor, oxidized on the surface

(layer 62 of oxide) and also cleaned for molecular bonding.

In this latter approach, the oxide film 62 of the second plate will advantageously be of thin thickness, for example between a few nm and 50 nm.

To increase the adhesion of the plates, the stacked structure is for example subjected to a heat treatment.

One of the plates is then thinned. If it is the plate 60 which is thinned, an alternation of zones with a variable insulating thickness (alternating between the thickness of the film 62 plus that of the layer 33 and that of these two films plus that of the zone 36 is obtained. ).

Moreover, if the structured plate is thinned (reference 30a denoting the thinning plane), alternating areas of variable thin film thickness (similar to the case of FIG. 6J) are obtained.

The reduction of a part of the thickness of one of the two bonded plates can be done for example by one or more of the techniques already mentioned (mechanical thinning, and / or chemical mechanical polishing (but, again, this step only polishes the surface and is not thinning over a large thickness, for example greater than 20 or 30 nm), thinning by ionic and / or chemical etching, inclusion prior to bonding an embrittlement zone buried in the plate to thin and fracture at this weakened zone).

As explained above in connection with FIGS. 12A-12C, further growth of the insulator may be appropriate for the case where the growth of the insulator affects the surface of the mask, and / or where the elimination the mask causes that of a part of the insulation 36.

Again, to simplify the process as much as possible, and to limit the successive steps of removing the overgrowth of the insulation, the mask 31 is selected from a material having an etching selectivity with respect to the insulator 36.

Preferably, the ratio of the etching rate of the mask to the etching rate of the insulator is greater than 2 or 5 or 10 or 100.

We now take the example of silicon as a semiconductor material of the substrate, silicon dioxide as an insulating material and silicon nitride as a material of the mask 31. At a controlled rate, thermal oxide 36 in the patterns 34 etched (Figure 8D) the oxygen atoms penetrating into the silicon mesh, which causes swelling of the latter.

The oxide height generated is preferably such that the surface 37 of the oxide corresponds at least to the interface 41 between the nitride 32 and the silicon oxide 331 initially produced.

In a variant, this oxide height may be greater. This is the case for example when only the mask is engraved. The surface 39 of the oxide is then above the initial oxide-nitride interface 41 at a height h (FIG. 8D). A selective thinning process is then used to locate the surface of the oxide at the initial oxide / nitride interface with sufficient precision. For example, this thinning process is a chemical attack by hydrofluoric acid diluted to 1%, the rate of attack of the thermal oxide is of the order of 6 nanometers per minute whereas it do not attack the nitride. More generally, etching, for example chemical etching, can be used at a speed of between 0.01 nm / min and 99 nm / min.

The steps described in connection with FIGS. 6A-6E are transposable in this alternative process, the "nitride / silicon" interface being substituted by the "nitride / initial oxide" interface.

The considerations set out above and relating to the attack by orthophosphoric acid, and possibly hydrofluoric acid, as well as to the use of a possible oversize of the oxide remain valid, as well as the oxidation conditions. thermal.

After the step of removing the nitride, the surface of the plate is formed by an alternation of zones of thermal oxide 70, 78, thin, made initially, and zones 36 of thicker thermal oxide, made in the patterns. engraved. The thus structured silicon wafer is cleaned for molecular bonding.

It is then bonded, for example to a blank silicon 50 plate (FIG. 8F) or to an oxidized silicon plate 60 (FIG. 8G), also cleaned for molecular bonding. The reference 62 designates an oxide layer on the surface of the plate 60. By such a method, structures with, alternately, SOI zones with a variable oxide thickness, called "silicon on multiple insulator" (MSOI in English). It can also be glued with a second plate as obtained in FIG. 8E. Here again, an MSOI structure is obtained.

One of the two plates may be thinned, for example to obtain a silicon film 52, 63 (FIGS. 8F, 8G).

In general, and beyond the example given above concerning SiO 2 and silicon, a variant of this method may allow the realization of a PSOI.

Indeed, at the end of the second method described above (Figure 8E), the plate consists of areas 70, 78 thin insulator and thick areas 36 of insulation, with a flat surface. It is therefore possible to attack this surface in a global manner in order to open onto the semiconductor material 30 after having removed a thickness of insulator corresponding to the thickness of the thin zones 70, 78 of insulation. This oxide attack can be done in different ways: by a chemical solution, by a plasma, by an ion bombardment .... One chooses a type of attack for which the difference between the speed of attack of the semiconductor and that of the insulator is the lowest possible (ratio of attack speeds typically less than 2).

In the case of the SiO ₂ / silicon pair, a solution based on dilute HF is possible, but stopping the attack is then difficult to control. On the other hand, a solution based on NH 4 OH / H 2 O 2 / H 2 O has an attack speed ratio of less than 2, which is more favorable. In the same way, an attack by Ion bombardment has a small difference in attack speed.

To increase the adhesion of the plates during an assembly, the stacked structure is for example subjected to a heat treatment. One of the plates is thinned to obtain the desired silicon film thickness or thicknesses.

The reduction of a part of the thickness of one of the two bonded plates, to obtain the correct thickness of the silicon surface film and to produce the desired MSOI or PSOI structures, can be done for example by one of the techniques described herein. above or by any combination of at least two of these techniques. The realized structures may result from a combination of the various process variants.

The method can be applied to various doping semiconductor plates, within the same plate, for example a silicon plate can be P + doped at vertically conductive zones (where there is no areas of insulation), while other areas are not doped or have different doping. In the case of FIG. 8E, for example, there may be different dopings under the thin layers 70, 78 and under the thick zones 36. This can be obtained, for example before etching for the zone under the mask and after the etching for the zone under the insulator 36. There may also be assembly of a first and a second different doping plates, for example an N-type Si plate 30 and a P-type Si 50, 60 plate. As a variant (FIG. 10A), a film 310 of strong conduction can be produced in the zones protected by the mask 31, for example a silicide or metal film in the zones protected by a nitride mask.

For example, a film 310 of silicide or metal may be deposited before depositing the nitride film 31. Advantageously, this high-conduction film, for example made of silicide or metal, located vertically above the spans (so-called non-etched areas of the substrate 30), is compatible with the temperature of the thermal generation treatment. insulation, for example oxide, in the etched patterns. For example, this film 310 is a tungsten silicide film (WSi2) or a tungsten film (which will subsequently react with the underlying silicon during heat treatment).

Finally, the application of the method of FIGS. 6A-6E to this structure leads (FIG. 10B) to a structuring of the surface comprising an alternation of insulating zones 36 and highly conductive zones 310-1, 310-2. These different areas can be aligned with very good accuracy, unless + _ 10 nm or +; 5 nm. Assembling steps with another substrate, as illustrated in Figures 6F - 6J can be performed with such a structure.

In some cases, the film 310 with strong conduction of the attack used for the removal of the mask 31 (for example by H ₃ PO ₄ ) will be protected. This protection can be a stop layer 410 (by example SiO ₂ ) very fine (see Figure HA which also incorporates the other references of Figure 1OA to designate identical or similar elements). Next steps of etching (FIG. HB), formation (growth or deposition) of the insulator 36 (FIG. HC), removal of the mask (FIG. HD) can take place.

Note that it may be advantageous to have, under a buried insulator, for example under a buried oxide of an SOI, a zone of strong conduction and, elsewhere, of a substrate (for example in silicon) very resistive (for example resistivity greater than 1 kΩ.cm) for microwave applications. In such a case the highly conductive zone 310 may correspond to a ground plane.

It is therefore possible to stop at this step, the component of the figure HD can be used as it is, without removing the protective layer 410. If it further removed this layer 410 protection (Figure HE), a structure such as that of FIGS. 8E and 9E is obtained (but with conductive portions between the insulating areas 36). The steps of FIGS. 8F - 8H can then be applied to this structure.

In the various examples given above, the example of silicon has been given, but a method according to the invention can be applied to other semiconductors than silicon, for the first plate. and / or for the second plate 50, 80, 82. For example, Si (lx) Ge (x) with 0 <x x <çl.

The thickness of the initial oxide film 33 may be in the range of lnm to a few tenths of micrometers, for example 0, 1 or 0.5 microns.

The depth (P in FIGS. 6C and 8C) of the etched patterns 34 in the substrate may be from a few nanometers to a few micrometers, for example between 5 nm and 2 μm. It is zero in the case of FIGS. 7A-7D and 9A-9E, which illustrate embodiments without etching of the substrate.

In general, to achieve the controlled growth of the insulator, one seeks to know the depth p with a certain precision. If this depth is relatively low, some means allow to measure it accurately (for example: optical or mechanical profilometers, or optical interferometer or ellipsometer).

If this depth is greater, we can use the upper plane of the mask 31 as a reference: the thickness of this mask is known precisely (for example by ellipsometry). The insulator is then formed up to a level 39 raised with respect to the mask-substrate interface (FIG. 6D or 7C) or mask-insulating layer (FIGS. 8D and 9C). The difference in height between the surface of the mask and that of the insulator then becomes an order of magnitude of what is measurable with the means stated above. The lateral dimensions (L in the figures

6C and 8C) patterns 34 will typically be in the range from 0.1 μm to a few millimeters, for example 5 mm.

The thickness adaptation of the insulator 36 in the etched patterns 34 may be effected by various techniques allowing a selective etching of the insulator in the etched patterns but not (or little) attack of the mask 31. For example, SiO 2 is attacked with 1% HF, resulting in an etching rate of 6 nm / min, while there is no attack of the Si 3 N 4 mask by this acid. For example, reactive ion etching may be mentioned.

The thickness of the superficial semiconductor films produced by thinning one of the plates of the stacked structure (52 or 30) will for example be between a few nanometers and a few tens of microns, for example between 1 nm and 5 nm and 10 nm. μm or 50 μm or 100 μm.

In the production of MSOI type structures, the thin insulation can also be produced on at least one of the two adhesive plates (deposition, growth, etc.) after the step of preparing the structured surface.

The process can easily be adapted with other insulators than silicon oxide SiO 2, as a film 331 end of initial insulation deposited before the nitride and / or as a thin film of insulation developed on the second plate and / or as a thin film of insulation developed, in an additional step, on a structured plate as shown in Figure 6E. For example, Al ₂ O ₃ , or AlN, or SiON, or Si ₃ N ₄ , or diamond, or HfO ₂ , or any dielectric with a high dielectric coefficient K (conventionally called microelectronic material type "High K"). or any combination comprising at least one of these materials.

The process may be used with other barrier films than Si3N4 nitride film 32. For example, films of A12O3 or AlN may be used. The selective shrinkage with respect to the insulator 331 will, for example, be carried out by chemical etching in a solution of NH ₄ OH: H ₂ O ₂ : H ₂ O for A12O3 and etching in a solution of TMAH (tetra methyl ammonium hydroxide) ) for AlN.

The process can be repeated several times on the same first plate, thus making SOI zones with various thicknesses of buried oxide.

In the process and the various embodiments, it is possible to implement steps for strengthening the molecular bonding (by specific surface cleaning, or activation of the surfaces by plasma, or bonding under a specific atmosphere, or heat treatments, etc.).

It is also possible to carry out a fine polishing of the chemical-mechanical type ("touch polishing" in English) in order to improve the micro-roughness of the oxide surfaces. This treatment is considered as a surface treatment (very low material removal, on the order of 1 nm to 30 nm) as opposed to the polishing thinning process making it possible to make up, on a large scale, a topography of the surfaces of oxide. In the methods explained above, the surface of the insulator 36 can be precisely controlled by limiting the rate of growth or the etch rate when a shrinkage is to be made (as in the case of the level of insulation 32 above). above the mask - semiconductor interface (FIG. 6D) or the initial insulating interface - mask (FIG. 7D), or the conductive film - mask interface (FIG. 10B).

It is furthermore possible, for example by using techniques for the optical measurement of film thicknesses, such as in particular ellipsometry, to accurately align the surface of the insulator 36 made in the patterns and the interface.

In any case, the method according to the invention does not require any thinning by mechanical-chemical polishing, and thus eliminates the risks mentioned in the introduction in connection with FIGS. 5A and 5B.

A chemical mechanical polishing may be practiced during the finishing of the surface or surfaces to be contacted, but, again, this step only polishes the surface to eliminate some surface roughness, having a relief of at most a few nm or at most 20 nm or 30 nm, and is not thinning over a large thickness, for example greater than 20 or 30 nm.

A method according to the invention makes it possible to produce a semiconductor structure, such as that of FIG. 1B, comprising insulating zones, for example at least a first insulating zone at the surface, or buried if the substrate is assembled with a layer. such as the layer 45, this first insulating zone having a first non-zero thickness, preferably uniform, and at least one second insulating zone at the surface, or buried if the substrate is assembled with a layer such as the layer 45, having a second non-zero thickness, preferably uniform, and different from the first thickness.

The method according to the invention makes it possible to produce 3 (or more) different thicknesses of insulation in the same substrate. It is possible, for this, to repeat the process with several levels of masks deposited consecutively. It is also possible to create cavities of different depths, to generate the oxide or the insulator, then to manage the local oxide thickenings by localized engravings.

A method according to the invention makes it possible to produce a semiconductor structure, such as that of FIG. 2B, comprising insulating zones, for example at least a first insulating zone at the surface, or buried if the substrate is assembled with a layer such as that the layer 245, having a first non-zero thickness, preferably uniform, and at least a second surface or buried semi-conductor zone if the substrate is assembled with a layer such as the layer 245.

If it is reiterated, this method makes it possible to produce 2 different thicknesses p and / or two different widths L of insulator in the same substrate, alternating with semiconductor zones. Zones 36 may also be made of a first type of insulator and then zones of another type of insulator.

FIG. 14 represents a semiconductor substrate 30 with insulating zones 36, 36-1 which may be different in their geometrical dimensions (depth and / or width) and / or in the natures of the materials constituting them.

These different insulating zones are obtained by reiteration of a method according to the invention, with different masks during the various stages of formation of the different insulating zones.

A method according to the invention makes it possible to produce a semiconductor structure, such as that of FIG. 8B, comprising insulating zones, for example at least a first insulating zone at the surface or buried, having a first non-zero thickness, preferably uniform, and at least a second surface or buried conductive zone having a second thickness, preferably uniform, possibly different from the first thickness.

Whatever the embodiment envisaged, it is possible to form on a component according to one of the processes above a film of an insulating material. For example, in FIGS. 13A and 13B are shown the structures of FIGS. 6E and 8E with such an insulating film 100, for example in AlN. If there is assembly with another substrate, such a film may be present on the surface of this other substrate. When a component according to the invention is assembled with a second substrate (see for example FIGS. 6F - 6J, or 8F - 8H) the second substrate 50, 60 may comprise at least one zone of first conductivity and one zone of second conductivity in area . It may also include at least one portion of circuit or surface component intended to be the assembly face with the substrate 30. The second substrate may therefore also be structured. The assembly with the first substrate can then implement an alignment of the two substrates.

In an assembly with a second substrate, it has been reported that, to increase the adhesion of the plates or substrates, the stacked structure can be subjected to heat treatment. In addition, if the heat treatment is carried out at high temperature (for example greater than or equal to H ⁰ O ⁰ C), it is possible to cause the disappearance at the bonding interface of an extremely fine residual oxide. In order to facilitate the disappearance of this possible interface oxide, as far as possible, the crystallographic misalignment between the two substrate (for example silicon) assembled plates will be minimized. Other examples of realization will now be given:

First example:

In this first example, the nitride film 32 is deposited by a plasma-assisted vapor deposition technique (PECVD) or by a low pressure deposition technique (LPCVD). This film has a thickness of 80 nanometers (Figure 6A). The patterns 34 are etched in nitride and silicon with a RIE (reactive ion etching) method and have a depth of 50 nanometers in silicon (Figure 6C).

The thermal oxide 36 is obtained in these units by a heat treatment at 900 ^° C. under a steam atmosphere. Its thickness is 100 nanometers. The surface 37 of the oxide generated in the etched patterns is at the nitride-silicon interface.

The thus structured plate is etched with orthophosphoric acid at 140 ^° C. Areas covered with nitride are exposed. The structured plate is flat, smooth, compatible with subsequent molecular bonding.

The plate is then cleaned to remove any hydrocarbons, remove the particles, and make the surface hydrophilic.

This first structured plate is then bonded to a second oxidized silicon plate 60, the thickness of the oxide film being 20 nanometers (FIG. 6H), this second plate being cleaned according to the same procedure. The stacked structure is subjected to a thermal treatment at 110 ^° C. for 2 hours under an argon atmosphere. The second silicon plate of this stacked structure is then thinned, for example by a grinding technique to leave, for example, only 25 microns of silicon 64. in this way obtains a stacked structure of the MSOI type.

A variation of this example can be made to obtain thicker insulator areas in the silicon wafer. The nitride film is deposited for example by LPCVD. The thickness of the nitride film is adapted according to the decrease in thickness which it will undergo during the subsequent thermal oxidation (as explained above in connection with FIG. 12A). For example it will have an initial thickness of 180nm. In this variant, the etched patterns have a silicon etch depth of 1.5 μm (FIGS. 15A, 15B).

A thermal oxidation is used at HO 0 ⁰ C to generate for example about 3 .mu.m of oxide in a humid atmosphere ("steam" type processes, conventional in microelectronics). In this case, the thickness of the nitride film is reduced by oxidation of about 10 nm. After a step of removing the oxide generated, during this oxidation, on the surface of the nitride film, only about 70 nm of nitride remains.

In such a case appear (FIG. 15C) at the edges of the patterns of the zones 700 of overflow of the oxide consisting of a local extra thickness of the oxide with respect to the upper level 701 of the mask 31 (for example nitride mask). These overflow zones represent a very low surface density of the face being structured. The use of a planarization process, according to a technique known elsewhere (see for example the planarization chapter of oxides in the book Chemical Mechanical Planarization of Microelectronic Materials, J. Steigerwald et al. , John Wiley & Sons, New York, 1997) allows the elimination of these overflow areas (Figure 15D). By chemical etching, the insulator height (in this case SiO 2), that is to say the upper level of the oxide of the units, is lowered to bring it to the lower level of the nitride, leaving, with respect to this same level, a slight oversize oxide (Figure 15E) which will be removed when removing the nitride mask 31 (Figure 15F). The upper surface of the oxide 36 then arrives at the lower surface of the mask 31, during or after removal thereof.

The following steps are identical to those of the preceding example from the removal of the nitride mask.

According to another variant (FIG. 16A), a thin layer of oxide 702 is introduced under the nitride film 31 serving as a mask. This oxide film can be produced by an initial thermal oxidation of the silicon wafer 30 and have for example a thickness of 20 nm. The oxide film is, for example, etched just after the etching of the nitride film 31 to allow subsequent etching of the patterns in the silicon 30 with a depth of, for example, 1.5 μm. Such an alternative method makes it possible to obtain, in fine, after steps similar to those described above in relation with FIGS. 15B - 15E, a structured plate having (FIG. 16B) an alternation of zones covered with a film 702. thin oxide (~ 20nm in this variant) and 36 covered areas a thicker oxide (~ 3μm in this example). Again, the upper surface of the oxide 36 then arrives at the lower surface of the mask 31, during or after removal thereof.

Second example:

This second example is a variant of the first example.

The structured plate is bonded to a second non-oxidized silicon plate 50 (FIG. 6F). Because of the cleaning procedure, a native oxide film is present on the exposed silicon area 40, 48 of the structured plate and on the second silicon plate. Thermal treatments at high temperature, for example greater than HO 0 ⁰ C for two hours can remove locally this oxide. In this way, a stacked structure of the PSOI type is obtained. In order to facilitate the disappearance of the possible interface oxide, as far as possible, the crystallographic misalignment between the two adhered silicon wafers will be minimized.

Third example:

In this third example, a first silicon plate 30 is thermally oxidized at 900 ° under a dry oxygen atmosphere, to generate an oxide film 33 of 20 nanometers thick (FIG. 8A). A PECVD nitride film 32 with a thickness of 80 nanometers is deposited on the latter. The reasons 34 are etched in silicon with a RIE (reactive ion etching) method and have a depth of 50 nanometers in silicon (Figure 8C).

The thermal oxide 36 is obtained in these units by a heat treatment at 900 ^° C. under a steam atmosphere. Its thickness is 140 nanometers. The surface 37 of the oxide 36 generated in the etched patterns is at the initially deposited silicon nitride-oxide interface (FIG. 8D).

The thus structured plate is etched with orthophosphoric acid at 140 ^° C. Areas covered with nitride are attacked. The surface of the structured plate is then composed of thermal oxide (FIG. 8C). It is flat, smooth, compatible with a subsequent molecular bonding. The plate is then cleaned in order to remove any hydrocarbons, to remove the particles, to make the surface hydrophilic.

This first structured plate 50 is then bonded to a second unoxidized silicon plate cleaned according to the same procedure (FIG. 8F). The stacked structure is subjected to heat treatment, for example to HO OC ⁰ , for 2 hours under an argon atmosphere. The second silicon plate of this stacked structure is then thinned by a grinding technique to leave, for example, only 20 microns of silicon 52. In this way, a stacked structure of the MSOI type is obtained. The variant of the first example described above in connection with FIGS. 16A and 16B is also a variant of this third example.

Fourth example:

This fourth example is a variant of the third example.

The thickness of the initial oxide film 33 is 10 nanometers (FIG. 8A). The thickness of the nitride film and the depth of the etched patterns in the silicon are identical to the previous example.

The oxide 36 generated in the patterns 34 has a thickness of 120 nanometers. The end of the preparation of this first structured plate is identical to Example 3. This first plate is then bonded to a second oxidized silicon plate, the thickness of the oxide of this second plate being 10 nanometers, made by thermal oxidation at 900 ^° C. under dry oxygen, this second plate being cleaned according to the same procedure.

The stacked structure is subjected to a heat treatment, for example at 110 ^° C. for 2 hours, under an argon atmosphere.

The second silicon wafer of this stacked structure is then thinned by a grinding technique to leave, for example, only 5 microns of silicon 52. In this way, a stacked structure of the MSOI type is obtained (FIG. 8F).

Fifth example: In this fifth example, variant of the fourth example, the second plate 50 is implanted by hydrogen ions, for example at the energy of

70KeV and with doses of 5.10 ¹⁶ at / cm ² , before being cleaned and glued on the first structured plate.

A fracture is induced in this second plate when the stacked structure is subjected, for example, to heat treatment at 500 ^° C. for 30 minutes. A silicon film 52 having a thickness of about 0.5 microns is obtained, secured by molecular bonding with the first structured plate. The stacked structure is then subjected to a heat treatment at high temperature, for example greater than 1000 ⁰ C, so as to consolidate the molecular bonding. In this way, a stacked structure of MSOI type with thin surface silicon film is obtained.

Sixth example: This sixth example is a variant of the third, fourth or fifth example. A film 20 of 20 nanometers of oxide is initially made on a first plate (Figure 8A). An 80 nanometer thick nitride film 32 is made by PECVD on this oxide.

Patterns 34 are etched on this first plate with a depth of 50 nanometers in the silicon.

A thermal oxidation treatment under a steam atmosphere makes it possible to produce an oxide 36 of 160 nanometers thick in engraved patterns.

The surface 37 of the oxide formed in the patterns is higher (about 20 nanometers) than the initial oxide-nitride interface.

Selective etching reduces the thickness of oxide in the patterns without decreasing the nitride thickness. This etching consists of an attack with hydrofluoric acid diluted to 1%. The etching rate of the oxide is of the order of 6 nanometers per minute. In particular, by using optical film thickness measurement techniques, such as for example ellipsometry, this step allows to precisely align the surface of the oxide 36 made in the patterns and the 41 nitride / oxide interface. initial. A flat and smooth surface compatible with a subsequent molecular bonding is then obtained.

Seventh Example: In this seventh example, variant of the first or second example, an 80 nanometer thick nitride film is made by PECVD on a first silicon wafer (FIG. 6A). Patterns 34 are etched on this first plate with a depth of 50 nanometers in the silicon. A thermal oxidation treatment under a steam atmosphere makes it possible to produce an oxide 36 of 120 nanometers in thickness in the etched patterns (FIG. 6D). The surface 39 of the oxide made in the patterns is higher (about 20 nanometers) than the silicon / nitride interface. Selective etching reduces the oxide thickness in the patterns without decreasing the nitride thickness. This etching consists of an attack with hydrofluoric acid diluted to 1%. The attack speed of the oxide is of the order of 6 nanometers per minute. In particular, by using optical film thickness measurement techniques such as ellipsometry, this step allows the surface 37 of the oxide made in the patterns and the initial nitride / oxide interface to be accurately aligned. . A flat and smooth surface compatible with a subsequent molecular bonding is then obtained.

Eighth example:

Starting from a silicon plate 30 (FIG. 17A) on which a film 31 of nitride 50 nm thick is deposited.

A resin film, for example a positive film, is then layered and then insulated through a first mask, the revelation is carried out and a mask is thus formed with the uninsulated resin.

By etching (eg RIE) this resin mask is transferred into the nitride film. The remaining resin is removed.

With the nitride mask 31, the silicon 30 is etched, for example to a depth of 1.5 μm, by dry etching (for example RIE) or by wet etching (for example TMAH) to form patterns 34. then deposits an insulating film 703 (FIG.

17B), for example silica, 1, 6μm thick, and for example by a PECVD deposition technique or by an LPCVD deposition technique.

The silica film is then removed from the nitride zones 31 by using a litho etching technique based on a counter mask principle, according to a technique known elsewhere (see, for example, US Pat. book cited above, chapter on Shallow Trench Isolation, p274). Conventionally after the deposition of oxide, a resin is layered on the oxide, for example a positive one, and insolation is caused by means of a mask. This mask is said against-mask because it is complementary to the first mask used initially and it allows to define a zone 700 of overflow not insolated around the patterns 34 made initially.

After revelation of the resin, there remains a resin mask in line with the patterns. For example, dry etching (RIE) makes it possible to eliminate, by means of this resin mask, the oxide in line with the areas covered by nitride, except in the overflow zones 700 (FIG. 17C).

The zones of overflow of the oxide consist of a local extra thickness of the deposited oxide with respect to the upper level of the mask 31 (nitride mask in this example).

These overflow zones represent a very low surface density of the face being structured. The use of a planarization process, according to a technique known elsewhere (see the chapter on planarization of oxides in the book above) allows the elimination of these zones of overflow. The upper level of the silica film 36 in the patterns is then close to the upper level of the nitride film 31 (FIG. 17D).

By chemical etching, the upper level of the oxide of the units is lowered to bring it to the lower level of the nitride 31 leaving a slight excess of oxide which will be removed during the removal of the nitride (FIG. 17E). For example, if the nitride film has a thickness of 50 nm, an oxide overprint 36 of 5 nm will be left. For example also, the nitride 31 is removed by etching in H3PO4 at 160 ^° C.

After removal of the nitride, the upper level of the oxide 36 of the patterns 34 is at the top of the silicon areas that were underlying the nitride mask (Fig. 17F). The upper surface of the oxide 36 then arrives at the lower surface of the mask 31, during or after removal thereof. A surface preparation (chemical cleaning, surface activation by CMP or plasma ...) can be used to make the surface suitable for subsequent bonding. Such a structured plate can then be glued to another plate, for example silicon or oxidized silicon.

According to a variant of this embodiment, a thin layer of oxide 702 (FIG. 17A) is introduced under the nitride film 31 serving as a mask. This oxide film can be produced by an initial thermal oxidation of the silicon wafer and have a thickness of, for example, 20 nm.

The oxide film is, for example, etched just after the etching of the nitride film to allow subsequent etching of the patterns in the silicon.

Such an alternative method makes it possible to obtain, in fine, after steps similar to those described above in connection with FIGS. 17B - 17E, a structured plate (FIG. 17G) presenting alternating zones covered with a film 702. thin oxide (~ 20 nm in this example) and zones covered with a thicker oxide (~ 1, 5 .mu.m in this example).

Ninth example:

On a silicon plate is deposited, for example by LPCVD, a nitride film, about 120nm thick. A resin film, for example a positive film, is then coated, then it is insulated through a mask, the revelation is carried out and thus, on the silicon substrate 30, a mask 31 is formed with the uninsulated resin (FIG. 18A). By dry etching (ex RIE) is transferred this resin mask in the nitride film. The remaining resin is removed.

With the nitride mask, for example, etching is carried out to a depth of 1.5 μm by means of dry etching (for example RIE) or by wet etching. (eg TMAH) to form, for example, patterns 34 (FIG. 18A).

A first silica film 704 of thickness 2.5 μm, for example, PECVD or LPCVD, is then deposited (FIG. 18B).

This silica film is removed directly above the nitride zones 31 by using these nitride zones as planarization stop pads, making it possible to maintain good homogeneity of elimination by a planarization process, according to a known technique. moreover (see the chapter on planarization of oxides in the book already quoted above).

It is noted, after the first planarization step, that the upper level 360 of the oxide in the pattern 34 is then in depression with respect to the upper level of the nitride mask 31 with a height h of the order of 80 nm (FIG. 18C).

A second silica film 705 of about 0.25 μm in thickness is then deposited, for example by PECVD or by LPCVD (FIG. 18D).

Eventually, such a step can be carried out one or more times and with deposits of thicker or thicker oxide films for each deposition / planarization cycle by using these nitride zones as planarization stop pads.

The silica film is removed above the nitride zones 31 using these nitride zones as planarization stop pads. For example, a planarization process of the same type as above is used. The upper level of the silica film in the patterns is then close to the upper level of the nitride film (FIG. 18E).

By chemical etching, the upper level of the oxide of the units is lowered to the lower level of the nitride, leaving a slight excess of oxide (FIG. 18F) which will be removed during removal of the nitride mask. For example, if the nitride film has a thickness of 50 nm, an excess thickness of oxide of 8 nm will be left. For example too, the nitride can be etched away in H3PO4.

After removal of the nitride, the upper level of the oxide 36 of the patterns 34 is at the upper level of the silicon zones, which were underlying the nitride film 31 (FIG. 18G). The upper surface of the oxide 36 therefore arrives at the lower surface of the mask 31, during or after removal thereof. A surface preparation (chemical cleaning, surface activation by CMP or plasma ...) can be used to make the surface suitable for subsequent bonding. Such a structured plate can then be glued to another plate, for example silicon, whether or not oxidized at the surface, depending on whether the application relates to PSOI or MSOI structures.

According to a variant of this embodiment, a thin layer 702 of oxide is introduced under the nitride film 31 serving as a mask (FIG. 18A). This oxide film 702 can be produced by an initial thermal oxidation of the silicon wafer and have a thickness of, for example, 20 nm.

The oxide film is, for example, etched just after the etching of the nitride film to allow subsequent etching of the patterns in the silicon.

Such an alternative method makes it possible to obtain, in fine, after steps similar to those described above in connection with FIGS. 18A-18F, a structured plate (FIG. 18H) having alternating zones covered with a 702 film. thin oxide (~ 20nm in this example) and zones 36 covered with a thicker oxide (~ l, 5μm in this example).

Claims

Method for producing a semiconductor structure, comprising: - controlled formation, through a mask (31), in a first substrate (30) made of a semiconductor material, of at least a first an insulating material (36) up to the level of the lower surface (35, 41) of the mask, before or during removal of the mask.

2. Method according to claim 1, the formation of insulating material comprising a step of controlled growth of said insulating material, up to the level (35) of the lower surface of the mask, and then removing the mask.

3. The process as claimed in claim 1, the insulation forming step comprising: a) a substep of controlled growth of an insulating material, up to the level of the lower surface (35) of the mask,

- a2) a substep of selective thinning of the insulating material, to bring it back to the level (35) of the lower surface of the mask.

The method of claim 1, wherein the insulation formation comprises:

- a) a sub-step of controlled growth of an insulating material, up to the level of the lower surface (35) of the mask, - a2) a sub-step of selective thinning of the insulating material, to bring it back to a level (391, 394, 394) greater than the lower surface (35) of the mask, thus maintaining a residual layer of insulation above from this surface.

5. The method of claim 4, the residual layer being removed at least in part during removal of the mask.

6. The method of claim 4 or 5, the residual layer being removed at least in part during the removal of a surface layer (311) formed on the mask (31) during sub-step a1).

7. Method according to one of claims 3 to 6, the step a2 being carried out by etching.

The method according to one of claims 3 to 7, wherein the sub step a1) is a controlled growth step of an insulating material (700, 703, 704, 705) above the upper surface (701) of the mask. (31).

9. The method of claim 8, the removal of at least a portion of the insulating material in line with the mask (31) leaving at least one area (700) of overflow.

The method of claim 8, removing at least a portion of the insulating material below the mask (31) being uniform, at least part of the mask acting as stopping zones during this elimination (FIG. 18E).

11. The method of claim 8, the sub-step a1) including a sub-step of growing areas (700) of overflow above the upper surface (701) of the mask (31).

12. Method according to one of the claims

9 or 11, further comprising an elimination of the overflow areas (700).

13. Method according to one of claims 1 to 12, the substrate further comprising an insulating layer (33, 702) surface.

14. The method of claim 13, further comprising a step of removing the insulator layer to form alternating semiconductor zones and insulating zones.

15. The method of claim 13 or 14, the insulating layer (33) having a thickness between 1 nm and 0.5 microns.

16. Method according to one of claims 1 to 15, the substrate further comprising a conductive layer (310) on the surface.

17. The method of claim 16, the conductive layer being silicide or metal or doped Si.

18. The method of claim 16 or

17, the conductive layer being covered with a protective layer (410).

19. The method of claim 18, the protective layer (410) not being removed after removal of the mask (31).

20. Method according to one of claims 1 to 19, comprising an etching of the first substrate (30) of a semiconductor material, through the mask

(31), forming at least one etched area (34) in the semiconductor material, and optionally in the insulating layer (33) surface or optionally in the conductive layer (310) and optionally in its protective layer (410) the insulating material being formed at least in this etched area.

21. The method of claim 20, the etched area (34) having a depth in the first semiconductor material between 1 nm and 10 microns.

22. Method according to one of claims 1 to 21, the removal of the mask being made selectively with respect to the insulating material.

23. A method of producing a semiconductor component, comprising:

the formation or the controlled growth, in a first zone of a semiconductor substrate (30), and up to the level (35) of the lower surface of a mask (31) covering at least a second substrate zone (30), or covering an insulating layer (33) or a conductive layer

(310) or a protective layer (410) of a conductive layer (310) covering at least a second area of the substrate, an insulator (36) through the mask,

- an insulation attack, selective with respect to the mask, and an attack of the mask, selective with respect to the insulation, in order to bring the upper surface (39) of the insulator back to the level (35) defined by the surface lower part of the mask.

24. The method of claim 23, the attack of the insulator leaving a residual layer of insulation above the level (35) defined by the lower surface of the mask (31).

25. The method of claim 24, the residual layer being removed at least in part during the attack of a surface layer (311) covering the mask and / or at least partly during the attack of the mask.

26. Method according to one of claims 23 to 25, comprising an etching (34) of the first region of the substrate.

27. The method of claim 26, the etched area (34) having a depth in the substrate of between 1 nm and 10 microns.

28. Method according to one of the claims

1 to 27, the semiconductor material being silicon or SiX _x Ge _x (CKx <çl).

29. Method according to one of claims 1 to 28, the insulating material being SiO ₂ , or Al ₂ O ₃ , or AlN, or SiON, or Si ₃ N ₄ , or diamond, or HfO ₂ , or a dielectric material with a high dielectric constant.

30. Method according to one of the claims

1 to 29, the mask being made of Si3N4 nitride, or of Al2O3 or AlN.

31. The method according to one of claims 1 to 30, further comprising a step of assembling with a second substrate (50, 60).

32. The method of claim 31, the assembly being made by molecular adhesion.

33. The method of claim 31 or 32, the second substrate being a second semiconductor material.

34. The method of claim 33, the second substrate further comprising a layer (62) of insulation on the second semiconductor material.

35. The method of claim 33 or

34, the first substrate having at least one zone of a first conductivity type, and the second substrate having at least one zone of the opposite conductivity type.

36. The method according to one of claims 31 to 35, further comprising a step of thinning the first and / or second substrate.

37. The method of claim 36, the thinning step of one and / or the other of the substrates being carried out by forming a layer or an embrittlement zone.

38. The method of claim 37, the layer or the weakening zone being formed by a porous silicon layer.

39. The method of claim 38, the formation of a layer or an embrittlement zone being achieved by implantation of ions in the first or second substrate.

40. The method of claim 39, the implanted ions being hydrogen ions or a mixture of hydrogen ions and helium ions.

41. The method of claim 40, the thinning step being obtained by polishing or etching.

42. Method according to one of the claims

31 to 41, the first and / or second substrate having at least one first conductivity zone and a second surface conductivity zone.

43. Method according to one of the claims

33 to 42, the second substrate having at least one surface circuit or component portion.

44. Method according to one of claims 1 to 43, the material of the first substrate comprising zones with different dopings.

45. Method according to one of claims 1 to 44, the formation of insulation through the mask comprising at least partly a thermal oxidation of the semiconductor substrate.

46. The method of claim 45, further comprising a deposit of insulator or oxide.

47. A method of producing a semiconductor structure comprising the formation of: a) a first insulating zone in a semiconductor substrate, b) - then the formation of at least a second insulating zone in the same substrate , steps a) and b) being performed according to one of claims 1 to 45.

48. The method of claim 47, the steps a) and b) being performed with different masks.

49. The method of claim 47 or 48, wherein at least two of the formed insulating regions have different depths and / or widths in the substrate and / or are formed of different insulating materials.

50. Method according to one of claims 1 to 49, an insulating film (100) being formed on at least one of the two substrates.

51. A semiconductor device comprising a semiconductor substrate (30), at least one insulating area (36) in said substrate, a surface of said insulating area being flush with the surface of the semiconductor ^¬ conductive material with a precision of less than +; 5 nm

52. Semiconductor device, comprising a semiconductor substrate (30), at least one insulating zone (36) in said substrate, a conductive layer (310-1, 310-2) on the substrate, outside the insulating zones this conductive layer being optionally covered with a protective layer (410), a surface of the insulating zone flush with the surface of the conductive layer (310) or possibly of the protective layer (410).

53. Device according to claim 52, the conductive layer being silicide or metal or doped Si.

54. Device according to claim 52 or 53, the surface of the insulating zone flush with the surface of the conductive layer (310) or possibly the protective layer (410) with an accuracy less than + 5 nm.

55. Device according to one of claims 52 to 54, further comprising a layer of an insulating material covering the insulating zone and the substrate or the conductive layer (310-1, 310-2) or the protective layer (410). ) covering the conductive layer.

56. Apparatus according to one of claims 51 to 55, the semiconductor material being silicon or SiX _x Ge _x (CKx_ <1).

57. Device according to one of claims 51 to 56, the insulating material of the insulating zone being SiO ₂ , or Al ₂ O ₃ , or AlN, or SiON, or Si ₃ N ₄ , or diamond , or HfO ₂ , or a dielectric material with high dielectric constant.