EP1756948A2 - Agencement reglable en sequence - Google Patents

Agencement reglable en sequence

Info

Publication number
EP1756948A2
EP1756948A2 EP05742037A EP05742037A EP1756948A2 EP 1756948 A2 EP1756948 A2 EP 1756948A2 EP 05742037 A EP05742037 A EP 05742037A EP 05742037 A EP05742037 A EP 05742037A EP 1756948 A2 EP1756948 A2 EP 1756948A2
Authority
EP
European Patent Office
Prior art keywords
frequency
signal
circuit
oscillator
division factor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05742037A
Other languages
German (de)
English (en)
Inventor
Fateh M. Singh
Vincent Fillatre
Abdelilah Faleh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP05742037A priority Critical patent/EP1756948A2/fr
Publication of EP1756948A2 publication Critical patent/EP1756948A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
    • H03J1/0008—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor
    • H03J1/0041—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor for frequency synthesis with counters or frequency dividers

Definitions

  • the frequency tunable arrangement may be, for example, an integrated circuit tuner for selecting a radio frequency signal that conveys information in the form of audio, video, or data or any combination of those.
  • Other aspects of the invention relate to a method of tuning such a frequency tunable arrangement, a signal processing arrangement, a computer program product for a signal processing arrangement, and an information-rendering apparatus.
  • the information-rendering apparatus may be, for example, a video display set.
  • BACKGROUND OF THE INVENTION United States patent 5,983,088 describes a tuner that includes a local oscillator and a mixer for converting an RF signal to an IF signal.
  • the local oscillator has only one tunable oscillating portion for generating an oscillator signal.
  • a controllable frequency divider divides the frequency of the oscillator signal so that the receiver is able to tune through the UHF and VHF bands.
  • the controllable frequency divider is controlled to divide by 1, 2, 4, 8, or 16.
  • a frequency tunable arrangement has the following characteristics.
  • the frequency tunable arrangement comprises a tunable oscillator circuit that provides an oscillator signal.
  • a controllable frequency divider circuit provides a frequency-divided signal on the basis of the oscillator signal.
  • the frequency- divided signal has a frequency that is equal to the frequency of the oscillator signal divided by a division factor.
  • the controllable frequency divider circuit provides any division factor among a set of division factors in which for any division factor it holds that the ratio between that division factor and a lower division factor closest thereto, if existing, does not exceed
  • the invention takes the following aspects into consideration.
  • phase noise is an oscillator characteristic that is of interest.
  • the phase noise of a tuning oscillator determines reception quality.
  • the phase noise of an oscillator is proportional to the tuning range of the oscillator in terms of minimum and maximum oscillator frequency. The greater the ratio between the maximum and the minimum oscillator f equency is, the more significant the phase noise will be.
  • the phase noise of an oscillator also depends on the elements that substantially determine the frequency of the oscillator. These frequency-determining elements may comprise, for example, an inductance and a capacitance. The lesser signal power the frequency-determining elements absorb, the lower the phase noise will be.
  • the controllable frequency divider circuit provides any division factor among a set of division factors in which for any division factor the ratio between that division factor and the lower division factor closest thereto, if existing, does not exceed 1.25.
  • the invention allows tuning throughout a relatively wide frequency range with the tunable oscillator having a tuning range that is only 1.25, or even lower, in terms of ratio between maximum oscillator frequency and minimum oscillator frequency. Since the tuning range of the tunable oscillator can be relatively small, satisfactory phase noise can be achieved with frequency-determining elements of relatively modest quality. Such frequency- determining elements are relatively cheap. A reduction in cost associated with the frequency- determining elements will generally outweigh an increase in cost associated with the controllable frequency divider circuit, which may be somewhat more complex compared with the frequency divider circuit in the prior-art tuner. For these reasons, the invention allows cost reduction.
  • the invention allows frequency- determining elements in the form of an inductance and a capacitance that form part of an integrated circuit substrate. Contrary to the prior-art tuner, the inductance need not be in the form of an external component in order to achieve satisfactory phase noise. This represents an appreciable cost reduction.
  • FIG. 1 is a block diagram that illustrates a video display set.
  • FIG. 2 is a block diagram that illustrated an integrated circuit tuner that forms part of the video display set.
  • FIG. 3 is a table that illustrates division factors and signal frequencies within the integrated circuit tuner.
  • FIG. 4 is a top-view diagram that illustrates a tunable oscillator circuit that forms part of the integrated circuit tuner.
  • FIG. 1 illustrates a video display set VDS that comprises a receiver REC and a display device DPL.
  • the receiver REC receives a radio frequency spectrum RF and retrieves a video signal VID from a desired signal within the radio frequency spectrum RF.
  • the display device DPL displays the video signal VID.
  • the receiver REC comprises a signal processing board SPB and a controller ⁇ ⁇
  • the signal processing board SPB comprises various components among which an integrated circuit tuner ICT and a decoder DEC.
  • the aforementioned elements form part of a signal processing chain that derives the video signal VID from the radio frequency spectrum RF received.
  • the controller CTRL controls this signal processing chain. For example, the controller CTRL controls the integrated circuit tuner ICT so that the integrated circuit tuner ICT selects a desired channel within the radio frequency spectrum RF.
  • FIG. 2 illustrates the integrated circuit tuner ICT.
  • the integrated circuit tuner ICT comprises a front-end circuit FEC, a mixer circuit MIX, and a back-end circuit BEC, which appear in a right-hand portion of FIG. 2.
  • the front-end circuit FEC receives an input signal IN which is, for example, a wideband-filtered version of the radio frequency spectrum RF.
  • the front-end circuit FEC amplifies the input signal IN so as to obtain a mixer input signal MI.
  • the front-end circuit FEC has a variable gain so that the mixer input signal MI is at an appropriate level.
  • the mixer circuit MLX mixes the mixer input signal MI with a mixer oscillator signal MO. Accordingly, an intermediate frequency signal IF is obtained.
  • the back-end circuit BEC processed this intermediate frequency signal IF.
  • the processing may include, for example, filtering and amplification preferably with a variable gain. Accordingly, an output signal OUT is obtained, which can be applied to the decoder DEC illustrated in FIG. 1.
  • the mixer oscillator signal MO is preferably a so-called quadrature signal, which has and in-phase component and a quadrature component.
  • the mixer circuit MIX preferably mixes the mixer input signal MI with the in-phase component and the quadrature component.
  • the mixer circuit MIX suppresses signals at so-called image frequencies. This alleviates filter requirements in the signal path that extends from the radio-frequency spectrum RFF, which is illustrated in FIG. 1, to the mixer input signal MI.
  • the integrated circuit tuner ICT further comprises an assembly of elements that provides the mixer oscillator signal MO.
  • the assembly of elements includes a tunable oscillator circuit TOC, a controllable divider CDIV, three divide-by-two circuits DBTl, DBT2, DBT3, a multiplexer MUX, a quadrature generation circuit QGC, and a frequency control circuit FCC.
  • the frequency control circuit FCC receives a tuning command TC from the controller CTRL illustrated in FIG. 1. In response to the tuning command TC, the frequency control circuit FCC applies appropriate control signals to the tunable oscillator circuit TOC, the controllable divider CDIV, and the multiplexer MUX.
  • the tunable oscillator circuit TOC provides an oscillator signal OS having a frequency that is tunable throughout a relatively small frequency range.
  • the frequency control circuit FCC determines the frequency of the oscillator signal OS.
  • the controllable divider CDIV divides the frequency of the oscillator signal OS. Accordingly, a divided oscillator signal OSA is obtained.
  • the controllable divider CDIV can divide the oscillator frequency by 4, 5, 6, or 7. That is, the controllable divider CDIV provides a division factor that may be 4, 5, 6, or 7.
  • the frequency control circuit FCC determines the division factor.
  • the controllable divider CDIV is preferably arranged so that the divided oscillator signal OSA has a 50% duty cycle.
  • the three divide-by-two dividers DBTl, DBT2, DBT3 form a frequency division chain that provides a twice-divided oscillator signal OSB, a three-times-divided oscillator signal OSC, and a four-times-divided oscillator signal OSD.
  • Divide-by-two divider DBTl divides by two the frequency of the divided oscillator signal OSA. Accordingly, the twice-divided oscillator signal OSB has a frequency that is half (1/2) the frequency of the divided oscillator signal OSA.
  • Divide-by-two divider DBT2 divides by two the frequency of the twice-divided oscillator signal OSB.
  • the three-times-divided oscillator signal OSC has a frequency which is one quarter (1/4) of the frequency of the divided oscillator signal OSA.
  • Divide-by-two divider DBT3 divides by two the frequency of the three-times-divided oscillator signal OSC.
  • the four-times-divided oscillator signal OSD has a frequency which is one eight (1/8) of the frequency of the divided oscillator signal OSA.
  • Each divide-by-two divider DBTl, DBT2, DBT3 is arranged to provide a quadrature output signal, which has an in-phase component and a quadrature component.
  • divide-by-two divider DBTl provides a quadrature output signal BQ that is a quadrature version of the twice frequency-divided oscillator signal OSB.
  • Divide-by-two divider DBT2 provides a quadrature output signal CQ that is a quadrature version of the three-times-divided oscillator signal OSC.
  • Divide-by-two divider DBT3 provides a quadrature output signal DQ that is a quadrature version of and the four-times-divided oscillator signal OSD.
  • the PCT application WO9621270 describes a divide-by-two circuit that provides quadrature signals with relatively great precision. It is advantageous if the divided oscillator signal OSA has 50% duty cycle as mentioned hereinbefore. In that case, the time interval between a rising edge and the following falling edge in the divided oscillator signal OSA is-identical to the time interval between a falling edge and the following rising edge. The time interval corresponds to a 90° phase difference in the twice-divided oscillator signal OSB, whose frequency is half (1/2) the frequency of the divided oscillator signal OSA.
  • the quadrature generation circuit QGC converts the divided oscillator signal OSA into a quadrature output signal AQ, which has the same frequency as the divided oscillator signal OSA.
  • the quadrature generation circuit QGC may comprise, for example, phase-shift networks and synchronization circuits.
  • the oscillator signal OS may serve as a clock signal for the synchronization circuits. A dotted line in FIG. 2 symbolizes this option.
  • the multiplexer MUX selects one of the four quadrature output signals AQ, BQ, CQ, or DQ that the multiplexer MUX receives.
  • the selected quadrature output signal constitutes the mixer oscillator signal MO that is applied to the mixer circuit MIX.
  • the frequency control circuit FCC controls the multiplexer MUX and determines which quadrature output signal is selected.
  • FIG. 3 illustrates respective frequencies of the quadrature output signals AQ, BQ, CQ, DQ, one of which is selected to constitute the mixer oscillator signal MO.
  • FIG. 3 is a table with six columns.
  • a column entitled “OS” specifies the frequency of the oscillator signal OS, which can be tuned throughout a frequency range between 3.6 and 2.88 GHz.
  • a column entitled “CDIV” specifies the four division factors 4, 5, 6, and 7 of the controllable divider CDIV. Each division factor corresponds to a different row in the table.
  • a column entitled “AQ” specifies the frequency of quadrature output signal AQ for each division factor: 4, 5, 6, or 7.
  • FIG. 3 demonstrates that the integrated circuit tuner ICT, which is illustrated in FIG. 2, can be tuned throughout various terrestrial television bands, namely the VHF1, VHF2, VHF3, and UHF band.
  • tuning parameters within the integrated circuit tuner ICT selection of a quadrature output signal AQ, BQ, CQ, or DQ, selection of the division factor 4, 5, 6, or 7, and selection of the frequency of the oscillator signal OS within the frequency range between 3.6 and 2.88 GHz.
  • the frequency control circuit FCC which is illustrated in FIG.
  • the frequency control circuit FCC or the controller CTRL, or both, may be in the form of, for example, a suitably programmed processor.
  • FIG. 4 illustrates the tunable oscillator circuit TOC.
  • the tunable oscillator circuit TOC is formed on an integrated circuit substrate SUB by means of, for example, etching and deposition techniques.
  • the tunable oscillator circuit TOC comprises an inductance Lo and an amplification circuit Ao.
  • the amplification circuit Ao comprises a voltage dependent capacitance Cvar.
  • one or more reverse biased diodes may form the voltage dependent capacitance Cvar.
  • the inductance Lo and the voltage dependent capacitance Cvar are frequency determining elements of the tunable oscillator circuit TOC.
  • a conductive path in the form of a loop constitutes the inductance Lo as illustrated in FIG. 4.
  • the conductive path may be formed, for example, in a conductive interconnection layer formed on the integrated circuit substrate SUB.
  • FIG. 4 thus illustrates that all elements of the tunable oscillator circuit TOC may be formed on the integrated circuit substrate SUB. Full integration has been achieved.
  • the integrated circuit substrate SUB may comprise other elements of the integrated circuit tuner ICT illustrated in FIG. 2, which is symbolized by means of broken lines. The broken lines illustrate a surface in which these other elements may be formed on the integrated circuit substrate SUB.
  • a frequency tunable arrangement comprises a tunable oscillator circuit (TOC) that provides an oscillator signal (OS).
  • a controllable frequency divider circuit provides a frequency-divided signal (mixer oscillator signal MO) on the basis of the oscillator signal (controllable divider CDIV, divide-by-two circuits DBTl, DBT2, DBT3, and multiplexer MUX, constitute a circuit assembly that provides mixer oscillator signal MO on the basis of oscillator signal OS).
  • the frequency-divided signal (MO) has a frequency that is equal to the frequency of the oscillator signal (OS) divided by a division factor.
  • the controllable frequency divider circuit provides any division factor among a set of division factors in which for any division factor the ratio between that division factor and the lower division factor closest thereto, if existing, does not exceed 1.25
  • controllable divider CDIV, divide-by-two circuits DBTl , DBT2, DBT3, and multiplexer MUX provide the following division factors: 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, and 56;
  • the lower division factor closest to division factor 5 is division factor 4, the ratio between these division factors, which is 1.25, does not does not exceed 1.25;
  • the lower division factor closest to division factor 6 is division factor 5, the ratio between these division factors, which is 1.2, does not does not exceed 1.25; for any other division factor that may be considered, the ratio between that division factor and the lower division factor closest thereto does not exceed 1.25;
  • division factor 4 is a special case because there is no lower division factor than 4).
  • controllable frequency divider circuit can further comprise divide-by-two circuits, which are of relatively simple structure and which have relatively modest power consumption. Consequently, the aforementioned characteristic allows cost efficiency or power efficiency, or even both.
  • the tunable oscillator circuit is formed on an integrated circuit substrate (SUB). This allows cost-efficient implementations and, moreover, avoids electromagnetic interferences with other circuits.
  • the tunable oscillator circuit comprises a resonance circuit (inductance
  • Lo voltage dependent capacitance Cvar
  • Lo voltage dependent capacitance
  • the inductance is formed on the integrated circuit substrate (SUB).
  • a controllable frequency divider circuit in accordance with the invention.
  • the multiplexer MUX may be omitted and each divide-by-two divider DBT can be switched between a divide-by-two mode and a non-divide mode: a "divide-by-one" mode.
  • the quadrature output signal DQ may directly constitute the mixer oscillator signal MO.
  • the quadrature generation circuit QGC may be omitted.
  • An additional divide- by-two divider having a quadrature signal output is inserted between the controllable frequency divider CDIV and divide-by-two circuit DBTl. In that case, the frequency of the tunable oscillator circuit TOC should be doubled in order to maintain tuning throughout UHF and VHF television bands.
  • the mixer circuit MIX does not require a quadrature signal so that the controllable divider circuit need not include any special circuitry for generating quadrature signals.
  • the drawings are diagrammatic, each representing only one possible embodiment of the invention. Thus, although a drawing shows different functions as different blocks, this by no means excludes that a single item of hardware or software carries out several functions. Nor does it exclude that an assembly of items of hardware or software or both carry out a function.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Superheterodyne Receivers (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne un agencement réglable en fréquence (ICT) qui comprend un circuit oscillateur réglable (TOC) qui génère un signal oscillateur (OS). Un circuit diviseur de fréquence régulable (CDIV, DBT1, DBT2, DBT3, MUX) génère un signal divisé en fréquence (MO) sur la base du signal oscillateur. Le signal divisé en fréquence possède une fréquence égale à la fréquence du signal oscillateur divisé par un facteur de division. Le circuit diviseur de fréquence régulable génère n'importe quel facteur de division parmi un ensemble de facteurs de division (4, 5, 6, 7, 8) dans lequel pour n'importe quel facteur de division un rapport entre le facteur de division et un facteur de division inférieur le plus proche, s'il existe n'excède pas 1,25.
EP05742037A 2004-06-08 2005-05-25 Agencement reglable en sequence Withdrawn EP1756948A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05742037A EP1756948A2 (fr) 2004-06-08 2005-05-25 Agencement reglable en sequence

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP04102591 2004-06-08
EP04300556 2004-08-25
PCT/IB2005/051717 WO2005122397A2 (fr) 2004-06-08 2005-05-25 Agencement reglable en sequence
EP05742037A EP1756948A2 (fr) 2004-06-08 2005-05-25 Agencement reglable en sequence

Publications (1)

Publication Number Publication Date
EP1756948A2 true EP1756948A2 (fr) 2007-02-28

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ID=34969239

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05742037A Withdrawn EP1756948A2 (fr) 2004-06-08 2005-05-25 Agencement reglable en sequence

Country Status (4)

Country Link
US (1) US7885623B2 (fr)
EP (1) EP1756948A2 (fr)
JP (1) JP2008510407A (fr)
WO (1) WO2005122397A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005018079A1 (de) * 2005-04-19 2006-10-26 Robert Bosch Gmbh Funkwellenempfänger
CN108882118B (zh) * 2018-06-26 2024-04-16 宗仁科技(平潭)股份有限公司 模仿警报声的集成电路和报警装置

Citations (3)

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EP0093433A2 (fr) * 1982-05-04 1983-11-09 Siemens Aktiengesellschaft Circuit oscillateur
US5703540A (en) * 1996-08-27 1997-12-30 Microclock Incorporated Voltage-controlled crystal oscillator with extended range
US20030122630A1 (en) * 1997-02-05 2003-07-03 Fox Enterprises, Inc., A Florida Corporation Programmable oscillator circuit

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GB1560233A (en) 1977-02-02 1980-01-30 Marconi Co Ltd Frequency synthesisers
GB2028727A (en) 1978-08-25 1980-03-12 Maclaren Ltd Andrews Collapsible tripodes
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JP2704324B2 (ja) * 1991-06-05 1998-01-26 松下電器産業株式会社 シンセサイズド信号発生装置
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WO1996021270A1 (fr) * 1994-12-30 1996-07-11 Philips Electronics N.V. Circuit et procede de generation de signaux en quadrature exacte
GB9501243D0 (en) 1995-01-23 1995-03-15 Rca Thomson Licensing Corp Local oscillator using digital handswitching
JP3411743B2 (ja) * 1996-01-23 2003-06-03 ペンタックス株式会社 電子現像型カメラのホワイトバランス調整装置
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EP0093433A2 (fr) * 1982-05-04 1983-11-09 Siemens Aktiengesellschaft Circuit oscillateur
US5703540A (en) * 1996-08-27 1997-12-30 Microclock Incorporated Voltage-controlled crystal oscillator with extended range
US20030122630A1 (en) * 1997-02-05 2003-07-03 Fox Enterprises, Inc., A Florida Corporation Programmable oscillator circuit

Also Published As

Publication number Publication date
WO2005122397A3 (fr) 2006-03-16
US7885623B2 (en) 2011-02-08
JP2008510407A (ja) 2008-04-03
US20080191810A1 (en) 2008-08-14
WO2005122397A2 (fr) 2005-12-22

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