EP1756741A4 - Routen mit lokaler bevorzugter richtung und layout-erzeugung - Google Patents

Routen mit lokaler bevorzugter richtung und layout-erzeugung

Info

Publication number
EP1756741A4
EP1756741A4 EP05755944A EP05755944A EP1756741A4 EP 1756741 A4 EP1756741 A4 EP 1756741A4 EP 05755944 A EP05755944 A EP 05755944A EP 05755944 A EP05755944 A EP 05755944A EP 1756741 A4 EP1756741 A4 EP 1756741A4
Authority
EP
European Patent Office
Prior art keywords
preferred direction
layout generation
local preferred
direction routing
routing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05755944A
Other languages
English (en)
French (fr)
Other versions
EP1756741A2 (de
Inventor
Asmus Hetzel
Anish Malhotra
Deepak Cherukuri
Etienne Jacques
Jon Frankle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/005,448 external-priority patent/US7340711B2/en
Priority claimed from US11/005,169 external-priority patent/US7412682B2/en
Priority claimed from US11/005,162 external-priority patent/US7707537B2/en
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of EP1756741A2 publication Critical patent/EP1756741A2/de
Publication of EP1756741A4 publication Critical patent/EP1756741A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
EP05755944A 2004-06-04 2005-06-04 Routen mit lokaler bevorzugter richtung und layout-erzeugung Withdrawn EP1756741A4 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US57743404P 2004-06-04 2004-06-04
US11/005,448 US7340711B2 (en) 2004-06-04 2004-12-06 Method and apparatus for local preferred direction routing
US11/005,169 US7412682B2 (en) 2004-06-04 2004-12-06 Local preferred direction routing
US11/005,162 US7707537B2 (en) 2004-06-04 2004-12-06 Method and apparatus for generating layout regions with local preferred directions
PCT/US2005/019359 WO2005122027A2 (en) 2004-06-04 2005-06-04 Local preferred direction routing and layout generation

Publications (2)

Publication Number Publication Date
EP1756741A2 EP1756741A2 (de) 2007-02-28
EP1756741A4 true EP1756741A4 (de) 2007-09-05

Family

ID=35503797

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05755944A Withdrawn EP1756741A4 (de) 2004-06-04 2005-06-04 Routen mit lokaler bevorzugter richtung und layout-erzeugung

Country Status (2)

Country Link
EP (1) EP1756741A4 (de)
WO (1) WO2005122027A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7441220B2 (en) 2000-12-07 2008-10-21 Cadence Design Systems, Inc. Local preferred direction architecture, tools, and apparatus
US7707537B2 (en) 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US10331840B2 (en) 2016-01-15 2019-06-25 International Business Machines Corporation Resource aware method for optimizing wires for slew, slack, or noise

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571451A (en) * 1984-06-04 1986-02-18 International Business Machines Corporation Method for routing electrical connections and resulting product
US4910680A (en) * 1987-03-26 1990-03-20 Kabushiki Kaisha Toshiba Wiring method for semiconductor integrated circuit
JPH0290368A (ja) * 1988-09-28 1990-03-29 Fujitsu Ltd Ｓｍｄ部品端子の自動引出し配線データ作成方法
US5224022A (en) * 1990-05-15 1993-06-29 Microelectronics And Computer Technology Corporation Reroute strategy for high density substrates
EP0552935A2 (de) * 1992-01-23 1993-07-28 Hitachi, Ltd. Verfahren zur Ermittlung von Leiterbahnen für elektrische Verbindungen und eine mit solchen Verfahren hergestellte Leiterplatte
US5258920A (en) * 1989-12-26 1993-11-02 General Electric Company Locally orientation specific routing system
US5375069A (en) * 1989-12-18 1994-12-20 Hitachi, Ltd. Wiring routes in a plurality of wiring layers
US20030018947A1 (en) * 2000-12-07 2003-01-23 Steven Teig Hierarchical routing method and apparatus that use diagonal routes
US6526555B1 (en) * 2001-06-03 2003-02-25 Cadence Design Systems, Inc. Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction
US20030088841A1 (en) * 2000-12-06 2003-05-08 Steven Teig Partitioning placement method and apparatus
US20040098678A1 (en) * 2002-11-18 2004-05-20 Steven Teig Method and apparatus for solving an optimization problem

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196563A (ja) * 1992-09-29 1994-07-15 Internatl Business Mach Corp <Ibm> Ｖｌｓｉの配線設計に対するコンピュータ実施可能な過密領域配線方法
US5798936A (en) * 1996-06-21 1998-08-25 Avant| Corporation Congestion-driven placement method and computer-implemented integrated-circuit design tool
US7480885B2 (en) * 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US7003752B2 (en) * 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571451A (en) * 1984-06-04 1986-02-18 International Business Machines Corporation Method for routing electrical connections and resulting product
US4910680A (en) * 1987-03-26 1990-03-20 Kabushiki Kaisha Toshiba Wiring method for semiconductor integrated circuit
JPH0290368A (ja) * 1988-09-28 1990-03-29 Fujitsu Ltd Ｓｍｄ部品端子の自動引出し配線データ作成方法
US5375069A (en) * 1989-12-18 1994-12-20 Hitachi, Ltd. Wiring routes in a plurality of wiring layers
US5258920A (en) * 1989-12-26 1993-11-02 General Electric Company Locally orientation specific routing system
US5224022A (en) * 1990-05-15 1993-06-29 Microelectronics And Computer Technology Corporation Reroute strategy for high density substrates
EP0552935A2 (de) * 1992-01-23 1993-07-28 Hitachi, Ltd. Verfahren zur Ermittlung von Leiterbahnen für elektrische Verbindungen und eine mit solchen Verfahren hergestellte Leiterplatte
US20030088841A1 (en) * 2000-12-06 2003-05-08 Steven Teig Partitioning placement method and apparatus
US20030018947A1 (en) * 2000-12-07 2003-01-23 Steven Teig Hierarchical routing method and apparatus that use diagonal routes
US6526555B1 (en) * 2001-06-03 2003-02-25 Cadence Design Systems, Inc. Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction
US20040098678A1 (en) * 2002-11-18 2004-05-20 Steven Teig Method and apparatus for solving an optimization problem

Also Published As

Publication number Publication date
WO2005122027A2 (en) 2005-12-22
EP1756741A2 (de) 2007-02-28
WO2005122027A3 (en) 2006-05-04

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Effective date: 20140411