EP1756741A4 - Local preferred direction routing and layout generation - Google Patents
Local preferred direction routing and layout generationInfo
- Publication number
- EP1756741A4 EP1756741A4 EP05755944A EP05755944A EP1756741A4 EP 1756741 A4 EP1756741 A4 EP 1756741A4 EP 05755944 A EP05755944 A EP 05755944A EP 05755944 A EP05755944 A EP 05755944A EP 1756741 A4 EP1756741 A4 EP 1756741A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- preferred direction
- layout generation
- local preferred
- direction routing
- routing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US57743404P | 2004-06-04 | 2004-06-04 | |
US11/005,448 US7340711B2 (en) | 2004-06-04 | 2004-12-06 | Method and apparatus for local preferred direction routing |
US11/005,169 US7412682B2 (en) | 2004-06-04 | 2004-12-06 | Local preferred direction routing |
US11/005,162 US7707537B2 (en) | 2004-06-04 | 2004-12-06 | Method and apparatus for generating layout regions with local preferred directions |
PCT/US2005/019359 WO2005122027A2 (en) | 2004-06-04 | 2005-06-04 | Local preferred direction routing and layout generation |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1756741A2 EP1756741A2 (en) | 2007-02-28 |
EP1756741A4 true EP1756741A4 (en) | 2007-09-05 |
Family
ID=35503797
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05755944A Withdrawn EP1756741A4 (en) | 2004-06-04 | 2005-06-04 | Local preferred direction routing and layout generation |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP1756741A4 (en) |
WO (1) | WO2005122027A2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7441220B2 (en) | 2000-12-07 | 2008-10-21 | Cadence Design Systems, Inc. | Local preferred direction architecture, tools, and apparatus |
US7707537B2 (en) | 2004-06-04 | 2010-04-27 | Cadence Design Systems, Inc. | Method and apparatus for generating layout regions with local preferred directions |
US10331840B2 (en) | 2016-01-15 | 2019-06-25 | International Business Machines Corporation | Resource aware method for optimizing wires for slew, slack, or noise |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4571451A (en) * | 1984-06-04 | 1986-02-18 | International Business Machines Corporation | Method for routing electrical connections and resulting product |
US4910680A (en) * | 1987-03-26 | 1990-03-20 | Kabushiki Kaisha Toshiba | Wiring method for semiconductor integrated circuit |
JPH0290368A (en) * | 1988-09-28 | 1990-03-29 | Fujitsu Ltd | Production for automatic lead-out wiring data on terminal of surface mount device parts |
US5224022A (en) * | 1990-05-15 | 1993-06-29 | Microelectronics And Computer Technology Corporation | Reroute strategy for high density substrates |
EP0552935A2 (en) * | 1992-01-23 | 1993-07-28 | Hitachi, Ltd. | A method of determining routes for a plurality of wiring connections and a circuit board produced by such a method |
US5258920A (en) * | 1989-12-26 | 1993-11-02 | General Electric Company | Locally orientation specific routing system |
US5375069A (en) * | 1989-12-18 | 1994-12-20 | Hitachi, Ltd. | Wiring routes in a plurality of wiring layers |
US20030018947A1 (en) * | 2000-12-07 | 2003-01-23 | Steven Teig | Hierarchical routing method and apparatus that use diagonal routes |
US6526555B1 (en) * | 2001-06-03 | 2003-02-25 | Cadence Design Systems, Inc. | Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction |
US20030088841A1 (en) * | 2000-12-06 | 2003-05-08 | Steven Teig | Partitioning placement method and apparatus |
US20040098678A1 (en) * | 2002-11-18 | 2004-05-20 | Steven Teig | Method and apparatus for solving an optimization problem |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06196563A (en) * | 1992-09-29 | 1994-07-15 | Internatl Business Mach Corp <Ibm> | Computable overclowded region wiring to vlsi wiring design |
US5798936A (en) * | 1996-06-21 | 1998-08-25 | Avant| Corporation | Congestion-driven placement method and computer-implemented integrated-circuit design tool |
US7480885B2 (en) * | 2002-11-18 | 2009-01-20 | Cadence Design Systems, Inc. | Method and apparatus for routing with independent goals on different layers |
US7003752B2 (en) * | 2002-11-18 | 2006-02-21 | Cadence Design Systems, Inc. | Method and apparatus for routing |
-
2005
- 2005-06-04 EP EP05755944A patent/EP1756741A4/en not_active Withdrawn
- 2005-06-04 WO PCT/US2005/019359 patent/WO2005122027A2/en not_active Application Discontinuation
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4571451A (en) * | 1984-06-04 | 1986-02-18 | International Business Machines Corporation | Method for routing electrical connections and resulting product |
US4910680A (en) * | 1987-03-26 | 1990-03-20 | Kabushiki Kaisha Toshiba | Wiring method for semiconductor integrated circuit |
JPH0290368A (en) * | 1988-09-28 | 1990-03-29 | Fujitsu Ltd | Production for automatic lead-out wiring data on terminal of surface mount device parts |
US5375069A (en) * | 1989-12-18 | 1994-12-20 | Hitachi, Ltd. | Wiring routes in a plurality of wiring layers |
US5258920A (en) * | 1989-12-26 | 1993-11-02 | General Electric Company | Locally orientation specific routing system |
US5224022A (en) * | 1990-05-15 | 1993-06-29 | Microelectronics And Computer Technology Corporation | Reroute strategy for high density substrates |
EP0552935A2 (en) * | 1992-01-23 | 1993-07-28 | Hitachi, Ltd. | A method of determining routes for a plurality of wiring connections and a circuit board produced by such a method |
US20030088841A1 (en) * | 2000-12-06 | 2003-05-08 | Steven Teig | Partitioning placement method and apparatus |
US20030018947A1 (en) * | 2000-12-07 | 2003-01-23 | Steven Teig | Hierarchical routing method and apparatus that use diagonal routes |
US6526555B1 (en) * | 2001-06-03 | 2003-02-25 | Cadence Design Systems, Inc. | Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction |
US20040098678A1 (en) * | 2002-11-18 | 2004-05-20 | Steven Teig | Method and apparatus for solving an optimization problem |
Also Published As
Publication number | Publication date |
---|---|
WO2005122027A3 (en) | 2006-05-04 |
WO2005122027A2 (en) | 2005-12-22 |
EP1756741A2 (en) | 2007-02-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20061205 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20070806 |
|
DAX | Request for extension of the european patent (deleted) | ||
17Q | First examination report despatched |
Effective date: 20130930 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20140411 |