EP1738337B1 - Digital measuring transducer with current signal - Google Patents
Digital measuring transducer with current signal Download PDFInfo
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- EP1738337B1 EP1738337B1 EP05729510A EP05729510A EP1738337B1 EP 1738337 B1 EP1738337 B1 EP 1738337B1 EP 05729510 A EP05729510 A EP 05729510A EP 05729510 A EP05729510 A EP 05729510A EP 1738337 B1 EP1738337 B1 EP 1738337B1
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- 238000012544 monitoring process Methods 0.000 claims abstract description 19
- 230000000737 periodic effect Effects 0.000 claims abstract description 4
- 230000001105 regulatory effect Effects 0.000 claims description 6
- 238000005259 measurement Methods 0.000 abstract description 16
- 230000001276 controlling effect Effects 0.000 description 7
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C19/00—Electric signal transmission systems
- G08C19/02—Electric signal transmission systems in which the signal transmitted is magnitude of current or voltage
Definitions
- the present invention relates to digital transducers, in particular a transmitter with current signal, in which therefore the measured value is output by controlling a signal current or a supply current.
- Digital transducers are those which comprise at least one microprocessor for processing the measurement signals or for controlling internal functions. Particularly in safety-relevant applications, it is necessary to be able to detect the failure of a transmitter or its components with sufficiently high probability.
- NAMUR Recommendation NE43 proposes that for meters with a measurement signal current in a band range between 4 and 20 mA, a device failure with an error signal current outside this band range, e.g. not more than 3.6 mA or at least 21 mA is signaled.
- Such a transducer is from the utility model DE 299 17 651 U1 known.
- the present invention is based on the object of providing a digital signal converter which reliably signals the failure of its microprocessor.
- the object is achieved by the transmitter according to the independent claim 1.
- the transmitter comprises a microprocessor with a reset input and a clock output for providing a periodic clock signal; a monitoring circuit having a clock input and a reset output; and a current regulator for outputting a measurement signal current, which measurement signal current in measurement operation in a first band region represents a measurement value; and signal an error outside the first band range; in which
- the clock input of the monitoring circuit is connected to the clock output of the microprocessor
- the reset input of the microprocessor is connected to the reset output of the monitoring circuit, in case of failure of the clock signal at the reset output of the monitoring circuit, a reset signal is output periodically, further
- the transmitter comprises a comparator circuit having a first input connected in a low pass to the reset output of the monitoring circuit, a second input to which a reference voltage is applied, and an output connected to an input of the current regulator, wherein after repeated output of the reset signal, the voltage at the first input of the comparator circuit exceeds the reference voltage, so that at the output of the comparator an actuating signal is applied, which causes the current controller to output an error signal current outside the first band range.
- the first band range is for the measurement signal current for example 4 to 20 mA.
- the error signal current should be at least 21 mA or at most 3.6 mA.
- the error signal current is regulated to 22 mA.
- the monitoring circuit may comprise, for example, a digital counter, which counts from a start value and, when exceeding or falling below a limit, causes the output of a reset signal at the reset output.
- the counter is reset to its start value both by each pulse of the clock signal of the microprocessor and by the reset signal of the monitoring circuit.
- the limit value is selected in such a way to the counting speed of the counter and the clock frequency of the microprocessor, that the limit value is never under or exceeded when the clock signal is functioning.
- the limit is selected so that after sending a reset signal is sufficient time to restart the microprocessor after a simple clock error, so that the clock signal is output again at the output of the microprocessor before the limit is reached. Therefore, only when a reset signal has not led to a successful reset in the expected time, a new reset signal is issued.
- the low pass via which the output signal of the monitoring circuit is supplied to the comparator circuit, comprises an RC element.
- the comparator circuit preferably comprises a first operational amplifier.
- the current regulator comprises two parallel current regulator circuits, of which the first current regulator circuit regulates the measurement signal current in the first band region and the second current regulator circuit regulates the error signal current to a value outside the first band region.
- the second current regulator circuit can for this purpose comprise a second operational amplifier, of which an input is connected to the output of the comparator circuit, and whose output is connected to the base of a transistor, via which the error signal current is adjusted. It is currently preferred that the internal power supply of the second operational amplifier for controlling the error signal current is independent of the power supply of the current control circuit for controlling the measurement signal current. In this way, it is ensured that the error signal current can be adjusted even when the voltage supply of the current regulator circuit for the measuring signal current has failed.
- the first current regulator circuit for controlling the measurement signal current may be of similar construction to the second current regulator circuit, wherein in a currently preferred embodiment the transmitter comprises an ASIC and parts of the first current regulator circuit are integrated into the ASIC.
- Fig. 1 a block diagram of a transmitter according to the invention
- FIG. 2 shows the time course of the signals at the test points designated in FIG. 1; FIG. and
- FIG. 3 shows an example of a current regulator for implementing the present invention.
- the circuit shown in Fig. 1 of a transmitter comprises a microprocessor 1 with a reset input and a clock output or trigger output for providing a periodic clock signal, which is shown as a curve a in Fig. 2. Furthermore, a current regulator 2 is provided, which regulates the supply current of the transmitter as a measurement signal current between 4 and 20 mA. In the normal measuring operation, the current controller 2 receives an actuating signal, which represents a measured value, from the microprocessor 1 and regulates the supply current to a value corresponding to the actuating signal.
- the transmitter further comprises monitoring circuit 3 with a clock input and a reset output, whose signal is shown as curve b in FIG.
- the reset output of the monitoring circuit remains at zero. However, if the clock signal fails, then a reset pulse is output at the reset output, which is repeated after a certain time, if the reset was unsuccessful, and the microprocessor clock signal 1 continues to be absent.
- the signal of the reset output is also fed via a low-pass filter 5 to the input of a comparator 4, which comprises a first operational amplifier.
- the signal curve at the comparator input can be seen from the curve c in FIG. If the reset is unsuccessful, several reset pulses lead to a voltage increase until the reference voltage at the reference input of the comparator 4 is exceeded.
- the voltage at the output of the comparator 4 is increased, and output as a fault signal to the current controller 2, which now outputs the supply current to an error signal current of 22 mA, for example.
- the general course of the supply current can be seen schematically from the curve d in FIG. Accordingly, the value of the supply current in the normal measuring operation in the band between 4 and 20 mA and is regulated to 22 mA after a short undefined transition, which is indicated by the X in the curve.
- the current controller 2 shown comprises two current regulator circuits connected in parallel, of which the first current regulator circuit regulates the measurement signal current in the first band region and the second current regulator circuit regulates the error signal current to a value outside the first band region.
- Both current regulator circuits essentially each comprise a current regulating transistor 21, 25 whose base is connected to the output of an operational amplifier 22, 26.
- a control voltage for controlling the measuring signal current or the error signal current.
- the second operational amplifier 26 of the second current regulator circuit of the output of the comparator 4 is connected via a series resistor R2. The reference input of the second operational amplifier is grounded. When now the output of the comparator is also grounded, the output signal of the second operational amplifier is grounded and the second transistor 25 is off.
- the comparator 4 If, on the other hand, a sustained failure of the clock of the microprocessor, the comparator 4 outputs a control signal Uv fault current , then the second operational amplifier 26 outputs a voltage which reduces the resistance of the second transistor 25, so that a current flows through the second transistor, which causes a total supply current of 22 mA.
- the resistance of the main electronics which is supplied by the supply current, and which is not shown here in detail, is summarized in this illustration by the resistor 27 and R HE .
- the first current regulator circuit for controlling the measurement signal current is in principle similar to the second current regulator circuit, wherein in the illustrated embodiment, the transmitter comprises an ASIC 24, and the operational amplifier 22 of the first current regulator circuit is integrated into the ASIC 24.
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measurement Of Current Or Voltage (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Amplifiers (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
Description
Die vorliegende Erfindung betrifft digitale Messumformer, insbesondere einen Messumformer mit Stromsignal, bei dem also der Messwert durch eine Regelung eines Signalstroms bzw. eines Speisestroms ausgegeben wird. Digitale Messumformer sind solche, die mindestens einen Mikroprozessor zur Aufbereitung der Messsignale bzw. zur Steuerung interner Funktionen umfassen. Insbesondere in sicherheitsrelevanten Anwendungen ist es erforderlich den Ausfall eines Messumformers bzw. seiner Komponenten mit ausreichend hoher Wahrscheinlichkeit erkennen zu können. In der NAMUR-Empfehlung NE43 wird beispielsweise vorgeschlagen, dass bei Messgeräten mit einem Messsignalstrom in einem Bandbereich zwischen 4 und 20 mA, ein Geräteausfall mit einem Fehlersignalstrom außerhalb dieses Bandbereichs, z.B. nicht mehr als 3,6 mA bzw. mindestens 21 mA signalisiert wird.The present invention relates to digital transducers, in particular a transmitter with current signal, in which therefore the measured value is output by controlling a signal current or a supply current. Digital transducers are those which comprise at least one microprocessor for processing the measurement signals or for controlling internal functions. Particularly in safety-relevant applications, it is necessary to be able to detect the failure of a transmitter or its components with sufficiently high probability. For example, NAMUR Recommendation NE43 proposes that for meters with a measurement signal current in a band range between 4 and 20 mA, a device failure with an error signal current outside this band range, e.g. not more than 3.6 mA or at least 21 mA is signaled.
Ein derartiger messumformer ist aus der Gebrauchsmusterschrift
Der vorliegenden Erfindung liegt nun die Aufgabe zugrunde einen digitalen Messumformer bereitzustellen, der den Ausfall seines Mikroprozessors sicher signalisiert. Die Aufgabe wird erfindungsgemäß gelöst durch den Messumformer gemäß des unabhängigen Patentanspruchs 1.The present invention is based on the object of providing a digital signal converter which reliably signals the failure of its microprocessor. The object is achieved by the transmitter according to the independent claim 1.
Der erfindungsgemäße Messumformer umfasst einen Mikroprozessor mit einem Reset-Eingang und einem Taktausgang zum Bereitstellen eines periodischen Taktsignals; eine Überwachungsschaltung mit einem Takt-Eingang und einem Reset-Ausgang; und einen Stromregler zur Ausgabe eines Messsignalstroms, welcher Messsignalstrom im Messbetrieb in einem ersten Bandbereich einen Messwert repräsentiert; und außerhalb des ersten Bandbereichs einen Fehler signalisiert; wobeiThe transmitter according to the invention comprises a microprocessor with a reset input and a clock output for providing a periodic clock signal; a monitoring circuit having a clock input and a reset output; and a current regulator for outputting a measurement signal current, which measurement signal current in measurement operation in a first band region represents a measurement value; and signal an error outside the first band range; in which
der Takt-Eingang der Überwachungsschaltung mit dem Taktausgang des Mikroprozessors verbunden ist, der Reset-Eingang des Mikroprozessors mit dem Reset-Ausgang der Überwachungsschaltung verbunden ist, bei Ausfall des Taktsignals am dem Reset-Ausgang der Überwachungsschaltung ein Reset-Signal periodisch ausgegeben wird, wobei fernerthe clock input of the monitoring circuit is connected to the clock output of the microprocessor, the reset input of the microprocessor is connected to the reset output of the monitoring circuit, in case of failure of the clock signal at the reset output of the monitoring circuit, a reset signal is output periodically, further
der Messumformer eine Komparatorschaltung aufweist mit einem ersten Eingang, der über einen Tiefpass mit dem Reset-Ausgang der Überwachungsschaltung verbunden ist, mit einem zweiten Eingang, an dem eine Referenzspannung anliegt, und mit einen Ausgang, der mit einem Eingang des Stromreglers verbunden ist, wobei nach wiederholter Ausgabe des Reset-Signals die Spannung am ersten Eingang der Komparatorschaltung die Referenzspannung übersteigt, so dass am Ausgang des Komparators ein Stellsignal anliegt, welches den Stromregler veranlasst ein Fehlersignalstrom außerhalb des ersten Bandbereichs auszugeben.the transmitter comprises a comparator circuit having a first input connected in a low pass to the reset output of the monitoring circuit, a second input to which a reference voltage is applied, and an output connected to an input of the current regulator, wherein after repeated output of the reset signal, the voltage at the first input of the comparator circuit exceeds the reference voltage, so that at the output of the comparator an actuating signal is applied, which causes the current controller to output an error signal current outside the first band range.
Wie eingangs angedeutet, beträgt der erste Bandbereich für den Messsignalstrom beispielsweise 4 bis 20 mA. In diesem Falle sollte der Fehlersignalstrom mindestens 21 mA oder höchstens 3,6 mA betragen. In einer derzeit bevorzugten Ausführungsform wird der Fehlersignalstrom auf 22 mA geregelt.As indicated at the outset, the first band range is for the measurement signal current for example 4 to 20 mA. In this case, the error signal current should be at least 21 mA or at most 3.6 mA. In a presently preferred embodiment, the error signal current is regulated to 22 mA.
Die Überwachungsschaltung kann beispielsweise einen digitalen Zähler umfassen, welcher von einem Startwert aus zählt und bei Über- oder Unterschreiten eines Grenzwertes die Ausgabe eines Reset-Signals am Reset-Ausgang veranlasst. Der Zähler sowohl durch jeden Puls des Taktsignals des Mikroprozessors als auch durch das Reset-Signal der Überwachungsschaltung auf seinen Startwert zurückgesetzt wird. Der Grenzwert ist dabei so auf die Zählgeschwindigkeit des Zählers und die Taktfrequenz des Mikroprozessors gewählt, dass der Grenzwert bei funktionierendem Taktsignals nie unter bzw. überschritten wird. Weiterhin ist der Grenzwert so gewählt, dass nach Aussenden eines Reset-Signals hinreichend Zeit bleibt, um den Mikroprozessor nach einer einfachen Taktstörung erneut zu starten, so dass am Ausgang des Mikroprozessor wieder das Taktsignal ausgegeben wird bevor der Grenzwert erreicht wird. Daher wird erst dann, wenn in der zu erwartenden Zeit ein Reset-Signal nicht zu einem erfolgreichen Reset geführt hat, ein erneutes Reset-Signal ausgegeben.The monitoring circuit may comprise, for example, a digital counter, which counts from a start value and, when exceeding or falling below a limit, causes the output of a reset signal at the reset output. The counter is reset to its start value both by each pulse of the clock signal of the microprocessor and by the reset signal of the monitoring circuit. The limit value is selected in such a way to the counting speed of the counter and the clock frequency of the microprocessor, that the limit value is never under or exceeded when the clock signal is functioning. Furthermore, the limit is selected so that after sending a reset signal is sufficient time to restart the microprocessor after a simple clock error, so that the clock signal is output again at the output of the microprocessor before the limit is reached. Therefore, only when a reset signal has not led to a successful reset in the expected time, a new reset signal is issued.
Es ist derzeit bevorzugt, dass der Tiefpass, über den das Ausgangssignal der Überwachungsschaltung der Komparatorschaltung zugeführt wird, ein RC-Glied umfasst. Die Komparatorschaltung umfasst vorzugsweise einen ersten Operationsverstärker.It is presently preferred that the low pass, via which the output signal of the monitoring circuit is supplied to the comparator circuit, comprises an RC element. The comparator circuit preferably comprises a first operational amplifier.
In einer derzeit bevorzugten Ausgestaltung der Erfindung umfasst der Stromregler zwei parallele Stromreglerschaltungen, von denen die erste Stromreglerschaltung einen den Messsignalstrom in dem ersten Bandbereich regelt und die zweite Stromreglerschaltung den Fehlersignalstrom auf einen Wert außerhalb des ersten Bandbereiches regelt.In a presently preferred embodiment of the invention, the current regulator comprises two parallel current regulator circuits, of which the first current regulator circuit regulates the measurement signal current in the first band region and the second current regulator circuit regulates the error signal current to a value outside the first band region.
Die zweite Stromreglerschaltung kann hierzu einen zweiten Operationsverstärker umfassen, von dem ein Eingang mit dem Ausgang der Komparatorschaltung verbunden ist, und dessen Ausgang mit der Basis eines Transistors verbunden ist, über den der Fehlersignalstrom eingestellt wird. Es ist derzeit bevorzugt, dass die interne Spannungsversorgung des zweiten Operationsverstärkers zur Regelung des Fehlersignalstroms unabhängig von der Spannungsversorgung des Stromregelungsschaltung zur Regelung des Messsignalstroms erfolgt. Auf diese Weise ist gewährleistet, dass der Fehlersignalstrom auch dann eingestellt werden kann, wenn die Spannungsversorgung der Stromreglerschaltung für den Messsignalstrom ausgefallen ist.The second current regulator circuit can for this purpose comprise a second operational amplifier, of which an input is connected to the output of the comparator circuit, and whose output is connected to the base of a transistor, via which the error signal current is adjusted. It is currently preferred that the internal power supply of the second operational amplifier for controlling the error signal current is independent of the power supply of the current control circuit for controlling the measurement signal current. In this way, it is ensured that the error signal current can be adjusted even when the voltage supply of the current regulator circuit for the measuring signal current has failed.
Die erste Stromreglerschaltung zur Regelung des Messsignalstroms kann ähnlich aufgebaut sein wie die zweite Stromreglerschaltung, wobei bei einer derzeit bevorzugten Ausführungsform der Messumformer einen ASIC umfasst und Teile der ersten Stromreglerschaltung in den ASIC integriert sind.The first current regulator circuit for controlling the measurement signal current may be of similar construction to the second current regulator circuit, wherein in a currently preferred embodiment the transmitter comprises an ASIC and parts of the first current regulator circuit are integrated into the ASIC.
Weitere Einzelheiten und Gesichtspunkte der Erfindung ergeben sich aus den abhängigen Ansprüchen, und der Beschreibung des in den Zeichnungen dargestellten Ausführungsbeispiels. Es zeigt:Further details and aspects of the invention will become apparent from the dependent claims, and the description of the embodiment shown in the drawings. It shows:
Fig. 1: ein Blockschaltbild eines erfindungsgemäßen Messumformers;Fig. 1: a block diagram of a transmitter according to the invention;
Fig. 2: den Zeitlichen Verlauf der Signale an den in Fig. 1 bezeichneten Testpunkten; undFIG. 2 shows the time course of the signals at the test points designated in FIG. 1; FIG. and
Fig.3: ein Beispiel für einen Stromregler zur Realisierung der vorliegenden Erfindung.3 shows an example of a current regulator for implementing the present invention.
Die in Fig. 1 gezeigte Schaltung eines erfindungsgemäßen Messumformers umfasst einen Mikroprozessor 1 mit einem Reset-Eingang und einem Taktausgang bzw. Triggerausgang zum Bereitstellen eines periodischen Taktsignals, welches als Kurve a in Fig. 2 dargestellt ist. Weiterhin ist ein Stromregler 2 vorgesehen, welcher den Speisestrom des Messumformers als Messsignalstrom zwischen 4 und 20 mA regelt. Der Stromregler 2 erhält im normalen Messbetrieb ein Stellsignal, welches einen Messwert repräsentiert, von dem Mikroprozessor 1 und regelt den Speisestrom auf einen dem Stellsignal entsprechenden Wert. Der Messumformer umfasst weiterhin Überwachungsschaltung 3 mit einem Takt-Eingang und einem Reset-Ausgang, dessen Signal als Kurve b in Fig. 2 dargestellt ist. Solange das Taktsignal des Mikroprozessors empfangen wird, bleibt der Reset-Ausgang der Überwachungsschaltung auf Null. Wenn allerdings das Taktsignal ausbleibt, dann wird am Reset-Ausgang ein Reset-Puls ausgegeben, der nach einer bestimmten Zeit wiederholt wird, wenn der Reset nicht erfolgreich war, und das Taktsignal des Mikroprozessors weiterhin 1 ausbleibt. Das Signal des Reset-Ausgangs wird zudem über einen Tiefpass 5 dem Eingang eines Komparators 4 zugeführt, der einen ersten Operationsverstärker umfasst. Der Signalverlauf am Komparatoreingang ist der Kurve c in Fig. 2 zu entnehmen. Bei erfolglosem Reset führen mehrere Reset-Pulse zu einem Spannungsanstieg, bis die Referenzspannung an dem Referenzeingang des Komparators 4 überschritten wird. Daraufhin wird die Spannung am Ausgang des Komparators 4 heraufgesetzt, und als Fehlerstellsignal an den Stromregler 2 ausgegeben, der nun den Speisestrom auf einen Fehlersignalstrom von beispielsweise 22 mA ausgibt. Der allgemeine Verlauf des Speisestroms ist schematisch der Kurve d in Fig. 2 zu entnehmen. Demnach liegt der Wert des Speisestroms im normalen Messbetrieb im Band zwischen 4 und 20 mA und wird nach einem kurzen undefinierten Übergang, der durch das X in der Kurve angedeutet ist, auf 22 mA geregelt.The circuit shown in Fig. 1 of a transmitter according to the invention comprises a microprocessor 1 with a reset input and a clock output or trigger output for providing a periodic clock signal, which is shown as a curve a in Fig. 2. Furthermore, a current regulator 2 is provided, which regulates the supply current of the transmitter as a measurement signal current between 4 and 20 mA. In the normal measuring operation, the current controller 2 receives an actuating signal, which represents a measured value, from the microprocessor 1 and regulates the supply current to a value corresponding to the actuating signal. The transmitter further comprises
Einzelheiten des Stromreglers 2 sollen kurz anhand von Fig. 3 erläutert werden.Details of the current controller 2 will be explained briefly with reference to FIG. 3.
Der gezeigte Stromregler 2 umfasst zwei parallel geschaltete Stromreglerschaltungen, von denen die erste Stromreglerschaltung einen den Messsignalstrom in dem ersten Bandbereich regelt und die zweite Stromreglerschaltung den Fehlersignalstrom auf einen Wert außerhalb des ersten Bandbereiches regelt.The current controller 2 shown comprises two current regulator circuits connected in parallel, of which the first current regulator circuit regulates the measurement signal current in the first band region and the second current regulator circuit regulates the error signal current to a value outside the first band region.
Beide Stromreglerschaltungen umfassen im wesentlichen jeweils einen Stromregeltransistor 21, 25 dessen Basis jeweils an dem Ausgang eines Operationsverstärker 22, 26 angeschlossen ist. An den Eingängen der Operationsverstärker 22, 26 liegt jeweils eine Stellspannung zur Regelung des Messsignalstroms bzw. des Fehlersignalstroms. An dem zweiten Operationsverstärker 26 der zweiten Stromreglerschaltung der liegt der Ausgang des Komparators 4 über einen Reihenwiderstand R2 an. Der Referenzeingang des zweiten Operationsverstärkers liegt auf Masse. Wann nun der Ausgang des Komparators ebenfalls auf Masse liegt, ist das Ausgangssignal des zweiten Operationsverstärkers auf Masse und der zweite Transistor 25 sperrt. Wenn dagegen bei einem nachhaltigen Ausfall des Taktes des Mikroprozessors, der Komparator 4 ein Stellsignal UvFehlerstrom ausgibt, dann gibt der zweite Operationsverstärker 26 eine Spannung aus, welche den Widerstand des zweiten Transistors 25 herabsetzt, so dass ein Strom über den zweiten Transistor fließt, welcher einen Gesamtspeisestrom von 22 mA bewirkt.Both current regulator circuits essentially each comprise a current regulating
Der Widerstand der Hauptelektronik, die durch den Speisestrom versorgt wird, und die hier nicht detailliert dargestellt ist, wird in dieser Darstellung durch den Widerstand 27 bzw. RHE zusammengefasst.The resistance of the main electronics, which is supplied by the supply current, and which is not shown here in detail, is summarized in this illustration by the
Die erste Stromreglerschaltung zur Regelung des Messsignalstroms ist prinzipiell ähnlich aufgebaut wie die zweite Stromreglerschaltung, wobei bei der dargestellten Ausführungsform der Messumformer einen ASIC 24 umfasst, und der Operationsverstärker 22 der ersten Stromreglerschaltung in den ASIC 24 integriert ist.The first current regulator circuit for controlling the measurement signal current is in principle similar to the second current regulator circuit, wherein in the illustrated embodiment, the transmitter comprises an
Claims (9)
- Measuring transducer, comprising: a microprocessor (1) with a reset input and a clock output for providing a periodic clock signal; a monitoring circuit (3) with a clock input and a reset output; and a current regulator (2) for outputting a measuring signal current, which measuring signal current represents a measured value in measuring operation in a first band range, and signals a fault outside the first band range, the clock input of the monitoring circuit being connected to the clock output of the microprocessor, and the reset input of the microprocessor being connected to the reset output of the monitoring circuit, and if the clock signal fails a reset signal is periodically output at the reset output of the monitoring circuit, characterised in that the measuring transducer further comprises a comparator circuit (4) which has a first input connected via a low-pass filter (5) to the reset output of the monitoring circuit (3), a second input to which a reference voltage is applied, and an output connected to an input of the current regulator, and after repeated outputting of the reset signal the voltage at the first input of the comparator circuit exceeds the reference voltage, so that a control signal is applied to the output of the comparator and causes the current regulator to output a fault signal current outside the first band range.
- Measuring transducer according to Claim 1, the low-pass filter comprising an RC element.
- Measuring transducer according to Claim 1 or 2, the comparator circuit comprising a first operational amplifier.
- Measuring transducer according to one of the preceding claims, the first band range being 4 to 20 mA.
- Measuring transducer according to Claim 4, the fault signal current being at least 21 mA.
- Measuring transducer according to one of the preceding claims, the monitoring circuit comprising a digital counter which counts from a starting value and causes a reset signal to be output if a limit value is over- or undershot, the counter being reset to its starting value both by each pulse of the clock signal of the microprocessor and by the reset signal of the monitoring circuit.
- Measuring transducer according to one of the preceding claims, the current regulator comprising two parallel current regulator circuits, of which the first current regulator circuit regulates a measuring signal current in the first band range and the second current regulator circuit regulates the fault signal current to a value outside the first band range.
- Measuring transducer according to Claim 7, the second current regulator circuit comprising a second operational amplifier, of which an input is connected to the output of the comparator, and its output is connected to the base of a transistor, via which the fault signal current is adjusted.
- Measuring transducer according to Claim 8, the voltage supply of the second operational amplifier for regulating the fault signal current being independent of the voltage supply of the current regulating circuit for regulating the measuring signal current.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102004019392A DE102004019392A1 (en) | 2004-04-19 | 2004-04-19 | Digital transmitter with current signal |
PCT/EP2005/051344 WO2005101345A1 (en) | 2004-04-19 | 2005-03-23 | Digital measuring transducer with current signal |
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EP1738337A1 EP1738337A1 (en) | 2007-01-03 |
EP1738337B1 true EP1738337B1 (en) | 2007-08-15 |
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EP05729510A Active EP1738337B1 (en) | 2004-04-19 | 2005-03-23 | Digital measuring transducer with current signal |
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US (1) | US7928742B2 (en) |
EP (1) | EP1738337B1 (en) |
CN (1) | CN100481147C (en) |
AT (1) | ATE370487T1 (en) |
DE (2) | DE102004019392A1 (en) |
WO (1) | WO2005101345A1 (en) |
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DE102008061006A1 (en) * | 2008-11-28 | 2010-06-02 | Esw Gmbh | Method and device for measuring electric current |
DE102011082018A1 (en) * | 2011-09-01 | 2013-03-07 | Siemens Aktiengesellschaft | Method for operating a field instrument for process instrumentation and field device |
DE102013107904A1 (en) * | 2013-07-24 | 2015-01-29 | Endress + Hauser Flowtec Ag | Measuring device with switchable measuring and operating electronics for the transmission of a measuring signal |
DE102015105090A1 (en) * | 2015-04-01 | 2016-10-06 | Krohne Messtechnik Gmbh | Method for operating a field device and corresponding field device |
CN109212307B (en) * | 2017-06-30 | 2020-12-18 | 致茂电子(苏州)有限公司 | Signal measurement device and signal measurement method |
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---|---|---|---|---|
JPS57123424A (en) | 1981-01-26 | 1982-07-31 | Toko Inc | Dc power supply device |
DE3322242A1 (en) | 1982-07-23 | 1984-01-26 | Robert Bosch Gmbh, 7000 Stuttgart | DEVICE FOR FUNCTION MONITORING OF ELECTRONIC DEVICES, IN PARTICULAR MICROPROCESSORS |
JPS6479841A (en) | 1987-09-22 | 1989-03-24 | Aisin Seiki | Abnormality monitoring device for microcomputer |
US4804958A (en) | 1987-10-09 | 1989-02-14 | Rosemount Inc. | Two-wire transmitter with threshold detection circuit |
FR2687810B1 (en) | 1992-02-21 | 1996-08-14 | Sextant Avionique | METHOD AND DEVICE FOR THE TEMPORAL MONITORING OF THE OPERATION OF A PROCESSOR. |
JPH06332755A (en) * | 1993-05-19 | 1994-12-02 | Mitsubishi Electric Corp | Watch dog timer circuit |
JP3633092B2 (en) * | 1996-03-18 | 2005-03-30 | 日産自動車株式会社 | Microcomputer failure monitoring device |
JP2000035903A (en) | 1998-07-16 | 2000-02-02 | Hitachi Ltd | Runaway monitoring device for microcomputer |
US6985581B1 (en) * | 1999-05-06 | 2006-01-10 | Intel Corporation | Method and apparatus to verify circuit operating conditions |
DE29917651U1 (en) * | 1999-10-07 | 2000-11-09 | Siemens AG, 80333 München | Transmitter and process control system |
DE10202028A1 (en) | 2002-01-18 | 2003-07-24 | Endress & Hauser Gmbh & Co Kg | Transmitter for detecting a physical measured variable and for converting it into an electrical variable uses signal processors to reshape the electrical variable into a test signal |
RU2331899C2 (en) | 2003-08-07 | 2008-08-20 | Роузмаунт Инк. | Processing unit with disabling circuit |
-
2004
- 2004-04-19 DE DE102004019392A patent/DE102004019392A1/en not_active Withdrawn
-
2005
- 2005-03-23 US US11/578,838 patent/US7928742B2/en active Active
- 2005-03-23 AT AT05729510T patent/ATE370487T1/en not_active IP Right Cessation
- 2005-03-23 EP EP05729510A patent/EP1738337B1/en active Active
- 2005-03-23 DE DE502005001258T patent/DE502005001258D1/en active Active
- 2005-03-23 WO PCT/EP2005/051344 patent/WO2005101345A1/en active IP Right Grant
- 2005-03-23 CN CNB2005800118534A patent/CN100481147C/en active Active
Also Published As
Publication number | Publication date |
---|---|
US7928742B2 (en) | 2011-04-19 |
DE502005001258D1 (en) | 2007-09-27 |
DE102004019392A1 (en) | 2005-12-08 |
EP1738337A1 (en) | 2007-01-03 |
CN100481147C (en) | 2009-04-22 |
ATE370487T1 (en) | 2007-09-15 |
WO2005101345A1 (en) | 2005-10-27 |
CN1942910A (en) | 2007-04-04 |
US20080030356A1 (en) | 2008-02-07 |
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