Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
  • G06F12/023—Free address space management
  • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
  • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Definitions

• the invention describes a method for managing memory blocks in a nonvolatile memory system with individually erasable memory blocks which can be addressed with real memory block numbers and which are addressable by an address conversion by means of allocator tables from a logical block number into respectively one of the real memory block numbers.
• Flash memory is used in many computer systems, especially in removable memory cards for digital cameras and portable computers. Flash memories are organized in blocks of memory with many sectors each. Essential features of these memories are that only a limited number of write and delete operations are possible and that deletion is possible only in memory blocks containing multiple sectors. The write and erase operations take much more time (up to a factor of 50) than reading.
• the conversion of logical memory addresses into real memory addresses is known in flash memory systems, for example from DE 102 27 256 for the uniform wear of real memory blocks or from DE 103 41 616, to manage defective real memory blocks. The memory systems are getting more and more memory capacity, so the memory block addresses are getting longer and the conversion tables from logical to real memory block addresses are getting bigger and bigger.
• Small memory block sizes about 4 Kbytes, are favorable in order not to make the loss of unused space in the memory blocks too large for file systems with many small files.
• larger memory blocks of 32 KB to 256 KB are now formed in order to keep the conversion tables correspondingly smaller. It is important to limit the address pointers in the tables to 16 bits in order to be able to carry out the address conversion quickly and efficiently. It is an object of the invention to efficiently manage storage systems of different sizes with uniform table structures with different real memory block sizes.
• This object is achieved by assigning the logical block number via a first table to a physical memory block number and assigning the physical memory block number to a real memory block number via a second table, one or more physical memory blocks being addressed with a physical memory block number.
• the second table allocates one or more physical memory blocks to a physical memory block number, the size of the real memory blocks being determined by the
• Structuring the memory chips used is given. For example, chips with block sizes of 4 Kbytes or with block sizes of 32 Kbytes, 64 Kbytes, 128 Kbytes or even larger real blocks are used.
• Size of the real memory blocks is performed.
• the method can thus be used in many different sized storage systems.
• the management of defective real memory blocks is performed only by means of the second address translation table, by replacing the numbers of defective memory blocks by the numbers of functional memory blocks in the second table.
• the numbers of defective memory blocks are then carried in unused areas of the second table.
• the formation of the physical memory blocks in the first address translation table has the advantage that large memory blocks are formed of multiple real memory blocks to which a memory operation is shared, no matter where the real memory blocks are located in the memory chips. This increases the speed of processing the memory operations. The speed of processing the memory operations is further increased when the real memory blocks reside in different memory chips. Then, the memory operations such as "write” or "erase” are performed in parallel in the memory chips (interleaving). In some types of memory chips, a large number of memory blocks are grouped in so-called banks, which are parallel
• Memory operations can perform. If the physical memory blocks each only consist of real memory blocks which are located in different banks and in different memory chips, the parallel processing of memory operations on all real memory blocks is carried out and a maximum processing speed is achieved.
• the address translation tables are kept in management-reserved non-volatile real memory blocks. They are thus available even after a power failure. For fast processing of the memory operations, copies of currently required parts of the address translation tables are additionally cached in an internal fast RAM memory.
• the numbers of the memory blocks reserved for the management of the memory system are not included in the first address translation table. They can not be addressed from outside via logical sector numbers. A small percentage of memory blocks, about 3%, are reserved for the replacement of memory blocks that have become corrupted. Also, the numbers of these real memory blocks are not included in the first address translation table. They can not be addressed from outside via logical sector numbers.
• Fig. 1 shows a block diagram of a memory system with 12 memory chips.
• Fig. 2 shows the structure of the two address conversion tables.
• Fig. 3 shows two examples of the translation of logical addresses into real addresses.
• FIG. 1 shows a block diagram for a memory system comprising twelve memory chips CO to CI 1 each having a memory capacity of 128 megabytes.
• the storage system thus has a size of 1.5 gigabytes.
• Memory operations such as "read” and “write” can be done with logical sectors of 512 bytes each - A -
• a physical memory block PB now comprises sixteen real memory blocks of the four chips of a superchip, each consisting of four independent banks with a total of 64 Kbytes.
• the physical block PB is formed in the superchip SCO with the chips CO to C3 each having one real memory block in each of the four by four banks BA0 to BA3. All physical memory blocks of the physical block PB can thus execute a memory operation in parallel.
• FIGS. 2A and 2B Two examples of address translations are given in FIGS. 2A and 2B.
• a memory operation is to be performed on the logical sector LSN numbered 127.
• the logical sector number is divided into the components sector number in a page PN, tuple index TI and logical block number LBN. Since sixteen blocks each having eight sectors are combined into one physical sector, a physical sector number between 0 and 127 results.
• the real sector numbers in a page are not necessarily continuous, but may have gaps depending on the size of the page.
• a page has four real sectors and two pages are combined into a real block. Since consecutive pages are arranged in consecutive banks, gaps in the numbering of the real sectors arise in a real block according to the number of banks and chips. In this
• Bit6 B6 is considered to be the uppermost bit of the real sector number.
• the physical sector number PSN becomes 127.
• the bit B6 is used as the fifth bit of the real sector number RSN.
• the real sector number RSN becomes 31.
• the logical sector number 1011769 is split.
• the physical sector number has the value 125.
• the bit B6 is used as the fifth bit of the real sector number RSN.
• the real sector number RSN becomes 25.
• FIG. 3 shows the structure of the two tables LTP and PTR.
• the logical block number LBN is translated into the address of a physical block consisting of the super chip number SCN and the physical block number PBN.
• the superchip number is thus 2 bits wide.
• a physical block number consists of thirteen bits and can therefore assume values from 0 to 8191. To accommodate 32 management blocks and 256 spare blocks each, the values are only up to 7903 and 7935, respectively.
• the logical block number LBN in this example is 16 bits wide and can take values between 0 and 24319, corresponding to the sum of the physical blocks of the three super chips SCO to SC2.
• the pointers from the first table LTP serve as an index in the second table PTR. They each point to a tuple of sixteen real blocks arranged in four by four banks BAO to BA3. A tuple is arranged in four chips of a superchip. This results in a table with 16 columns, in each of which the real block numbers of a bank are specified. Values between 0 and 7903 or 7935 can be specified as long as no substitute blocks have been entered. For example, e.g. in the second line at the last position a replacement block EB registered, which then has a larger block number.
• the block numbers can only have values modulo the bank number. Through administrative operations, however, the block numbers can be swapped arbitrarily within the banks.
• the rows of the table PTR that can not be addressed by a physical block number are unused, here each identified by a U.
• the real memory blocks to be addressed by the two examples from FIG. 2 are indicated by hatching in the table.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Techniques For Improving Reliability Of Storages (AREA)
• Memory System (AREA)
• Memory System Of A Hierarchy Structure (AREA)
• Read Only Memory (AREA)

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• 2005
  • 2005-01-07 DE DE102005001038A patent/DE102005001038B3/de not_active Expired - Fee Related
  • 2005-12-20 EP EP05850471A patent/EP1700220A1/de not_active Withdrawn
  • 2005-12-20 JP JP2007553484A patent/JP2008527581A/ja active Pending
  • 2005-12-20 CA CA002591957A patent/CA2591957A1/en not_active Abandoned
  • 2005-12-20 WO PCT/EP2005/056985 patent/WO2006072549A1/de active Application Filing
  • 2005-12-20 KR KR1020077013809A patent/KR20070092712A/ko not_active Application Discontinuation
  • 2005-12-20 CN CNA2005800461384A patent/CN101099136A/zh active Pending
  • 2005-12-20 US US11/813,548 patent/US20080201517A1/en not_active Abandoned
  • 2005-12-22 TW TW094145751A patent/TW200636465A/zh unknown

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