EP1700190B1 - Optimisation du delai de sortie a partir d'un etat actif de gestion de d'energie - Google Patents

Optimisation du delai de sortie a partir d'un etat actif de gestion de d'energie Download PDF

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Publication number
EP1700190B1
EP1700190B1 EP04815487.6A EP04815487A EP1700190B1 EP 1700190 B1 EP1700190 B1 EP 1700190B1 EP 04815487 A EP04815487 A EP 04815487A EP 1700190 B1 EP1700190 B1 EP 1700190B1
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EP
European Patent Office
Prior art keywords
interconnect
state
low power
activity
receiver
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Not-in-force
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EP04815487.6A
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German (de)
English (en)
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EP1700190A2 (fr
Inventor
David M. Puffer
Suneel G. Mitbander
Sarath K. Kotamreddy
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of power management within a computer system.
  • Power management has become and will continue to be an important factor in computer system component design.
  • One technique to reduce power consumption is to turn off input and/or output buffer circuits when an interconnect is idle for a period of time.
  • PCI Express PCI Express Base Specification, revision 1.0a.
  • the PCI Express specification defines an active power management state called "LOs." In this state, a device turns off its transmitters to save power whenever the transmitter is idle for up to 7us.
  • a transmitting device on one side of a PCI Express point-to-point link is required to communicate to the receiving device on the other side of the link that the transmitting device is entering the L0s state. This is accomplished by delivering a packet of information called an "electrical idle ordered set" to the receiving device. In response to receiving the electrical idle ordered set, the receiving device enters the L0s state and turns off its receiver circuit (including input buffers). When the transmitting device exits the L0s state and desires to recommence communication with the receiving device, the transmitting device begins by delivering a series of "fast training sets" (FTS).
  • An FTS includes special characters that are recognized by the receiving device and allow the receiving device to achieve bit and symbol synchronization following the period of no activity on the interconnect.
  • a typical FTS is 4 bytes in length.
  • the FTS series is received at the receiving device input circuitry, and after bit and symbol synchronization are achieved the FTS moves through the receiver pipeline circuitry until it is received by a power management unit that responds to the FTS by causing the receiving device to exit the L0s state.
  • a typical PCI Express device may have a pipeline delay of 20 or so symbol clock periods.
  • the number of FTS that must be transmitted by the transmitting device to the receiving device depends on the greatest length of time it may require for the receiving device to recognize activity on the interconnect, turn on the receiver circuit, achieve bit and symbol lock, and reset receiver pipeline logic.
  • the transmitting device and the receiving device first detect each other's presence, perhaps at system start-up, the receiving device must communicate to the transmitting device the minimum number of FTS that must be transmitted by the transmitting device to the receiving device when exiting the L0s state.
  • a problem may occur when the transmitting device enters L0s (sending an electrical idle ordered set to the receiving device) and quickly (in as little as 20ns) exits L0s (thereby beginning transmission of the FTS series).
  • the transmitting device would exit L0s and start transmitting FTS before the electrical idle ordered set has a chance to move through the receiving device pipeline and be recognized by the power management unit.
  • the power management unit will cause the receiving device to enter the L0s state (turning off the receiver circuitry) even though the transmitting device is already sending FTS.
  • the receiving device will exit L0s soon thereafter in response to the continued activity on the interconnect, but a number of FTS will have gone by without being recognized by the receiving device.
  • the transmitting device may begin to send higher-level packets before the receiving device is prepared to receive the packets, and the data will be lost.
  • the minimum number of FTS that must be transmitted from the transmitting device to the receiving device when the transmitting device exits the L0s state is inflated to cover the pipeline delay time, thereby ensuring that the receiving device will receive adequate time to enter and exit the L0s state and be prepared to receive higher-level packet data even in the case where the transmitting device enters and exits L0s quickly.
  • Low power states such as L0s are most useful when they can be entered and exited as quickly as possible. Low entry and exit latencies allow the low power states to be applied more liberally without adversely affecting interconnect performance.
  • United States patent 6021506 is a method and apparatus for stopping a bus clock when there are no activities present on a bus.
  • An AGP bus couples a graphics controller to core logic to transfer data between the two devices.
  • a controller generates a first (AGP bus) clock signal CLK and a second (internal) clock signal iclk for the first and second devices. If the controller determines that there are no graphics activities on the AGP bus (i.e., the bus is idle), the controller issues a stop request to stop the internal clock signal iclk. The processing of the stop request is delayed for a period of seven cycles on the AGP bus clock CLK to await for an objection from either the graphics controller or the core logic.
  • the internal clock iclk will not be stopped, and will continue to run. However, if an objection is not received, then the internal clock iclk will stop. If the graphics controller is in a low power or "sleep" state, the AGP bus clock CLK is stopped, thereby conserving power.
  • a transmitting device and a receiving device are coupled together via an interconnect.
  • An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline.
  • the power management unit checks for activity on the interconnect. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be turned off.
  • Figure 1 is a block diagram of one example embodiment of a computer system including a serial interconnect 145 coupling a serial interconnect controller 200 with an endpoint device 140.
  • the endpoint device 140 may be any of a wide range of devices, including a graphics controller, a network controller, etc.
  • the system of Figure 1 also includes a processor 110 coupled to a memory controller hub 120.
  • the memory controller hub 120 is further coupled to a system memory 130.
  • the memory controller hub 120 includes the serial interconnect controller 200.
  • the serial interconnect 145 is a PCI Express link, although other embodiments are possible using other interconnect types.
  • the serial interconnect 145 is a bi-directional link, although, for purposes of example, in this discussion the serial interconnect controller 200 will be discussed as being a receiving device and the endpoint device 140 will be described as being a transmitting device.
  • FIG. 2 is a block diagram of a portion of the serial interconnect controller 200. Again, this discussion will treat the serial interconnect controller 200 as a receiving device, although in practice the interconnect 145 is a bi-directional link.
  • the serial interconnect controller device 200 receives data over a differential pair of signals 145 (RX+ and RX-). The signals 145 are received at receiving circuitry 210.
  • the receiving circuitry 210 includes input buffers (not shown).
  • the controller 200 also includes receiver pipeline circuitry for processing the received signals, including a data extraction unit 220 and a packet processing unit 230.
  • the units 220 and 230 perform various functions including bit and symbol recovery, clock compensation, and packet processing.
  • the serial interconnect controller 200 also includes an electrical idle detect circuit 250. This circuit asserts a signal 251 when there is no activity on the signals 145.
  • the serial interconnect controller 200 further includes a power management unit 240 that receives input from the packet processing unit 230 and also receives signal 251 from the electrical idle detect circuit 250.
  • the power management unit 240 includes a state machine that is described below in connection with Figure 3 .
  • Figure 3 is a diagram of a state machine implemented in the power management unit 240.
  • State L0 310 represents a normal operating state where there is activity on the interconnect 145 and the receiver RX 210 is operating at full power.
  • an electrical idle ordered set works its way through the pipeline and is received at the power management unit 240, a check is made with regard to whether there is activity on the interconnect 145. This check is made by the electrical idle detect circuit 250.
  • the interconnect 145 is deemed to be at electrical idle if the differential signals 145 are at approximately a common mode voltage.
  • the state machine advances to state L0s entry 320.
  • the receiver circuit RX 210 is turned off in order to conserve power.
  • the state machine then advances to an L0s idle state 330.
  • the state machine remains in L0s idle state 330 until the electrical idle detect circuit 250 detects activity (electrical idle not detected) on the interconnect 145.
  • the state machine advances to state L0s Rx On 340.
  • the receiver circuitry 210 is turned on.
  • the process of turning on the receiver 210 may take a number of clock periods. In this example embodiment, the process of turning on the receiver takes 14 clock periods.
  • the state machine advances to an L0s Rx Reset state 350.
  • the symbol alignment and elastic buffer logic (not shown) in the data extraction unit 220 and the packet processing unit 230 are reset.
  • the state machine then advances to an L0s bit and symbol lock state 360 where the receiver locks on to the incoming bit stream and acquires symbol lock. If the receiving device 200 is unable to detect bit and symbol alignment within an appropriate period of time (during receipt of FTS sequence), then the state machine advances to a recovery state. Otherwise, the state machine re-enters the L0 state 310.
  • State 310 proceeds to state 320 if there is no activity on the interconnect when an electrical idle ordered set is received at the power management unit 240. However, if there is activity on the interconnect 145 (as determined by the electrical idle detect circuit 250) when the electrical idle ordered set is received at the power management unit 240, then the state machine transitions from the L0s state 310 to the L0s Rx Reset state 350. The state machine still enters L0s, but the steps of turning off and turning back on the receiver are avoided.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Communication Control (AREA)
  • Small-Scale Networks (AREA)

Claims (12)

  1. Procédé pour faire entrer, et sortir, un dispositif récepteur (200) d'un système informatique dans un mode d'économie d'énergie, comprenant les étapes consistant à :
    déterminer s'il existe une activité sur un interconnecteur (145) et faire entrer le dispositif récepteur (200) dans un mode d'économie d'énergie en réponse à la détermination d'une absence d'activité sur l'interconnecteur (145), caractérisé par les opérations consistant à :
    déterminer s'il existe une activité sur l'interconnecteur (145) en réponse à la réception d'un paquet d'informations au niveau d'une unité de gestion de la consommation d'énergie (240) dans le dispositif récepteur (200), le paquet d'informations indiquant au dispositif récepteur (200) qu'un dispositif transmetteur (140) couplé au dispositif récepteur (200) par le biais de l'interconnecteur (145) va entrer dans un mode d'économie d'énergie ;
    et
    passer outre l'entrée du dispositif récepteur (200) dans le mode d'économie d'énergie et entrer un état de restauration en réponse à la détermination d'activité sur l'interconnecteur (145).
  2. Procédé selon la revendication 1, dans lequel le mode d'économie d'énergie comprend un état d'entrée en économie d'énergie (320) comprenant la désactivation d'un circuit récepteur (210) dans le dispositif récepteur (200) ; et
    l'état de restauration comprenant un état de restauration d'économie d'énergie (350) comprenant la restauration de logique tampon dans le dispositif récepteur (200).
  3. Procédé selon la revendication 2, comprenant, en outre, l'entrée dans un état inactif d'économie d'énergie (330) postérieurement à l'état d'entrée en économie d'énergie (320).
  4. Procédé selon la revendication 3, comprenant, en outre, les étapes consistant à :
    détecter une activité sur l'interconnecteur (145) après l'entrée dans l'état inactif d'économie d'énergie (330) ; et
    quitter l'état inactif d'économie d'énergie (330) et entrer un état de MARCHE de récepteur d'économie d'énergie (340) en réponse à la détection d'activité sur l'interconnecteur (145) après l'entrée dans l'état inactif d'économie d'énergie (330).
  5. Procédé selon la revendication 4, comprenant, en outre, l'activation du circuit récepteur (210) pendant l'état de MARCHE de récepteur d'économie d'énergie (340).
  6. Procédé selon la revendication 5, comprenant, en outre, la sortie de l'état de MARCHE de récepteur d'économie d'énergie (340) et l'entrée d'un état de restauration de récepteur d'économie d'énergie une fois le circuit récepteur (210) activé pendant l'état de MARCHE de récepteur d'économie d'énergie (340).
  7. Dispositif récepteur d'un système informatique, comprenant :
    un circuit récepteur (210) pour connexion électrique à un interconnecteur (145) ;
    un pipeline pour traiter des signaux entrants reçus au niveau du circuit récepteur (210) ;
    une unité de gestion de la consommation d'énergie (240) ; et
    une unité de vérification d'activité (250) d'interconnecteur (145) couplée au circuit récepteur (210) pour déterminer s'il existe une activité sur l'interconnecteur (145) caractérisé par :
    l'unité de gestion de la consommation d'énergie (240) apte à recevoir un paquet d'informations destiné à être traité par le pipeline, le paquet d'informations indiquant qu'un dispositif transmetteur (140) couplé au circuit récepteur (210) par le biais de l'interconnecteur (145) va entrer dans un mode d'économie d'énergie,
    l'unité de vérification d'activité (250) d'interconnecteur (145) déterminant s'il existe une activité sur l'interconnecteur (145) en réponse à l'unité de gestion de la consommation d'énergie (240) recevant le paquet d'informations ; et
    l'unité de gestion de la consommation d'énergie (240) désactivant le circuit récepteur (210) en réponse à l'unité de vérification d'activité (250) d'interconnecteur (145) indiquant qu'il n'y a pas d'activité sur l'interconnecteur (145), et ne désactivant pas le circuit récepteur (210) en réponse à l'unité de vérification d'activité (250) d'interconnecteur (145) indiquant qu'il existe une activité sur l'interconnecteur (145).
  8. Dispositif récepteur selon la revendication 7, dans lequel le pipeline comprend une unité d'extraction de données (220) et une unité de traitement de paquet (230).
  9. Dispositif récepteur selon la revendication 8, le circuit récepteur (210) comprenant une paire d'entrées destinées à recevoir une paire de signaux différentiels, les signaux différentiels inclus en tant que partie de l'interconnecteur (145).
  10. Dispositif récepteur selon la revendication 9, l'unité de vérification d'activité (250) d'interconnecteur (145) indiquant qu'il n'y a pas d'activité sur l'interconnecteur (145) si la paire de signaux différentiels est sensiblement à une tension de mode commun.
  11. Dispositif récepteur selon la revendication 10, le circuit récepteur (210) permettant une connexion électrique à un PCI Express interconnecteur (145).
  12. Système informatique, comprenant :
    un dispositif transmetteur (140) ; et
    un dispositif récepteur (200) couplé au dispositif transmetteur (140) par le biais d'un interconnecteur (145), le dispositif récepteur (200) étant tel que revendiqué dans l'une quelconque des revendications 7 à 11.
EP04815487.6A 2003-12-30 2004-12-23 Optimisation du delai de sortie a partir d'un etat actif de gestion de d'energie Not-in-force EP1700190B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/749,619 US7178045B2 (en) 2003-12-30 2003-12-30 Optimizing exit latency from an active power management state
PCT/US2004/043418 WO2005066765A2 (fr) 2003-12-30 2004-12-23 Optimisation du delai de sortie a partir d'un etat actif de gestion de d'energie

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EP1700190A2 EP1700190A2 (fr) 2006-09-13
EP1700190B1 true EP1700190B1 (fr) 2014-03-05

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US (1) US7178045B2 (fr)
EP (1) EP1700190B1 (fr)
KR (2) KR100898645B1 (fr)
CN (1) CN100483304C (fr)
TW (1) TWI280474B (fr)
WO (1) WO2005066765A2 (fr)

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WO2005066765A2 (fr) 2005-07-21
CN100483304C (zh) 2009-04-29
WO2005066765A3 (fr) 2005-09-15
KR101129748B1 (ko) 2012-04-13
TW200532428A (en) 2005-10-01
US7178045B2 (en) 2007-02-13
EP1700190A2 (fr) 2006-09-13
KR20090017643A (ko) 2009-02-18
CN1902567A (zh) 2007-01-24
US20050144487A1 (en) 2005-06-30
TWI280474B (en) 2007-05-01
KR100898645B1 (ko) 2009-05-22
KR20060127110A (ko) 2006-12-11

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