EP1700178A1

EP1700178A1 - Voltage regulation system

Info

Publication number: EP1700178A1
Application number: EP04820845A
Authority: EP
Inventors: Martin Brox
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2003-12-30
Filing date: 2004-11-23
Publication date: 2006-09-13
Anticipated expiration: 2024-11-23
Also published as: DE10361724A1; WO2005064426A1; DE502004008797D1; US7965066B2; EP1700178B1; CN1902558A; US20080191790A1; JP2007517298A

Abstract

The invention relates to a voltage regulation method and a voltage regulation system (11), by means of which a first voltage (VDD), applied to an input of the voltage regulation system (11), is converted into a second voltage (VINT), which is provided at an output (19c) of the voltage regulation system (11), with a first device (12), for the generation of an essentially constant voltage (VBGR) from the first voltage (VDD), or a voltage derived therefrom, whereby an additional device (34) is provided for the generation of a further voltage (VTRACK) from the first voltage (VDD), or a voltage derived therefrom, in particular a voltage (VTRACK), which can be greater than the voltage (VBGR), generated by the first device (12).

Description

description

Voltage regulation system

The invention relates to a voltage control system according to

Preamble of claim 1, and a voltage control method.

In the case of semiconductor components, in particular in the case of memory components such as e.g. DRAMs (DRAM = Dynamic Random Access Memory or dynamic random access memory), a voltage level VINT used internally in the component can differ from a voltage level used outside the component, e.g. distinguish from an external voltage supply for the semiconductor component provided voltage level (supply voltage level) VDD.

In particular, the internally used voltage level VINT can be lower than the level VDD of the supply voltage - for example the internally used voltage level VINT can be 1.5 V, and the supply voltage level VDD e.g. between 1.5 V and 2.5 V, etc.

An internal voltage level VINT which is lower than the supply voltage level VDD has the advantage that the power losses in the semiconductor component can be reduced as a result.

Furthermore, the voltage level VDD of the external voltage supply can be subject to relatively large fluctuations.

Therefore, the supply voltage is usually - so that the component can be operated as error-free as possible or in the most reliable way possible - by means of a voltage regulator into a (only relatively low

Fluctuations, to a certain, constant, reduced value regulated) internal voltage VINT converted.

Conventional voltage regulators (e.g. corresponding down-converter regulators) can e.g. have a differential amplifier and a p-field effect transistor. The gate of the field effect transistor can be connected to an output of the differential amplifier, and the source of the field effect transistor e.g. to the external power supply.

A reference voltage VREF, which is subject to only relatively slight fluctuations, is applied to the plus or minus input of the differential amplifier. The voltage output at the drain of the field effect transistor can be direct, or e.g. can be fed back to the minus input of the differential amplifier with the interposition of a voltage divider.

The differential amplifier regulates the voltage present at the gate connection of the field effect transistor so that the (feedback) drain voltage - and thus the voltage output by the voltage regulator - is constant and of the same size as the reference voltage, or e.g. larger by a certain factor.

To generate the above Reference voltage VREF can e.g. a corresponding conventional reference voltage generator, e.g. a band-gap reference voltage generating device can be used, which is derived from the above - the above relatively high supply voltage level VDD - supply voltage (which may be subject to relatively large voltage fluctuations) - e.g. by means of one or more diodes - generates a signal having a constant voltage level VBGR.

The signal having the constant voltage level VBGR can be forwarded to a buffer circuit, there stored accordingly (and temporarily) and - in the form of corresponding signals having the above-mentioned reference voltage level VREF - further distributed (for example to the above-mentioned voltage regulator (or to the plus or minus input of the corresponding voltage regulator differential amplifier), and / or to further devices provided on the semiconductor component, for example further voltage regulators).

The object of the invention is to provide a new type of voltage control system and a new type of voltage control method.

It achieves this and other goals through the subject matter of claims 1 and 9.

Advantageous developments of the invention are specified in the subclaims.

According to one aspect of the invention, a voltage control system is provided ^'with which a voltage applied to an input of the voltage regulation system first voltage is converted into a second voltage which can be tapped at an output of the voltage regulation system, comprising first means for generating a substantially constant voltage from the first voltage, or a voltage derived therefrom, wherein a further device is additionally provided for generating a further voltage from the first voltage, or a voltage derived therefrom, in particular a voltage which can be greater than that of the first Device generated voltage.

The voltage generated by the first device, or a voltage obtained therefrom, and the further voltage generated by the further device, or a voltage obtained therefrom, can be used particularly advantageously to control a voltage regulation circuit arrangement. in particular as a reference voltage for a voltage control circuit arrangement which generates the above-mentioned second voltage.

A device is preferably additionally provided for activating and / or deactivating the further device.

If - in certain situations - the performance, in particular the switching speed, of devices connected to the (second) voltage is to be increased, the further device can be activated (and thereby achieved that the voltage control system outputs a higher (second) voltage than if the other device is deactivated).

The invention is explained in more detail below with the aid of several exemplary embodiments and the accompanying drawing. In the drawing "shows:

Figure 1 is a schematic representation of a conventional voltage control system;

Figure 2 is a schematic representation of a voltage control system according to an embodiment of the invention;

FIG. 3 shows a schematic detailed illustration of a buffer circuit that can be used in the voltage control system shown in FIG. 2;

FIG. 4 shows a schematic detailed illustration of a voltage regulator that can be used in the voltage regulating system shown in FIG. 2;

Figure 5 is a schematic representation of the level of the output voltage of that shown in Figure 2 Voltage control system, depending on the level of the supply voltage, in the activated and in the non-activated state of the additional buffer circuit; and

FIG. 6 shows a schematic detailed illustration of a further, additional buffer circuit that can be used in the voltage control system shown in FIG. 2;

FIG. 1 shows a schematic representation of a voltage control system 1 according to the prior art, which is arranged on a corresponding semiconductor component.

This has a reference voltage generating device 2 (e.g. a band-gap reference voltage generating device), a buffer circuit 3, and one or more voltage regulators 4 (e.g. corresponding down-converter regulators).

As can be seen from Figure 1, the reference voltage

Generation device 2 - z. B. A supply voltage provided by an external voltage supply for the semiconductor component is supplied via corresponding lines 5, 6, 7.

The supply voltage has a voltage level VDD, which is relatively high and possibly subject to relatively strong fluctuations.

The reference voltage generating device 2 generates from the supply voltage - e.g. by means of one or more diodes - a signal having a constant voltage level VBGR.

The signal having the constant voltage level VBGR is - via a corresponding line 8 - passed on to the above-mentioned buffer circuit 3, there accordingly (temporarily) stored, and - in the form of corresponding signals, which also have a constant voltage level VREF - further distributed (for example - via a line 9a - to the above-mentioned voltage regulator 4, and / or to other devices provided on the semiconductor component, for example further voltage regulators, etc.).

The voltage regulator 4 can e.g. a differential amplifier and a p-field effect transistor. The gate of the field effect transistor can be connected to an output of the

Differential amplifier can be connected, and the source of the field effect transistor - via a line 9b - to the above. external power supply (voltage level VDD).

At the plus or minus input of the differential amplifier - as a “reference voltage” - the voltage VREF, which is passed on to the voltage regulator 4 via the above-mentioned line 9a, can be applied (or only subjected to relatively small fluctuations).

The voltage output at the drain of the field effect transistor can be direct, or e.g. with the interposition of a voltage divider to the minus input of the differential amplifier.

The differential amplifier regulates the voltage present at the gate connection of the field effect transistor in such a way that the (feedback) drain voltage - and thus that of the voltage regulator 4 e.g. voltage VINT - output on a corresponding line 9c - is constant and of the same size as the reference voltage VREF, or e.g. larger by a certain factor.

With the help of the above Voltage control system 1 can thus from the above. external, relatively high, and relatively strong

Fluctuated voltage VDD a relatively small fluctuations, to a certain constant, reduced value regulated voltage VINT are generated, with the aid of which appropriate devices provided on the semiconductor component can be operated - reliably and with only a relatively low power loss.

FIG. 2 shows a schematic illustration of a voltage control system 11, which is arranged on a corresponding semiconductor component, in accordance with an exemplary embodiment of the invention.

The semiconductor component can e.g. are a corresponding, integrated (analog or digital) computing circuit, and / or a semiconductor memory component such as e.g. a function memory component (PLA, PAL, etc.) or table memory component (e.g. ROM or RAM), in particular an SRAM or DRAM.

The voltage control system 11 has a reference voltage generator 12 (e.g., a band-gap reference voltage generator), one

Buffer circuit 13, and one or more voltage regulators 14 (e.g. corresponding down-converter regulators).

As can be seen from Figure 2, the reference voltage generating device 12 - e.g. A supply voltage provided by an external voltage supply for the semiconductor component is supplied via corresponding lines 15a, 15b, 16a, 17.

The supply voltage has a - relatively high, and possibly relatively strong fluctuations - voltage level VDD. For example, the level of the supply voltage can be between 1.5 V and 2.5 V, for example between 1.6 V and 2.0 V (1.8 V + 0.2 V).

The reference voltage generating device 12 generates from the supply voltage - e.g. by means of one or more diodes

- A signal having a constant voltage level VBGR.

The signal having the constant voltage level VBGR is - via a corresponding line 18 - to the above. Buffer circuit 13 forwarded, there (appropriately) stored, and - in the form of corresponding signals which also have a constant voltage level VREF1 - distributed (for example - via a line 19a - to the above-mentioned voltage regulator 14, and / or - for example via corresponding further, Lines not shown here - to further devices provided on the semiconductor component (for example further voltage regulators, etc.).

FIG. 3 shows a schematic detailed illustration of a buffer circuit 13 that can be used in the voltage control system 11 shown in FIG.

The buffer circuit 13 has a differential amplifier 20 with a plus input 21a and a minus input 21b, and a field effect transistor 22 (here: a p-channel MOSFET).

An output of the differential amplifier 20 is connected via a line 23 to a gate connection of the field effect transistor 22.

As further shown in FIG. 3, the source of the field effect transistor 22 is connected via a line lb (which - according to FIG. 2 - is connected to the above lines 16a, 17) to the one having the above-mentioned, relatively high voltage level VDD

- Supply voltage connected. As can be seen from FIG. 3, the above-mentioned signal, which is supplied via line 18 from the reference voltage generator 12 and has the above-mentioned, relatively constant voltage level VBGR, is present at the minus input 21b of the differential amplifier 20.

The signal which is output at the drain of the field effect transistor 22 and has the above-mentioned, relatively constant voltage level VREF1 is fed back via a line 24 and a line 25 connected thereto to the plus input 21a of the differential amplifier 20, and - via the line 24 Line 19a - to the above Distributed voltage regulator 14 (and / or - e.g. via corresponding further lines, not shown here - to the above-mentioned further voltage regulators, etc.).

FIG. 4 shows a schematic detailed illustration of a voltage regulator 14 which can be used in the voltage regulating system 11 shown in FIG.

The voltage regulator 14 has a differential amplifier 28 with a plus input 32 and a minus input 31, and a field effect transistor 29 (here: a p-channel MOSFET) ^' .

An output of the differential amplifier 28 is connected via a line 29a to a gate terminal of the field effect transistor 29.

As further shown in Figure 4, the source of the

Field effect transistor 29 via a line 19b (and - according

Figure 2 - the line 17) connected to the supply voltage having the above-mentioned, relatively high voltage level VDD.

At the plus input 32 of the differential amplifier 4 is - as will be explained in more detail below - on the line 19a, and a line 27 connected to this from the buffer circuit 13 and having the above-mentioned, relatively constant voltage level VREF1 (reference) signal, and optionally also a further buffer circuit 33 provided in parallel with the above-mentioned buffer circuit 13 (Further) (reference) signal (which - as will be explained in greater detail below - has a relatively high voltage level VREF2 which is subject to variable or possibly corresponding fluctuations, and which has a line 26 and the line 27 connected to it is forwarded from the further buffer circuit 33 to the voltage regulator 14).

The output at the drain of the field effect transistor 29

Voltage (VINT) is fed back directly to the differential amplifier 28 in a first embodiment of the voltage regulator 14; For this purpose, the drain of the field-effect transistor 29 can be (directly) connected via a line 19c (and a line connected to it, not shown here) to the minus input 31 of the differential amplifier 28 (the feedback present at the minus input 31 of the differential amplifier 28) The voltage (VINT_FB) is then the same as the drain voltage (VINT)).

In a second, alternative embodiment, on the other hand, the voltage (VINT) output at the drain of the field effect transistor 29 is interposed with the interposition of a voltage divider (not shown here), i.e. fed back to the differential amplifier 28 in a divided manner. The drain of the

Field effect transistor 29 can be connected via line 19c (and a line connected to it, not shown here) to a first resistor R ₂ (not shown) of the voltage divider, which on the one hand (via a further voltage divider resistor Rα (also not shown)) with the earth, and on the other hand with the minus Input 31 of differential amplifier 28 is connected ("the feedback voltage present at negative input 31 of differential amplifier 28 (VINT_FB) is then a certain factor smaller than the drain voltage (VINT)).

The differential amplifier 28 controls the above. First embodiment of the voltage regulator 14 (with direct feedback of the drain voltage (VINT)) the voltage present at the gate connection of the field effect transistor 29 such that the (feedback) drain voltage (VINT) is the same as that at the plus input 32 of the differential amplifier 28 applied reference voltage (ie VREFl (if VREFl is larger than VREF2), or VREF2 (if VREF2 is larger than VREFl) (see below)).

In contrast, in the second, alternative embodiment of the voltage regulator 14 explained above - in which the drain voltage (VINT) is not direct, but by means of the above-mentioned. Voltage divider is fed back - that applied to the gate terminal of the field effect transistor 29

Voltage regulated by differential amplifier 28 such that:

VINT = VREF x (1+ (R ₂ / Rι))

(Relatively more precisely, and as will be explained in more detail below: VINT = VREFl x (1+ (R ₂ / Rι)), if applies: VREFl> VREF2, or VINT = VREF2 x (1+ (R ₂ / Rι) ) if applies: VREF2> VREFl)

The at the drain of the field effect transistor 29 (i.e. from

Voltage regulator 14) voltage output on line 19c

(VINT) represents the output voltage of the voltage control system 11.

Through the above Regulation is achieved that the

Output voltage (VINT) of the voltage control system 1 - as illustrated for example in FIG. 5 - in contrast to that Supply voltage (VDD), which can be subject to relatively large fluctuations - has a constant variable VINTnom - for example 1.5 V (but only if - as will be explained in more detail below - the (further) buffer circuit 33 is not activated ( partially shown in dashed lines in FIG. 5), or if - with activated buffer circuit 33 - the supply voltage (VDD) is smaller than a predetermined threshold value (VDDnom) (as will also be explained in more detail below)).

The output voltage VINT present on the line 19c can - if necessary via further lines, not shown here - be passed on as “internal supply voltage” to corresponding devices provided on the semiconductor component (which thus - in the case of a constant voltage value VINTnom mentioned above having output voltage VINT - with very high reliability, and with only relatively low power loss, and relatively long life can be operated).

If - in certain situations - the performance, in particular the switching speed of the devices connected to the output voltage VINT (via line 19c, for example) is to be increased, although this may increase the reliability and / or the service life of the device connected to the

Output voltage VINT operated devices, and / or their power loss is increased - the level of the output voltage VINT present on line 19c, i.e. the level of the internal supply voltage above the above - the value ("nominal value" VINTnom) provided in normal operation and specified in the respective specification may be increased.

This (further, second) operating mode (“power mode”) can be used, for example, if the semiconductor component is to be used in high-end graphics systems, for example as a high-end graphics memory component, for example as Memory component, in particular DRAM memory component for a high-clocked, in particular overclocked processor, in particular graphics processor.

To the above To enable "power operation", the voltage control system 11 provides - in addition to the above-mentioned reference voltage generating device 12 and the buffer circuit 13 - the above-mentioned further buffer circuit 33, and - as will be explained in more detail below - a (further) reference voltage Generating device 34 (for example a voltage tracking reference voltage generating device), and an (additional) register 35.

Immediately after the start-up (or switching on / starting up) of the voltage control system 11 (“power-up”), or after the — for the first time — supply of the above-mentioned external supply voltage to the line 17 (which, as explained, the above, possibly . Varying voltage level VDD), the voltage control system 11 is initially operated in the above-mentioned “normal operation”.

In "normal operation", the above-mentioned further buffer circuit 33 is deactivated.

For this purpose, at a corresponding exit of the above

Register 35 a corresponding (e.g. "logic low")

Output signal VTRACK_ENABLE is output and - via a corresponding control line 36 - forwarded to a corresponding control connection of the buffer circuit 33 (cf. also FIG. 6).

The output of a corresponding (for example “logically low”) output signal at the above-mentioned register output when the voltage control system 11 is switched on / started up (“power-up”) (which leads to a — initially — deactivated state of the buffer circuit 33) can be ensured in this way, for example that at Switching on / starting up the voltage control system 11 the register is reset accordingly by applying a corresponding reset signal to a line 37 connected to the reset input of the register 36.

Should - as can be determined individually by the respective user of the semiconductor component - during operation of the semiconductor component from the above. "Normal operation" in the above "power operation" (and - if necessary several times - back to "normal operation"), an external control device connected to the semiconductor component by means of appropriate external lines sends a corresponding control signal to one of the Control input of the register 35 connected line 38 applied (for example a "logically high" control signal for changing to the

"Power operation", and a "logically low" control signal (normal operation activation signal) for the (return) change to "normal operation").

On the next positive (or negative) edge of a clock signal - supplied to the clock input of register 35 via a clock line 39 (provided by the above (system) control device, for example) - the output signal output at the register output (ie the signal VTRACKJENABLE then takes on the control line 36) to the state of the control signal present at the control input of the register 35 (ie on the line 38), as a result of which the buffer circuit 33 is either activated accordingly ("logically high" state of the VTRACKJENABLE signal), or - again - deactivated ("logically lower "state of the signal VTRACK_ENABLE).

FIG. 6 shows a schematic detailed illustration of a buffer circuit which can be used as a further, additional buffer circuit 33 in the voltage control system 11 (which, as explained, is connected to the register 35 via the line 36). The buffer circuit 33 has a differential amplifier 120 with a plus input 121a and a minus input 121b, and a field effect transistor 122 (here: a p-channel MOSFET).

An output of the differential amplifier 120 is connected via a line 123 to a gate connection of the field effect transistor 122.

As further shown in Figure 6, the source of the

Field effect transistor 122 is connected via a line 116b (which - according to FIG. 2 - via a line 116c and a line 115a to the above-mentioned lines 15a, 16a, 17) to the supply voltage having the above-mentioned, relatively high voltage level VDD.

As can be seen from FIGS. 2 and 6, there is at the minus input 121b of the differential amplifier 120 a voltage level VTRACK which is supplied via a line 118 from the reference voltage generating device 34 and which (as will be explained in more detail below) has a variable or corresponding fluctuations Signal on.

The output at the drain of the field effect transistor 122, the above. - possibly variable - signal having a voltage level VREF2 is fed back via a line 124 and a line 125 connected thereto to the plus input 121a of the differential amplifier 120 and output on the line 26 connected to line 124.

With the aid of the - further - buffer circuit 33, when the buffer circuit 33 is in an “activated” state (ie with a “logically high” signal VTRACK_ENABLE present on the control line 36), the above-mentioned one, which has a variable voltage level VTRACK, and via the line 118 forwarded by the reference voltage generating device 34 to the buffer circuit 33 - signal (between ) saved, and - in the form of corresponding signals having a voltage level VREF2 corresponding to the voltage level VREF2, which can be picked up on the line 26 - passed on to the above-mentioned voltage regulator 14 (and / or - for example via corresponding further lines, not shown here - to the above-mentioned further ones Voltage regulator, etc.).

In contrast, in the "deactivated" state of the buffer circuit 33 - i.e. with a "logically low" signal VTRACK_ENABLE present on the control line 36 - its output (i.e. the drain of the field effect transistor 122, and thus the line 26) is in a high-resistance state.

As can be seen from FIG. 2, the reference voltage generator 34 (“tracking reference voltage generator”) - via a line 115b, and the lines 115a, 15a, 16a, 17 connected to it - are at the above-mentioned, the relatively high voltage levels VDD - supply voltage connected.

The (further) reference voltage generating device 34 uses the supply voltage having the voltage level VDD to generate a voltage - which is forwarded via line 118 to the buffer circuit 33 - with a level VTRACK which can be higher than the level VBGR of that of the (first) reference voltage - Generation device 12 generates voltage VBGR (which means that the level VREF2 of the voltage forwarded from the (further) buffer circuit 33 via line 26 to the voltage regulator 14 can be higher than the level VREFl of the (first) buffer circuit 13 via the line 19a to the voltage regulator 14 forwarded voltage).

For example, the (further) reference voltage generating device 34 can generate a voltage, which is passed on to the buffer circuit 33 via the line 118, from the supply voltage having the voltage level VDD which has a voltage level VTRACK which is proportional to the voltage level VDD of the supply voltage.

The level VTRACK is advantageous (or in an alternative embodiment) that of the (further)

Reference voltage generating device 34 generated voltage substantially the same size or only slightly less than the level VDD of the supply voltage (for example, VTRACK = 0.5 ... 0.95 x VDD, in particular 0.7 ... 0.9 x VDD, etc.).

For example, the (further) reference voltage generating device 34 can be designed in the form of a voltage divider circuit (having a plurality of resistors connected in series (for example a first resistor can be connected to the supply voltage via line 115b, and a second resistor in series with the first Resistance to the earth potential, the voltage output by the (further) reference voltage generating device 34 being tapped between the two resistors and being able to be passed on to the buffer circuit 33 via the line 118).

The (further) reference voltage generating device 34 (and the - first - reference voltage generating device 12) is (or are) designed such that when the supply voltage (VDD) is the same as the above-mentioned predetermined threshold value (VDDnom), the level VTRACK of the voltage generated by the (further) reference voltage generating device 34 is the same as the level VBGR of the voltage generated by the (first) reference voltage generating device 12 (cf. also FIG. 5) - the level VREF1 of the voltage by the buffer circuit 13 generated voltage is then identical to the level VREF2 of the voltage generated by the buffer circuit 33). In the deactivated state of the (further) buffer circuit 33 (due to the then high-impedance state of the output of the buffer circuit 33, ie the signal VREF2 present on line 26), the state of the signal input on line 27 into voltage regulator 14 becomes (and thus also the state of the signal VINT output by the voltage regulator 14 on the line 19c) is determined exclusively by the signal VREF1 which is present on the line 19a connected to the line 27 and which is output by the (first) buffer circuit 33 (as shown in FIG. 5 - partly with a broken line) is then the level of the signal VINT output by the voltage regulator 14 - corresponding to the level of the signal VREFl - regardless of the current level of the level VDD of the supply voltage is constantly the same size (VINTnom)).

In contrast, when the (further) buffer circuit 33 is activated (due to the parallel connection of the two buffer circuits 13 and 33), the state of the signal input to the voltage regulator 14 on the line 27 (and thus also the state of the voltage regulator 14 on the line)

19c output signal VINT) is determined in each case by that of the signals VREF1, VREF2 present on the lines 19a, 26, which are connected to one another and connected to the line 27 and which, at the moment, has a higher level (this ensures that - as in FIG. 5 is illustrated with the aid of the solid line - the level of the signal VINT output by the voltage regulator 14 cannot drop below the standard or nominal level (VINTnom).

Claims

claims

1. Voltage control system (11) with which a first voltage (VDD) present at an input (17) of the voltage control system (11) is converted into a second voltage (VINT), which is tapped at an output (19c) of the voltage control system (11) can be characterized by a first device (12, 13) for generating a substantially constant voltage (VBGR) from the first voltage (VDD), or a voltage derived therefrom, in that a further device (34, 33) is provided for Generating a further voltage (VTRACK) from the first voltage (VDD), or a voltage derived therefrom.

2. Voltage control system (11) according to claim 1, wherein the further voltage (VTRACK) generated by the further device (34, 33) can be greater than the voltage (VBGR) generated by the first device (12).

3. Voltage control system (11) according to claim 1 or 2, wherein the further voltage (VTRACK) generated by the further device (34, 33) is proportional to the first voltage

(VDD), or the voltage derived from it.

4. Voltage control system (11) according to claim 3, wherein the further device (34, 33) has a voltage divider circuit.

5. Voltage control system (11) according to one of the preceding claims, in which the voltage generated by the first device (12) (VBGR), or a voltage obtained therefrom (VREFl), and the further voltage (34) generated by the further device ( VTRACK), or a voltage (VREF2) obtained therefrom can be used to drive a voltage regulation circuit arrangement (14), in particular as a reference voltage (VREFl, VREF2) for the voltage control circuit arrangement (14).

6. Voltage control system (11) according to one of the preceding claims, in which a device (35) is additionally provided for activating and / or deactivating the further device (34, 33).

7. Voltage control system (11) according to claim 6, in which - in the activated state of the further device (34, 33) - the level of the reference voltage (VREF1, VREF2) used for the voltage control circuit arrangement (14) from that of voltages (VBGR, VTRACK) generated by the first and the further device (12, 34), or the voltages (VREF1, VREF2) obtained therefrom, which has a higher level.

8. Voltage control system (11) according to claim 6 or 7, in which - in the deactivated state of the further device (34, 33) - the level of the reference voltage (VREF1, VREF2) used for the voltage control circuit arrangement (14) the voltage (VBGR) generated by the first device (12), or the voltage obtained therefrom (VREFl) is determined.

9. Voltage control method, wherein a first voltage (VDD) is converted into a second voltage (VINT), in particular into a second voltage (VINT), which has a lower voltage level than the first voltage (VDD), the method having the step : Generating a substantially constant voltage (VBGR) from the first voltage (VDD), or a voltage derived therefrom, characterized in that the method further comprises the step: generating a further voltage (VTRACK) from the first voltage (VDD), or one voltage derived therefrom, in particular a further voltage (VTRACK), which can be greater than that from the first voltage (VDD), or the voltage derived therefrom, constant voltage (VBGR).