EP1668683A1 - Procede de formation de couches dielectriques a faibles constantes dielectriques - Google Patents

Procede de formation de couches dielectriques a faibles constantes dielectriques

Info

Publication number
EP1668683A1
EP1668683A1 EP04770031A EP04770031A EP1668683A1 EP 1668683 A1 EP1668683 A1 EP 1668683A1 EP 04770031 A EP04770031 A EP 04770031A EP 04770031 A EP04770031 A EP 04770031A EP 1668683 A1 EP1668683 A1 EP 1668683A1
Authority
EP
European Patent Office
Prior art keywords
layer
recited
wafer
dielectric
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04770031A
Other languages
German (de)
English (en)
Inventor
Harbans Sachdev
Garkay Leung
John Rapp
Mary Matera-Longo
Nara Sarma
Stephen Meisner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP1668683A1 publication Critical patent/EP1668683A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02307—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a liquid

Definitions

  • ILD's inter- level and intra-level dielectrics
  • porous Si0 2 formed from hydrosilsesquioxane (HSQ), which is a flowable oxide that may be deposited by spin-on coating techniques. After the spin-on process is complete, the material is baked, and the solvent is removed, leaving silicon dioxide (glass), which is porous.
  • the dielectric constant of the porous oxide layer is illustratively on the order of approximately 2.0 to approximately 3.8, and certainly less than 3.9. As can be appreciated, the greater the degree of porosity, the lower the dielectric constant.
  • the referenced dielectric materials deposited by spin-coating are often referred to as spin-on-glass (SOG) materials. While these materials have shown promise in providing low-k ILD's, their deposition can be exceedingly costly.
  • a method of depositing a dielectric material includes providing a substrate with at least one layer over the substrate. The method further includes pre-wetting a top surface of a top layer with a substance, spin coating the solution and forming the dielectric material.
  • a semiconductor structure includes a layer of porous low-k dielectric material disposed over a substrate, wherein the material has a thickness across the layer, and the thickness has a uniformity across a surface with a standard deviation of +0.728%.
  • Fig. 1 is a flow-chart of a process 100 of forming a low-k dielectric layer over a semiconductor wafer in accordance with an example embodiment.
  • the wafer includes a semiconductor substrate, and at least one other layer formed thereover.
  • the layer or layers over the substrate may be the usual layers in an IC, including but not limited to doped and undoped semiconductor layers, dielectric layers metal layers, including patterned metal layers, and other layers within the purview of one of ordinary skill in the art in the semiconductor processing art.
  • a wafer is provided.
  • a solvent is dispensed over the uppermost surface of the wafer.
  • the solvent is chosen to provide an adequate cleaning of the top surface of the wafer. Characteristically, the solvent significantly reduces if not substantially eliminates the surface tension at the surface of the wafer. As described more fully below, the surface tension retards the adhering of the slurry of the SOG to the wafer, thereby impeding the deposition of the slurry.
  • the slurry is a solution of hydrosilsequioxane polymer (HSQ) in a solution of hexamethyldisiloxane (Siloxane).
  • HSQ hydrosilsequioxane polymer
  • Siloxane hexamethyldisiloxane
  • the solution is illustratively 80% Siloxane / 20% HSQ by volume.
  • the solvent used as the pre- wet is beneficially Siloxane as well.
  • approximately 3.0 ml to approximately 5.0 ml of the Siloxane is dispensed onto the wafer as it is rotated at approximately 75 rpm for approximately 2.5 seconds.
  • the wafer is spun at a rate of approximately 1000 rpm for approximately 4.0 seconds to spread the solvent more evenly across the entire wafer surface.
  • the HSG/Siloxane solution is dispensed onto the wafer by known spin- on techniques.
  • the SOG spread step is advantageously increased from approximately 70 rpm to approximately 75 rpm, and the rotation time is changed from 1.5 to 2.0 sec.
  • a 'high-speed' rotation step follows the initial slurry deposition step.
  • the rotation rate of the wafer in the 'high speed' is adjusted for optimum thickness, depending on the desired thickness of the applied SOG film. For example, for an SOG layer having a mean thickness of 4500 Angstroms the rotation rate of the wafer in high-speed step is approximately 4000 rpm. For a layer with a mean thickness of 2000 Angstroms, the rotation rate is approximately 2000 rpm.
  • Fig. 2a shows a wafer 201, which includes a substrate 204, which is illustratively a semiconductor such as monocrystalline silicon.
  • the substrate has at least one other layer disposed thereover in this stage of the processing of the wafer.
  • These illustrative layers 202 and 203 may be other dielectric layers (e.g., ILD's), other semiconductor layers, metal layers within an oxide, and other layers within the purview of the artisan of ordinary skill. It is also noted that the low-k ILD of the example embodiments may be fabricated over the PHUS03 0336WO ⁇ resort nTM PCT/IB2004/051793
  • Fig. 2b shows the rotation 206 of the wafer 201 and the deposition of the pre-wet solvent 205, which is illustratively siloxane. This sequence is substantially the same as that described in connection with step 102 of Fig. 1. After the pre-wet is completed, and as shown in Fig. 2c the slurry 207 is deposited while the pre- wetted wafer 201 is spun as at 206. This sequence is essentially the same as that described at step 103. Fig. 2d shows the slurry 208 deposited over the top surface of the wafer 201.
  • the wafer is baked, resulting in the low-k dielectric material layer's 209 being formed over the wafer 201 and as shown in Fig. 2e.
  • This layer 209 may be an ILD, or other dielectric layer as needed.
  • the wafer may be further processed as needed.
  • the processing after the pre-wetting of the wafer as at step 102 of Fig. 1 and Fig. 2b is, for the most part, well-known, and is as described for example in texts such as VLSI Principles and Technology, Silicon and Gallium Arsenide, 2 nd Edition, 1994, by Soreb Ghandi, page 725. The disclosure of this reference is specifically incorporated herein by reference.
  • step 103 the deposition of the slurry of step 103, and the heat treatment of step 104 may be well-known
  • the pre-wet of the example embodiments of step 102 of Fig. 1 and of Fig. 2b is clearly advantageous compared to known methods.
  • the method of the exemplary embodiments results in a significant reduction in the amount of slurry that is required to deposit a layer of slurry of a sufficient thickness to fabricate a low-k ILD of sufficient thickness.
  • the amount of slurry required to form a layer having a certain thickness was reduced from 4.0 ml by a known technique, which does not include a pre-wet, to 1.4 ml of slurry when the pre-wet of the example embodiments is used.
  • This reduction by nearly 65% of the amount of slurry used results in a significant reduction in wasted slurry.
  • the components of the slurry can be among the most expensive in processing semiconductor wafers.
  • applicants have determined that by using the prewetting technique of the example embodiments, the uniformity across the wafer of the resultant SOG layer (low-k ILD) is significantly improved compared to known techniques.
  • a standard method of depositing the SOG by spin-coating results in a layer having a mean thickness of 4482.73 Angstroms, with a standard deviation in thickness of +39.3589.73 Angstroms, or + 0.878%.
  • a layer of SOG fabricated using the pre-wet of the example embodiments had a thickness of 4433.09 Angstroms with a standard deviation of ⁇ 32.2566 Angstroms, or +0.728%.
  • this standard deviation is merely illustrative, and the standard deviation in the thickness may be less than +0.728%.
  • the thickness uniformity and reproducibility may be further improved compared to the example embodiments above, by 'priming' the wafers with hexamethyldisilazane (HMDS) before applying the pre-wet.
  • HMDS hexamethyldisilazane
  • the HMDS vapor is applied, followed by a vacuum heat treatment (bake) at 120 °C for approximately 10 minutes.
  • the example embodiments described so far primarily focus on the use of HSQ in Siloxane solution as the material for the SOG, with Siloxane as the pre-wet.
  • octamethyltrisiloxane and decamethyltetrasiloxane may be used as the pre-wet to possibly further improve the process latitude and to possibly further reduce the volume of SOG solution (slurry) required for forming the low-k dielectric for each wafer.
  • SOG solution slurry
  • octamethyltrisiloxane in concentration of approximately 5 to approximately 50% by volume in combination with hexamethyldisiloxane as the solvent for HSQ instead of Siloxane alone.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Paints Or Removers (AREA)

Abstract

Un procédé (100) de dépôt d'un matériau diélectrique consiste à utiliser (101) un substrat sur lequel est appliquée au moins une couche. Ce procédé consiste en outre à pré-mouiller (102) avec une matière une surface supérieure d'une couche supérieure, à appliquer par centrifugation (103) la solution et à former (104) le matériau diélectrique. A titre d'exemple, ce matériau diélectrique est composé de SiO2 relativement poreux, et présente une constante diélectrique relativement faible. Le pré-mouillage entraîne une réduction des coûts de traitement dans la mesure où il permet de réduire les pertes en solution. En outre, la couche diélectrique (209) présente une épaisseur d'une homogénéité accrue.
EP04770031A 2003-09-19 2004-09-18 Procede de formation de couches dielectriques a faibles constantes dielectriques Withdrawn EP1668683A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US50445203P 2003-09-19 2003-09-19
PCT/IB2004/051793 WO2005029567A1 (fr) 2003-09-19 2004-09-18 Procede de formation de couches dielectriques a faibles constantes dielectriques

Publications (1)

Publication Number Publication Date
EP1668683A1 true EP1668683A1 (fr) 2006-06-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP04770031A Withdrawn EP1668683A1 (fr) 2003-09-19 2004-09-18 Procede de formation de couches dielectriques a faibles constantes dielectriques

Country Status (5)

Country Link
EP (1) EP1668683A1 (fr)
JP (1) JP2007506276A (fr)
KR (1) KR20060096996A (fr)
CN (1) CN1883038A (fr)
WO (1) WO2005029567A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009123104A1 (fr) * 2008-04-02 2009-10-08 三井化学株式会社 Composition et son procédé de production, matériau poreux et son procédé de production, film d'isolation intercouche, matériau semi-conducteur, dispositif semi-conducteur, et film de protection superficiel à bas indice de réfraction

Family Cites Families (7)

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Publication number Priority date Publication date Assignee Title
US5429673A (en) * 1993-10-01 1995-07-04 Silicon Resources, Inc. Binary vapor adhesion promoters and methods of using the same
US6008540A (en) * 1997-05-28 1999-12-28 Texas Instruments Incorporated Integrated circuit dielectric and method
US6066578A (en) * 1997-12-01 2000-05-23 Advanced Micro Devices, Inc. Method and system for providing inorganic vapor surface treatment for photoresist adhesion promotion
US6218020B1 (en) * 1999-01-07 2001-04-17 Alliedsignal Inc. Dielectric films from organohydridosiloxane resins with high organic content
US6541367B1 (en) * 2000-01-18 2003-04-01 Applied Materials, Inc. Very low dielectric constant plasma-enhanced CVD films
JP2002324745A (ja) * 2001-04-25 2002-11-08 Tokyo Ohka Kogyo Co Ltd レジスト膜形成方法
JP2003257836A (ja) * 2002-03-05 2003-09-12 Matsushita Electric Ind Co Ltd 有機膜形成方法

Non-Patent Citations (1)

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Title
See references of WO2005029567A1 *

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Publication number Publication date
WO2005029567A1 (fr) 2005-03-31
CN1883038A (zh) 2006-12-20
JP2007506276A (ja) 2007-03-15
KR20060096996A (ko) 2006-09-13

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