EP1665053A1 - Gestion de blocs effaces dans des memoires flash - Google Patents
Gestion de blocs effaces dans des memoires flashInfo
- Publication number
- EP1665053A1 EP1665053A1 EP04766485A EP04766485A EP1665053A1 EP 1665053 A1 EP1665053 A1 EP 1665053A1 EP 04766485 A EP04766485 A EP 04766485A EP 04766485 A EP04766485 A EP 04766485A EP 1665053 A1 EP1665053 A1 EP 1665053A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- block
- memory
- flag
- memory block
- erased
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000015654 memory Effects 0.000 title claims abstract description 101
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000012217 deletion Methods 0.000 claims description 7
- 230000037430 deletion Effects 0.000 claims description 7
- 238000013507 mapping Methods 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract 1
- 230000004044 response Effects 0.000 description 2
- 108090000248 Deleted entry Proteins 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7205—Cleaning, compaction, garbage collection, erase control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7209—Validity control, e.g. using flags, time stamps or sequence numbers
Definitions
- the invention relates to a method for managing deletion in a memory system with individually erasable memory blocks that can be addressed with real memory block addresses, which are divided into a plurality of writable memory sectors, and which are converted by addressing by means of an assignment table of logical block addresses into one of the real ones Memory block addresses are addressable.
- Flash memory is used in many computer systems, especially in removable memory cards for digital cameras and portable computers. Flash memories are organized in memory blocks with many sectors each. The main characteristics of these memories are that only a limited number of write and erase operations are possible, that only sectors that were previously erased can be written to, and that erasure is only possible in the large memory blocks.
- the writing and deleting processes take a lot more time (up to a factor of 50) than reading. In order to achieve a long service life and fast response times of the storage system, it is therefore important to manage with just a few deletion processes and to carry out the deletion at times when no other read or write operations are pending.
- Patent application DE 198 40 389 describes how the use of certain buffer block sectors can be written without having to delete the entire memory block beforehand. If there are no more buffer blocks, one must be deleted immediately, which delays the write operation.
- US Pat. No. 5,485,595 describes the management of memory blocks in a management table which contains a plurality of flags on the status of the memory blocks. Below these are the flags "USED FLAG” and "OLD FLAG”, which indicate whether there are several versions of the memory block in the memory. The memory blocks with the "OLD FLAG" are waiting to be deleted. However, each time the memory operation is performed, the management table must be searched for the valid entry for the logical block address, which extends the memory operations.
- This object is achieved in that a first flag “erased” about the physical erased state and a second flag “content erased” about the logical erased state is carried for each memory block in the allocation table.
- the memory system considered here with non-volatile memory cells is organized in memory blocks which can be erased individually via an erase operation.
- the memory blocks in turn are divided into sectors that can be written to individually. Writing is only possible in previously deleted memory cells.
- All memory blocks are listed in an allocation table.
- the assignor table is divided into a first area for user data blocks, a second area for management blocks, a third area for buffer blocks and a fourth area for reserve blocks.
- the table contains pointers with memory block addresses and flags to the respective memory blocks which the pointers point.
- the allocator table is accessed by a memory controller with logical block addresses and a real memory block address is assigned to each logical block address. The respective memory operation is carried out in the real memory block assigned to the logical block address via the pointer.
- Memory block is completely physically deleted.
- the second flag "content erased” indicates that the content of the block has not yet been physically deleted, but the content is no longer valid and the block is intended for deletion.
- the first flag "erased” is set in the allocation table after each physical deletion of the associated memory block.
- the second flag "content erased” is set each time the entire content of the memory block becomes invalid. Thus, the two flags each indicate the status of the content of the associated memory block.
- the management of the memory blocks and the execution of the memory operations are carried out by programs in a memory controller.
- the background program searches the allocator table for memory block addresses with the second flag "content erased" set. It deletes memory blocks found in this way, the first flag being set "erased”.
- the buffer block area If no deleted memory block is found in the buffer block area, it is expedient to search for a deleted memory block in the useful data area and to use one as an alternative block. For this purpose, the pointers to the deleted memory block in the user data area and the pointer to an undeleted block in the buffer block area are interchanged, and the undeleted memory block now located in the user data area is given the "content erased" feature.
- the user data area can be very large and heavily occupied, it can take a long time to find a deleted memory block. Therefore, it makes sense to search for a number of deleted memory blocks in the user data area of less than a predetermined threshold value instead of searching the user data area for a deleted memory block, but to delete a memory block in the buffer block area and then use it as an alternative block.
- the programs in the memory controller allow access to any memory blocks and sectors.
- the content should correspond to deleted data, even if the memory cells still have other content. If such a memory block is now accessed by reading, a program in the memory controller recognizes this and returns data, the deleted data corresponds.
- Fig. 1 shows the relationship of the allocator table with the memory blocks
- Fig. 1 the assignment table ZT is shown, which is divided into three areas. These are the user data area NB, the buffer block area BB and the reserve area RB.
- the allocation table ZT is accessed via the logical block address LBA and the associated memory block address SBA is found which points to a memory block SB.
- the flags "erased” ER and "content erased” CER are carried to the memory block addresses SBA.
- the first entry in the allocation table ZT denotes a memory block SB used with data D.
- the flags "erased” ER and “content erased” CER are not set in this case.
- the second entry designates a deleted memory block (111..1), in which the flags are set. In the buffer block area BB there is no deleted entry with the flag "erased” ER set.
- the second entry now points to a memory block, the content of which has been logically deleted, but which still contains the old data D. This is indicated by the combination of flags 01.
- the entry of the buffer block now points to the deleted memory block (111..1). This is now used as an alternative block for writing the new user data.
- the background program will later delete the memory block SB which now belongs to the second entry.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- Memory System (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
L'invention concerne un procédé de gestion de l'effacement dans un système à mémoire comprenant des blocs mémoire (SB) effaçables individuellement, adressables au moyen d'adresses de blocs mémoire réelles (SBA), lesdits blocs mémoire étant subdivisés en une pluralité de secteurs inscriptibles et étant adressables au moyen d'une conversion d'adresse utilisant une table d'affectation (ZT) pour convertir des adresses de blocs logiques (LBA) en l'une des adresses de blocs mémoire réelles respectives (SBA). La table d'affectation (ZT) est subdivisée en au moins une zone de données utiles (NB) et une zone à bloc tampon (BB). L'invention est caractérisée en ce qu'à chaque bloc mémoire (SB) dans la table d'affectation (ZT) sont associés un premier identificateur </= EFFACé >/= (ER) indiquant l'état d'effacement physique, et un second identificateur </= CONTENU EFFACé >/= (CER) indiquant l'état d'effacement logique.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10341618A DE10341618A1 (de) | 2003-09-10 | 2003-09-10 | Verwaltung gelöschter Blöcke in Flash-Speichern |
PCT/EP2004/051782 WO2005026963A1 (fr) | 2003-09-10 | 2004-08-12 | Gestion de blocs effaces dans des memoires flash |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1665053A1 true EP1665053A1 (fr) | 2006-06-07 |
Family
ID=34305636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04766485A Withdrawn EP1665053A1 (fr) | 2003-09-10 | 2004-08-12 | Gestion de blocs effaces dans des memoires flash |
Country Status (9)
Country | Link |
---|---|
US (1) | US20090125668A1 (fr) |
EP (1) | EP1665053A1 (fr) |
JP (1) | JP2007505415A (fr) |
KR (1) | KR20060130013A (fr) |
CN (1) | CN1849590A (fr) |
CA (1) | CA2536992A1 (fr) |
DE (1) | DE10341618A1 (fr) |
TW (1) | TW200519596A (fr) |
WO (1) | WO2005026963A1 (fr) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1936866A (zh) * | 2006-08-18 | 2007-03-28 | 福昭科技(深圳)有限公司 | 具有资料还原功能的闪存记忆体存储机制 |
CN101105774B (zh) * | 2006-10-26 | 2010-08-11 | 福昭科技(深圳)有限公司 | 闪存记忆体在进行数据存取时的逻辑与物理地址转换方法 |
US7515500B2 (en) * | 2006-12-20 | 2009-04-07 | Nokia Corporation | Memory device performance enhancement through pre-erase mechanism |
US20100318723A1 (en) * | 2007-02-23 | 2010-12-16 | Masahiro Nakanishi | Memory controller, nonvolatile memory device, and nonvolatile memory system |
JP4164118B1 (ja) * | 2008-03-26 | 2008-10-08 | 眞澄 鈴木 | フラッシュメモリを用いた記憶装置 |
KR100970537B1 (ko) * | 2008-11-20 | 2010-07-16 | 서울시립대학교 산학협력단 | Ssd 관리 장치 및 방법 |
US20100131726A1 (en) * | 2008-11-26 | 2010-05-27 | Nokia Corporation | Methods, apparatuses, and computer program products for enhancing memory erase functionality |
US8407401B2 (en) | 2008-11-26 | 2013-03-26 | Core Wireless Licensing S.A.R.L. | Methods, apparatuses, and computer program products for enhancing memory erase functionality |
KR101601790B1 (ko) | 2009-09-22 | 2016-03-21 | 삼성전자주식회사 | 암호키 선택장치를 구비하는 스토리지 시스템 및 암호 키 선택방법 |
TWI414940B (zh) * | 2009-12-30 | 2013-11-11 | Phison Electronics Corp | 區塊管理與資料寫入方法、快閃記憶體儲存系統與控制器 |
TWI475385B (zh) * | 2012-03-14 | 2015-03-01 | Phison Electronics Corp | 程式化記憶胞與資料讀取方法、記憶體控制器與儲存裝置 |
KR20140056657A (ko) | 2012-10-30 | 2014-05-12 | 삼성전자주식회사 | 메인 메모리를 구비한 컴퓨터 시스템 및 그것의 제어 방법 |
TWI557561B (zh) * | 2016-02-05 | 2016-11-11 | 群聯電子股份有限公司 | 記憶體管理方法、記憶體控制電路單元與記憶體儲存裝置 |
US11288007B2 (en) * | 2019-05-16 | 2022-03-29 | Western Digital Technologies, Inc. | Virtual physical erase of a memory of a data storage device |
US11581048B2 (en) * | 2020-11-30 | 2023-02-14 | Cigent Technology, Inc. | Method and system for validating erasure status of data blocks |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5485595A (en) * | 1993-03-26 | 1996-01-16 | Cirrus Logic, Inc. | Flash memory mass storage architecture incorporating wear leveling technique without using cam cells |
JP3464836B2 (ja) * | 1995-01-19 | 2003-11-10 | 富士通株式会社 | 記憶装置のメモリ管理装置 |
US5838614A (en) * | 1995-07-31 | 1998-11-17 | Lexar Microsystems, Inc. | Identification and verification of a sector within a block of mass storage flash memory |
JPH0997205A (ja) * | 1995-09-28 | 1997-04-08 | Canon Inc | フラッシュrom管理方法及び装置及びコンピュータ制御装置 |
US5953737A (en) * | 1997-03-31 | 1999-09-14 | Lexar Media, Inc. | Method and apparatus for performing erase operations transparent to a solid state storage system |
JP3718578B2 (ja) * | 1997-06-25 | 2005-11-24 | ソニー株式会社 | メモリ管理方法及びメモリ管理装置 |
JP2000227871A (ja) * | 1999-02-05 | 2000-08-15 | Seiko Epson Corp | 不揮発性記憶装置、その制御方法、および、情報記録媒体 |
-
2003
- 2003-09-10 DE DE10341618A patent/DE10341618A1/de not_active Withdrawn
-
2004
- 2004-08-12 CN CNA2004800260130A patent/CN1849590A/zh active Pending
- 2004-08-12 WO PCT/EP2004/051782 patent/WO2005026963A1/fr active Application Filing
- 2004-08-12 JP JP2006530229A patent/JP2007505415A/ja active Pending
- 2004-08-12 US US10/571,590 patent/US20090125668A1/en not_active Abandoned
- 2004-08-12 EP EP04766485A patent/EP1665053A1/fr not_active Withdrawn
- 2004-08-12 KR KR1020067004108A patent/KR20060130013A/ko not_active Application Discontinuation
- 2004-08-12 CA CA002536992A patent/CA2536992A1/fr not_active Abandoned
- 2004-09-02 TW TW093126506A patent/TW200519596A/zh unknown
Non-Patent Citations (1)
Title |
---|
See references of WO2005026963A1 * |
Also Published As
Publication number | Publication date |
---|---|
KR20060130013A (ko) | 2006-12-18 |
CA2536992A1 (fr) | 2005-03-24 |
DE10341618A1 (de) | 2005-05-04 |
WO2005026963A1 (fr) | 2005-03-24 |
TW200519596A (en) | 2005-06-16 |
JP2007505415A (ja) | 2007-03-08 |
US20090125668A1 (en) | 2009-05-14 |
CN1849590A (zh) | 2006-10-18 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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17P | Request for examination filed |
Effective date: 20060228 |
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AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR |
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DAX | Request for extension of the european patent (deleted) | ||
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: HYPERSTONE GMBH |
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17Q | First examination report despatched |
Effective date: 20100628 |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
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18W | Application withdrawn |
Effective date: 20100909 |