EP1632061A2 - Systeme et procede de transmission sur un bus - Google Patents

Systeme et procede de transmission sur un bus

Info

Publication number
EP1632061A2
EP1632061A2 EP04753996A EP04753996A EP1632061A2 EP 1632061 A2 EP1632061 A2 EP 1632061A2 EP 04753996 A EP04753996 A EP 04753996A EP 04753996 A EP04753996 A EP 04753996A EP 1632061 A2 EP1632061 A2 EP 1632061A2
Authority
EP
European Patent Office
Prior art keywords
data
digital data
bit
bus
communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP04753996A
Other languages
German (de)
English (en)
Other versions
EP1632061B1 (fr
Inventor
Hamed Eshraghian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Starent Networks LLC
Original Assignee
Starent Networks LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Starent Networks LLC filed Critical Starent Networks LLC
Publication of EP1632061A2 publication Critical patent/EP1632061A2/fr
Application granted granted Critical
Publication of EP1632061B1 publication Critical patent/EP1632061B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4273—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a clocked protocol

Definitions

  • the present application relates to systems and methods for exchanging electrical signals, and in particular to the communication of digital information between two or more electronic components over a communication bus.
  • the signals can be in analog form, generally signified by a magnitude of some characteristic of the signal, e.g. voltage. Alternately, the signals can be in digital form, signified by discrete values of the signal, e.g. binary signals (0/1, +1/-1, high/low, etc.).
  • a bus can contain any number of conducting lines, and can be formed by grouping the conducting lines physically or logically.
  • Buses can be produced in bundles, braids, or flat ribbons, and can have endpoint connectors or terminators suitable for making contact between the components coupled by the buses.
  • Buses can also be produced by laying out solder lines on an electronic circuit board, or by etching conductive traces into a semiconducting substrate. When packaged in a chip, buses can be manufactured along with the chip in the package.
  • the CSIX bus provides lines for data communication, including header information, a Ready bit, and vertical parity checking bits.
  • Another available communication bus is the proprietary Focus bus from Vitesse Semiconductor Corporation.
  • the Focus bus provides data lines, header information, but no Ready bit or vertical parity information. Both the CSIX and Focus buses require flow control data to be exchanged outside the buses, on separate lines, which consume valuable bus and pin locations.
  • the CSIX bus requires start-of- frame (SOF) and parity (PAR) lines in addition to clock and data lines.
  • the Focus bus requires flow control lines in addition to clock and data lines.
  • the buses provide improved bus availability, bandwidth, and performance by utilizing common clock signals instead of conventional clock sourcing.
  • the buses use useful and new cell formats that enable devices to exchange information and payloads in a streamlined fashion within existing hardware limitations that are less prone to error.
  • a bus and method for using the same is provided to satisfy the "F8" bus used in the ST- 16 intelligent mobile gateway device from Starent Networks of Tewksbury, Mass., or similar devices.
  • One embodiment of the present disclosure is directed to a method for exchanging digital data between devices over a bus, including providing at least one bit of data to indicate the type of digital data being exchanged; providing at least one bit of data to indicate whether a device coupled to the bus is ready to communicate with other devices over the bus; and providing at least one vertical parity bit for checking for error conditions in corresponding bits of the digital data.
  • Another embodiment of the present disclosure is directed to a system for transferring digital data between at least two devices, including a communication bus having a plurality of communication Unes, the communication bus coupled at a first end thereof to a first device and coupled at a second end thereof to a second device; at least one of the plurality of communication lines carrying a bit of data to indicate the type of digital data being exchanged; at least one of the plurality of communication lines carrying a bit of data to indicate whether a device coupled to the communication bus is ready to communicate with other devices over the communication bus; and the plurality of communication lines carrying vertical parity bits for checking for error conditions in corresponding bits of the digital data.
  • Figure 1 illustrates an exemplary grouping of FPGA circuits arranged on a motherboard and interconnected by communication buses;
  • Figure 2 illustrates an 8-bit byte of a data cell, with notation for numbering the bits
  • Figure 3 illustrates an exemplary F8 cell format, showing the information contained in each byte and bit of the cell
  • Figure 4 illustrates the operation of vertical parity in a data cell
  • Figure 5 illustrates data blocks within an exemplary F8 data cell, including payload cells
  • Figure 6 illustrates a null cell.
  • FIG. 1 illustrates an exemplary motherboard 100 having various logic chips, circuits, and communication elements coupled thereto.
  • Motherboard 100 is typically provided with connection pins (not shown) that deliver power, ground connections, data, and control signals between the motherboard and a computer system in which the motherboard is installed.
  • the computer system may be local and has motherboard 100 installed into a hardware slot designed for such cards.
  • the computer system may be also be remote or distributed such that motherboard 100 and the computer system are not in physical proximity to one another.
  • the motherboard 100 of Figure 1 includes a voice data transport (VDT) field programmable gate array (FPGA) chip 110 that manages aspects of delivery and processing of information from voice communication sessions.
  • VDT voice data transport
  • FPGA field programmable gate array
  • Two other FPGAs are disposed on motherboard 100: a general purpose digital signal processing (GP DSP) chip 130 and a voice over internet protocol digital signal processing (VoIP DSP) chip 140.
  • the chips in this example are constructed as packaged integrated circuits (ICs) and are generally mounted on cards or daughter boards, e.g. 131, 132, which themselves are electrically and/or mechanically coupled to motherboard 100, but the FPGAs may also be placed directly onto appropriate mating connections on motherboard 100.
  • Each of the FPGAs 130 and 140 are connected to FPGA 110 by "F8" communication bus lines 150.
  • An F8 bus has 16 total lines, consisting of 8 lines for receiving data, and another 8 lines for transmitting data. This is indicated by the slash symbols accompanying the numerals "8" in the figures, as well as the directionality of the arrows and the letters “R” (receive) and “T” (transmit).
  • F8 bus 150A connects VDT 110 and GP DSP 130
  • F8 bus 150B connects VDT 110 and VoIP DSP 140.
  • not all buses connecting the various components need to be of the same design or of the F8 type, but rather, it is possible to have a variety of bus types represented on a single board or system if appropriate.
  • This system of integrated circuits and associated computing components provides the ability to receive, process, store, and retransmit digital data from a variety of sources and in one or more formats.
  • the circuits may be used to handle voice and data communication in internet protocol (IP), asynchronous transfer mode (ATM), or time division multiplexing (TDM) applications.
  • IP internet protocol
  • ATM asynchronous transfer mode
  • TDM time division multiplexing
  • a clock source usually a solid state resonator crystal 120 is powered from some source of power on a daughter board or a motherboard 110.
  • the clock 120 generates a cyclical (CLK) signal suitable for actuating and synchronizing other parts of the system.
  • CLK cyclical
  • the clock signal is delivered to the FPGAs 110, 130, and 140 through clock Unes 121, 122, and 123, respectively.
  • the clock signals to all of the FPGAs are thus shared from their source 120 and will be substantially synchronized (having contemporaneous rising and falUng edges).
  • the present system of sharing a common clock signal is preferable to conventional clock sourcing.
  • a clock signal is generated at a clock and then passed to a first circuit.
  • the first circuit in turn passes on a clock signal to a second circuit, which may pass a clock signal to a third, and so on.
  • Clock sourcing works by a two-way (back and forth) communication between the circuits. Therefore, clock sourcing requires two lines dedicated to the exchange of clock signal information.
  • a shared clock signal method only requires a single clock line per clocked device (121, 122, 123), and provides a savings of one communication line at each of the circuits. Therefore, in shared or common clocked embodiments, an extra communication line is freed up to be used for other communication functions or data transfer.
  • a double-eight communication bus such as the F8 bus
  • the communication is performed according to a pre-determined format so that the two communicating components may properly parse the significance of the information.
  • a preUminary step a convention for illustrating and describing the information content is shown in Figure 2.
  • An exemplary byte 200 is shown having 8 bits 210. The bits are designated sequentially from 0 to 7. Each bit (binary digit) carries a "0" or a "1" (or their equivalent) information.
  • bit number 0 carries a "1" datum of information
  • bit number 1 carries a "0" datum of information
  • bit number 2 carries a "1” datum of information
  • the entire 8-bit byte 200 carries the data "10001101."
  • the bus 150 is usually “unconcerned” with the actual data it carries, and the communicating circuits are the elements that will parse and process the information sent and received over the bus.
  • a short hand notation 220 is used to indicate a group of bits carrying information of some significance.
  • Figure 2 provides an example of a group of bits "100" carried in bit 7 through bit 5 of byte 200. This group of bits is indicated by the notation "7:5" or seven-through-five. This notation will be used below to describe the use of the bytes and what information is delivered in an exemplary F8 format.
  • Figure 3 illustrates an exemplary format of a cell of information comprising several 8-bit bytes. Data strings, structures, and words of other size and other orderings of the information within the cell are possible and can be implemented by those skilled in the art.
  • the first byte (byte 0) carries three pieces of information:
  • bits 7:5 the type of cell.
  • the figure shows several types of cell types that can be indicated by the 7:5 bits of byte 0. The are:
  • bits 3:0 are reserved, and not used by the devices.
  • the next byte (byte 1) carries the Byte Count (BC), or number of bytes of payload data in the cell, in bits 6:0, with bit 7 being reserved.
  • the byte count is an integer number, represented in a 7-bit binary format in the present example.
  • more than one byte may be used to signify the number of payload bytes in the cell. This could be used if the number of payload bytes is too large to be represented by the bits in a single Byte Count byte or portion thereof.
  • the final byte (number BC+2) is for vertical parity (VP). Parity bits are used for error checking.
  • Errors arise in digital communication from a variety of sources. For example, electrical interference can cause a "0" bit to arrive at its destination as a "1" bit, or vice versa. A parity sense is adopted to check for flipped bits. Even vertical parity means that an even number of "l”s were packaged in a column of cells at its origin, and odd vertical parity means that an odd number of "l”s were packaged in a column of cells at its origin.
  • Figure 4 illustrates an exemplary F8 cell similar to that described above, having odd parity error checking.
  • Data content of the first two columns 310, 320 are shown for illustrative purposes, while the rest of the cell's data values are not shown for simpUcity.
  • the last row 350 of cell 300 contains the VP bits.
  • Bits 330 and 340 contain the VP bits for columns 310 and 320, respectively. Each VP bit is made to produce an odd total number of "l”s in its column.
  • bit 330 is a "1" because its column contains two other "l”s, and a "1" is needed in VP bit location 330 to make the number of "l”s for column 310 equal 3, an odd number.
  • VP bit 340 is made to be a "0" because the column 320 otherwise contains one "1" value, which is an odd number of "l”s.
  • the VP bits in the other six positions of row 350 would similarly be made to be “0” or "1” as necessary to keep the total number of "l”s per column of the cell odd. If the figure was for an even parity configuration, the "l"s and "0"s of the VP row 350 would be interchanged.
  • Figure 5 illustrates another F8 cell 400 according to the present exemplary format, showing blocks of bits in each byte of the cell signifying various content. The shaded blocks of bits are reserved or unused.
  • the cell illustrated in Figure 5 includes 64 8-bit data (payload) bytes, D0...D63. In some embodiments, this number of payload bytes facilitates communication with components using the TDM format or IP packet format. Other embodiments could have less, more, or no payload cells.
  • Figure 6 illustrates a "null" cell 500.
  • Byte 0 includes the Type of cell in bits 7:5 as described previously. This type according to the example used is defined by bit values "100" in the 5:7 bits 510.
  • the Ready bit 520 follows in bit 4 of byte 0.
  • null cell 500 Byte 1 of null cell 500 is used for vertical parity. No payload data is carried in a null cell, but it does carry the Ready bit to indicate the availability of the device.
  • new communication buses and methods for carrying data over the buses have been presented.
  • shared clocking of interconnected devices provides a savings in lines used for clock signals to the devices.
  • data cell formats including flow control functionality and being indicative of the type of data cell, including whether the data cell is a null cell are provided.
  • the disclosure teaches a way to populate a data cell with binary information suitable for use with the F8 bus and compatible systems.
  • the systems and methods include provisions for error checking using vertical parity, and improve the overall performance and pin/line availability to devices communicating over the bus lines. Therefore, increased functionality and lower cost can be achieved in digital communication systems using such buses.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Information Transfer Systems (AREA)
  • Selective Calling Equipment (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Abstract

L'invention concerne des systèmes et des procédés de transmission de données sur un bus de transmission. Dans certains aspects de l'invention, les données sont des informations numériques transmises sur un bus à lignes multiples reliant au moins deux dispositifs électroniques, tels que des circuits intégrés. L'invention concerne également des formats utiles permettant d'organiser les données dans des cellules de données transmises sur le bus, ainsi que des exemples de signaux d'horloge partagés, d'informations de bit prêt et de contrôle de parité verticale.
EP04753996A 2003-06-03 2004-06-03 Systeme et procede de transmission sur un bus Expired - Lifetime EP1632061B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47556103P 2003-06-03 2003-06-03
PCT/US2004/017288 WO2004109530A2 (fr) 2003-06-03 2004-06-03 Systeme et procede de transmission sur un bus

Publications (2)

Publication Number Publication Date
EP1632061A2 true EP1632061A2 (fr) 2006-03-08
EP1632061B1 EP1632061B1 (fr) 2007-10-03

Family

ID=33511694

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04753996A Expired - Lifetime EP1632061B1 (fr) 2003-06-03 2004-06-03 Systeme et procede de transmission sur un bus

Country Status (8)

Country Link
US (2) US20050033891A1 (fr)
EP (1) EP1632061B1 (fr)
JP (1) JP2006526854A (fr)
CN (1) CN1817012A (fr)
AT (1) ATE375050T1 (fr)
CA (1) CA2528310A1 (fr)
DE (1) DE602004009310T2 (fr)
WO (1) WO2004109530A2 (fr)

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Also Published As

Publication number Publication date
WO2004109530A8 (fr) 2005-06-16
CA2528310A1 (fr) 2004-12-16
EP1632061B1 (fr) 2007-10-03
CN1817012A (zh) 2006-08-09
WO2004109530A2 (fr) 2004-12-16
DE602004009310T2 (de) 2008-07-10
DE602004009310D1 (de) 2007-11-15
US20050033891A1 (en) 2005-02-10
ATE375050T1 (de) 2007-10-15
WO2004109530B1 (fr) 2005-08-04
US20090210593A1 (en) 2009-08-20
WO2004109530A3 (fr) 2005-04-21
JP2006526854A (ja) 2006-11-24

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