US20220066976A1

US20220066976A1 - PCI Express to PCI Express based low latency interconnect scheme for clustering systems

Info

Publication number: US20220066976A1
Application number: US17/523,878
Authority: US
Inventors: Mammen Thomas
Original assignee: Individual
Current assignee: Individual
Priority date: 2005-10-04
Filing date: 2021-11-10
Publication date: 2022-03-03
Also published as: US20160378708A1; US20120226835A1; US20070098001A1; US9519608B2; US20150127875A1; US8189603B2; US11194754B2; US20220374388A1; US20220100694A1; US20230315674A1

Abstract

PCI-Express (PCIE) is a Bus or I/O interconnect standard typically used for communication between a computer or computing system root complex and a plurality of peripheral devices, where the PCIE system typically include a PCIE switch which has only a single inbound PCIE port. An outbound PCIE port on the computing system connects to the single inbound PCIE port of the PCIE switch. The invention discloses a PCIE based interconnect scheme enabling switching and inter-connection between a plurality of PCIE enabled systems, each having a PCIE root complex forming a cluster. The technical advances and scalability of PCIE architecture can be applied to enable data transport between the systems forming the cluster. The PCIE network switch comprise a plurality of inbound ports such that each of the plurality of computing systems connects to an inbound port of the network switch for enabling data transmission and communication within the cluster.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 15/175,800 titled “PCI Express to PCI Express based low latency interconnect scheme for clustering systems” filed on Jun. 7, 2016, which is a continuation of U.S. application Ser. No. 14/588,937 titled “PCI Express to PCI Express based low latency interconnect scheme for clustering systems” filed on Jan. 3, 2015, currently U.S. Pat. No. 9,519,608 which is a continuation of U.S. patent application Ser. No. 13/441,883 titled “PCI Express to PCI Express based low latency interconnect scheme for clustering systems” filed on Apr. 8, 2012, which was abandoned, which is a continuation of U.S. patent application Ser. No. 11/242,463 titled “PCI Express to PCI Express based low latency interconnect scheme for clustering systems” filed on Oct. 4, 2005 which issued as U.S. Pat. No. 8,189,603 on May 29, 2012, all of which have a common inventor, and are hereby incorporated by reference for all that they contain.

TECHNICAL FIELD

The invention generally relates to providing high speed interconnect between systems within an interconnected cluster of systems.

BACKGROUND AND PRIOR ART

The need for high speed and low latency cluster interconnect scheme for data and information transport between systems have been recognized as a limiting factor to achieving high speed operation in clustered systems and one needing immediate attention to resolve. The growth of interconnected and distributed processing schemes have made it essential that high speed interconnect schemes be defined and established to provide the speeds necessary to take advantage of the high speeds being achieved by data processing systems and enable faster data sharing between interconnected systems.
There are today interconnect schemes that allow data transfer at high speeds, the most common and fast interconnect scheme existing today is the Ethernet connection allowing transport speeds from 10 MB to as high as 10 GB/sec. TCP/IP protocols used with Ethernet have high over-head with inherent latency that make it unsuitable for some distributed applications. Further TCP/IP protocol tends to drop data packets under high traffic congestion times, which require resend of the lost packets which cause delays in data transfer and is not acceptable for high reliability system operation. Recent developments in optical transport also provide high speed interconnect capability. Efforts are under way in different areas of data transport to reduce the latency of the interconnect as this is a limitation on growth of the distributed computing, control and storage systems. All these require either changes in transmission protocols, re-encapsulation of data or modulation of data into alternate forms with associated delays increase in latencies and associated costs.

DESCRIPTION

PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled computing systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected computing systems can be any computing, control, storage or embedded systems. The scalability of the interconnect will allow the cluster to grow the bandwidth between the computing systems as they become necessary without changing to a different connection architecture.

What is Proposed

PCI Express (PCIE) has achieved a prominent place as the I/O interconnect standard for use inside computers, processing system and embedded systems that allow serial high speed data transfer to and from peripheral devices. The typical PCIE provides 2.5-3.8 GB transfer rate per link (this may change as the standard and data rates change). The PCIE standard is evolving fast, becoming faster and starting become firm and used within more and more systems. Typically each PCIE based system has a root complex which controls all connections and data transfers to and from connected peripheral devices through PCIE peripheral end points or peripheral modules. What is disclosed is the use of PCIE standard based peripherals enabled for interconnection to similar PCIE standard based peripheral connected directly using data links, as an interconnect between multiple systems, typically through one or more network switches. This interconnect scheme by using PCIE based protocols for data transfer over direct physical connection links between the PCIE based peripheral devices, (see FIG. 1), without any intermediate conversion of the transmitted data stream to other data transmission protocols or encapsulation of the transmitted data stream within other data transmission protocols, thereby reducing the latencies of communication between the connected PCI based systems within the cluster. The PCIE standard based peripheral enabled for interconnection at a peripheral end point of the system, by directly connecting using PCIE standard based peripheral to PCIE standard based peripheral direct data link connections to the switch, provides for increase in the number of links per connection as bandwidth needs of system interconnections increase and thereby allow scaling of the band width available within any single interconnect or the system of interconnects as required.

Some Advantages of the Proposed Connection Scheme:

1. Reduced Latency of Data transfer as conversion from PCIE to other protocols like
Ethernet are avoided during transfer.
2. The number of links per connection can scale from X1 to larger numbers X32 or even X64 as PCIE capabilities increase to cater to the connection bandwidth needed. Minimum change in interconnect architecture is needed with increased bandwidth, enabling easy scaling with need.
3. Any speed increase in the link connection due to technology advance is directly applicable to the interconnection scheme.
4. Standardization of the PCIE based peripheral will make components easily available from multiple vendors, making the implementation of interconnect scheme easier and cheaper.
5. The PCIE based peripheral to PCIE based peripheral links in connections allow ease of software control and provide reliable bandwidth.
6. The use of standardized PCIE based peripheral modules enabled for interconnection as out bound port and the use of PCI-Express enabled port on the PCI-Express based network switch for interconnection between PCI-Express based network switches will allow for easy expansion of the cluster as computing needs grow.
7. The PCIE links and switches are agnostic to the data transmission and can be updated with new technology as they become available, to speed up data transfer between clustered PCI-Express enabled computing systems, (also called PCIE computing systems that are computing systems using PCI-Express bus for peripheral component interconnection, where the PCIE bus is under the control of a root complex of a respective computing system) without changing the capabilities and protocols of the interconnect scheme.

DESCRIPTION OF FIGURES

FIG. 1 Typical Interconnected (multi-system) cluster (shown with eight systems connected in a star architecture using direct connected data links between PCIE standard based peripheral to PCIE standard based peripheral)

FIG. 2—is a cluster using multiple interconnect modules or switches to interconnect smaller clusters.

Explanation of Numbering and Lettering in FIG. 1
(1) to (8): Number of Systems interconnected in FIG. 1 (9): Switch sub-system. (10): Software configuration and control input for the switch. (1 a) to (8 a): PCI Express based peripheral module (PCIE Modules) attached to systems. (1 b) to (8 b): PCI Express based peripheral modules (PCIE Modules) at switch. (1L) to (8L): PCIE based peripheral module to PCIE based peripheral module connections having n-links (n-data links)
Explanation of Numbering and Lettering in FIG. 2
(12-1) and (12-2): clusters (9-1) and (9-2): interconnect modules or switch sub-systems. (10-1) and (10-2): Software configuration inputs (11-1) and (11-2): Switch to switch interconnect module in the cluster (11L): Switch to switch interconnection

DESCRIPTION OF INVENTION

PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.
FIG. 1 is a typical cluster interconnect. The Multi-system cluster shown consist of eight units or systems {(1) to (8)} that are to be interconnected. Each system is PCI Express (PCIE) based system with a PCIE root complex for control of data transfer to and from connected peripheral devices via PCIE peripheral modules as is standard for PCIE based systems. Each system to be interconnected has at least a PCIE based peripheral module {(1 a) to (8 a)} as an IO module, at the interconnect port enabled for system interconnection, with n-links built into or attached to the system. (9) is an interconnect module or a switch sub-system, which has number of PCIE based connection modules equal to or more than the number of systems to be interconnected, in this case of FIG. 1 this number being eight {(1 b) to (8 b)}, that can be interconnected for data transfer through the switch. A software based control input is provided to configure and/or control the operation of the switch and enable connections between the switch ports for transfer of data. Link connections {(1L) to (8L)} attach the PCIE based peripheral modules 1 a to 8 a, enabled for interconnection on the respective systems 1 to 8, to the on the switch with n links. The value of n can vary depending on the connect band width required by the system.
When data has to be transferred between say system 1 and system 5, in the simple case, the control is used to establish an internal link between PCIE based peripheral modules 1 b and 5 b at the respective ports of the switch. A hand shake is established between outbound communication enabled PCIE based peripheral module (PCIE Module) 1 a and inbound PCIE module 1 b at the switch port and inbound PCIE module 5 a on the switch port and outbound communication enabled PCIE module 5 b. This provides a through connection between the PCIE modules 1 a to 5 b through the switch allowing data transfer. Data can then be transferred at speed between the modules and hence between systems. In more complex cases data can also be transferred and queued in storage implemented in the switch, at the ports and then when links are free transferred out to the right systems at speed.
Multiple systems can be interconnected at one time to form a multi-system that allow data and information transfer and sharing through the switch. It is also possible to connect smaller clusters together to take advantage of the growth in system volume by using an available connection scheme that interconnects the switches that form a node of the cluster.
If need for higher bandwidth and low latency data transfers between systems increase, the connections can grow by increasing the number of links connecting the PCIE modules between the systems in the cluster and the switch without completely changing the architecture of the interconnect. This scalability is of great importance in retaining flexibility for growth and scaling of the cluster.
It should be understood that the system may consist of peripheral devices, storage devices and processors and any other communication devices. The interconnect is agnostic to the type of device as long as they have a PCIE module at the port to enable the connection to the switch. This feature will reduce the cost of expanding the system by changing the switch interconnect density alone for growth of the multi-system.
PCIE is currently being standardized and that will enable the use of the existing PCIE modules to be used from different vendors to reduce the over all cost of the system. In addition using a standardized module in the system as well as the switch will allow the cost of software development to be reduced and in the long run use available software to configure and run the systems.
As the expansion of the cluster in terms of number of systems, connected, bandwidth usage and control will all be cost effective, it is expected the overall system cost can be reduced and overall performance improved by standardized PCIE module use with standardized software control.
Typical connect operation may be explained with reference to two of the systems, example system (1) and system (5). System (1) has a PCIE module (1 a) at the interconnect port and that is connected by the connection link or data-link or link (1L) to a PCIE module (1 b) at the IO port of the switch (9). System (5) is similarly connected to the switch trough the PCIE module (5 a) at its interconnect port to the PCIE module (5 b) at the switch (9) IO port by link (5L). Each PCIE module operates for transfer of data to and from it by standard PCI Express protocols, provided by the configuration software loaded into the PCIE modules and switch. The switch operates by the software control and configuration loaded in through the software configuration input.
FIG. 2 is that of a multi-switch cluster. As the need tom interconnect larger number of systems increase, it will be optimum to interconnect multiple switches of the clusters to form a new larger cluster. Such a connection is shown in FIG. 2. The shown connection is for two smaller clusters (12-1 and 12-2) interconnected using PCIE modules that can be connected together using any low latency switch to switch connection (11-10 and 11-2), connected using interconnect links (11L) to provide sufficient band width for the connection. The switch to switch connection transmits and receives data and information using any suitable protocol and the switches provide the interconnection internally through the software configuration loaded into them.
The following are some of the advantages of the disclosed interconnect scheme 1. Provide a low latency interconnect for the cluster. 2. Use of PCI Express based protocols for data and information transfer within the cluster. 3. Ease of growth in bandwidth as the system requirements increase by increasing the number of links within the cluster. 4. Standardized PCIE component use in the cluster reduce initial cost. 5. Lower cost of growth due to standardization of hardware and software. 6. Path of expansion from a small cluster to larger clusters as need grows. 7. Future proofed system architecture. 8. Any speed increase in the switch and link connections due to technology advance is directly applicable to the interconnection scheme.
The circuit implementations can be any or a combination of Integrated-circuit, FPGA, Silicon on Chip (SOC), chip on board (COB), optical, or hybrid circuit implementations. The disclosed interconnect scheme provides advantages for low latency multi-system cluster growth that are not available from any other source.
While the invention has been described in terms of several embodiments, those of ordinary skill in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. Multiple existing methods and methods developed using newly developed technology may be used to establish the hand shake between systems and to improve data transfer and latency. The description is thus to be regarded as illustrative instead of limiting and capable of using any new technology developments in the field of communication an data transfer. There are numerous other variations to different aspects of the invention described above, which in the interest of conciseness have not been provided in detail. Accordingly, other embodiments are limited only within the scope of the claims.

Claims

1. A PCI-Express switch device for transferring information between at least first and second PCI-Express enabled computing systems, wherein each of the PCI-Express enabled computing systems comprise a PCI-Express bus system that is under control of a PCI-Express root complex, the PCI-Express switch device comprising:

a plurality of inbound PCI-Express ports, wherein at least first and second inbound PCI-Express ports of the plurality of inbound PCI-Express ports are configured for sending and receiving data and network packets in communication with an outbound PCI-Express port on each of the first and second PCI-Express enabled computing systems respectively.

2. The PCI-Express switch device of claim 1, further comprising a first PCI-Express expansion port, wherein the first PCI-Express expansion port utilizes PCI-Express protocol and is enabled to connect to a second PCI-Express expansion port on a second PCI-Express switch device.

3. The PCI-Express switch device of claim 1, wherein the switch device further comprises one or more outbound PCI-Express ports for communicating with PCI-Express peripheral devices.

4. The PCI-Express switch device of claim 1, wherein the PCI-Express switch device is configured to transfer data between the PCI-Express enabled computing systems using PCI-Express protocol.

5. The PCI-Express switch device of claim 1, wherein the PCI-Express switch device comprises any of a silicon device or a circuit module.

6. A PCI-Express switch device for transferring information between at least first and second PCI-Express enabled computing systems, wherein each of the PCI-Express enabled computing systems comprises a PCI-Express bus system that is under control of a PCI-Express root complex, the PCI-Express switch device comprising:

at least first and second inbound PCI-Express ports wherein the inbound PCI-Express ports are connectable to at least the first and the second PCI-Express enabled computing systems respectively, wherein the PCI-Express switch comprises a plurality of inbound PCI-Express ports;

wherein the PCI-Express switch receives via at least the first inbound PCI-Express port of the PCI-Express switch, a first data packet transmitted from an outbound PCI-Express port on the first PCI-Express enabled computing system; and

wherein the PCI-Express switch transmits the first data packet from the second inbound PCI-Express port of the PCI-Express switch, the first data packet subsequently being receivable by an outbound PCI-Express port on the second PCI-Express enabled computing system.

7. The PCI-Express switch device of claim 6, further comprising a first PCI-Express expansion port, wherein the first PCI-Express expansion port utilizes PCI-Express protocol and is enabled to connect to a second PCI-Express expansion port on a second PCI-Express switch device.

8. The PCI-Express switch device of claim 7, wherein the PCI-Express switch device is configured to transfer data between the PCI-Express enabled computing systems using PCI-Express protocol.

9. The PCI-Express switch device of claim 6, wherein the PCI-Express switch device comprises a plurality of inbound PCI-Express ports.

10. The PCI-Express switch device of claim 6, wherein the PCI-Express switch device comprises any of a silicon device or a circuit module.

11. A PCI-Express switch device for transferring data between at least first and second PCI-Express enabled computing systems, the PCI-Express switch device comprising:

a plurality of inbound PCI-Express ports that enable transferring data from at least the first PCI-Express enabled computing system to at least the second PCI-Express enabled computing system using PCI-Express protocol, wherein each of the PCI-Express enabled computing systems comprise a PCI-Express bus under control of a root complex, wherein:

a) a first inbound PCI-Express port on the PCI-Express switch device is configurable to receive a first data packet from an outbound PCI-Express port on the first PCI-Express enabled computing system ,;

b) the PCI-Express switch device transfers the first data packet from the first inbound PCI-Express port on the PCI-Express switch to a second inbound PCI-Express port on the PCI-Express switch; and

c) the second inbound PCI-Express port on the PCI-Express switch device is configurable to transfer the first data packet from the second inbound PCI-Express port on the PCI-Express switch device to an outbound PCI-Express port on the second PCI-Express enabled computing system.

12. The PCI-Express switch device of claim 11, further enabling transfer of a second data packet from at least the second PCI-Express enabled computing system to at least the first PCI-Express enabled computing system using PCI-Express protocol, wherein:

d) the PCI-Express switch device is enabled to receive the second data packet from the outbound PCI-Express port on the second PCI-Express enabled computing system;

e) the PCI-Express switch device transfers the second data packet from the second inbound PCI-Express port on the PCI-Express switch device to the first inbound PCI-Express port on the PCI-Express switch; and

f) PCI-Express switch device is enabled to transfer the second data packet from the first inbound PCI-Express inbound port on the PCI-Express switch to the outbound PCI-Express port on the first computing system.

13. The PCI-Express switch device of claim 12, further comprising a first PCI-Express expansion port, wherein the first PCI-Express expansion port utilizes PCI-Express protocol and is enabled to connect to a second PCI-Express expansion port on a second PCI-Express switch device.

14. The PCI-Express switch device of claim 13 wherein a data packet received by the PCI-Express switch from either the first or second PCI-Express enabled computing systems, is transmitted via the first PCI-Express expansion port to the second PCI-Express expansion port on the second PCI-Express switch device, whereby the second PCI-Express switch device transmits the data packet via an inbound PCI-Express port on the second PCI-Express switch device to an outbound PCI-Express port on a third PCI-Express enabled computing system.

15. The PCI-Express switch device of claim 11, wherein the PCI-Express switch device comprises one or more outbound PCI-Express ports for communicating with PCI-Express peripheral devices.

16. The PCI-Express switch device of claim 12, wherein data transfer within the PCI-Express enabled computing systems over the PCI Express bus that is connectable to the PCI-Express switch device, is under control of the root complex.

17. The PCI-Express switch device of claim 12, wherein the PCI-Express switch device is configured to transfer data between the PCI-Express enabled computing systems using PCI-Express protocol.

18. The PCI-Express switch device of claim 11, wherein the PCI-Express switch device comprises any of a silicon device or a circuit module.