Classifications

• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
  • G03F7/7055—Exposure light control in all parts of the microlithographic apparatus, e.g. pulse length control or light interruption
  • G03F7/70558—Dose control, i.e. achievement of a desired dose
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
  • G03F7/70605—Workpiece metrology
  • G03F7/70616—Monitoring the printed patterns
  • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
  • G03F7/70605—Workpiece metrology
  • G03F7/70653—Metrology techniques
  • G03F7/70658—Electrical testing

Definitions

• the invention relates to semiconductor processing. More particularly the invention relates to the determining effects of process changes in pursuit of improving performance of the photolithographic process.
• MOSFET metal-oxide-semiconductor field-effect transistors
• PMOS p-channel MOS
• NMOS n-channel MOS
• CMOS complementary MOS
• BiCMOS transistors bipolar transistors
• IGFETs insulated-gate FET
• Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed.
• the particular structure of a given active device can vary between device types.
• an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions.
• photolithography a wafer substrate is coated with a light-sensitive material called photo-resist.
• photo-resist a light-sensitive material
• the wafer is exposed to light; the light striking the wafer is passed through a mask plate.
• This mask plate defines the desired features to be printed on the substrate.
• the resist- coated wafer substrate is developed.
• the desired features as defined on the mask are retained on the photo resist-coated substrate. Unexposed areas of resist are washed away with a developer.
• the wafer having the desired features defined is subjected to etching.
• the etching may either be a wet etch, in which liquid chemicals are used to remove wafer material or a dry etch, in which wafer material is subjected to a radio frequency (RF) induced plasma.
• RF radio frequency
• Often desired features have particular regions in which the final printed and etched regions have to be accurately reproduced over time. These are referred to as critical dimensions (CDs).
• CDs critical dimensions
• wafer fabrication becomes more reliant on maintaining consistent CDs over normal process variations.
• the active device dimensions as designed and replicated on the photo mask and those actually rendered on the wafer substrate have to be repeatable and controllable.
• the process attempts to maintain the final CDs equal to the masking CDs.
• imperfections in the process or changes in technology that may be realized in a given fabrication process, if the process were "tweaked" often necessitate the rendering of final CDs that deviate from the masking CDs.
• wafers are exposed at a variety of conditions at one or more critical layers and then probed for yield. For example, it is common to quantify the effect of gate width on yield by exposing wafers at different doses to create a variety of linesizes. Typically, each wafer is exposed at a different exposure and perhaps, focus value. Since silicon and processing costs are expensive, it is desireable to obtain the same information on a wafer; that is, expose wafers with an array of doses and perhaps focuses.
• U.S. Patent 5,757,507 of Austent et al. relates generally to manufacturing processes requiring lithography and, more particularly, to monitoring of bias and overlay error in lithographic and etch processes used in microelectronics manufacturing which is particularly useful more monitoring pattern features with dimensions on the order of less than 0.5 ⁇ m.
• U.S. Patent 5,962,173 of Leroux et al. relates generally to the field of fabricating integrated circuits and more particularly to maintaining accuracy in the fabrication of such circuits having extremely narrow line elements such as gate lines.
• U.S. Patent 5,902, 703 of Leroux et al. relates generally to the field of fabricating integrated circuits and more particularly to maintaining accuracy in the fabrication of such circuits having relatively narrow line elements such as gate lines.
• the invention is also directed to the verification of stepper lens fabrication quality.
• U.S. Patent 5,976,741 of Ziger et al. relates generally to methods of determining illumination exposure dosages and other processing parameters in the field of fabricating integrated circuits. More particularly, the invention concerns methods of processing semiconductor wafers in step and repeat systems.
• U.S. Patent 6,301,008 Bl of Ziger et al. relates to semiconductor devices and their manufacture, and more particularly, to arrangements and processes for developing relatively narrow line widths of elements such as gate lines, while maintaining accuracy in their fabrication.
• U.S. Patent Application US 2002/0182516 Al of Bowes relates generally to metrology of semiconductor manufacturing processes. More particularly, the present invention is a needle comb reticle pattern for simultaneously making critical dimension (CD) measurements of device features and registration measurements of mask overlays relative to semiconductor wafers during processing of semiconductor wafers.
• CD critical dimension
• This reference and those previously cited are herein incorporated by reference in their entirety.
• data is obtained by exposing an array of exposure doses (or focuses) on different columns or rows of dies on a wafer substrate. .
• dies are printed at multiple exposure doses. Each column of die may be exposed at particular exposure dose. As the user steps across the wafer the exposure dose may be increased. .
• Sort maps are die-by-die plots across the wafer substrate having active devices of electrical measurements performed on a completed wafer having active devices (e.g, "wafer sort").
• Sort maps are electrical test results of die tested on a wafer, these die may comprise electrical test patterns and circuits or may be devices that have end-user applications, for example, memory devices, microprocessors, microcontrollers, amplifiers, application specific integrated circuits (ASICS), etc. Furthermore, such devices may be digital or analog devices produced in a number of wafer fabrication processes, for example, CMOS, BiCMOS, Bipolar, etc.
• the substrates may be silicon, gallium arsenide (GaAs) or other substrate suitable for building microelectronic circuits thereon.
• a given wafer substrate with a particular example product will exhibit sort maps characteristic of the processing the wafer substrate received in its fabrication. Correlation between sort and stepper maps becomes more difficult as the number of chips per wafer increase. Additionally, stepper maps can be intentionally offset in either or both the horizontal and vertical directions further complicating the correlation of the two maps. Thus, there is a need for a method to address two challenges of exposure characterization at the wafer level, the confounding of yield with systemic defects and the alignment of exposure fields with yield maps.
• a method for manufacturing a wafer having a substrate comprises randomly assigning numbers to exposure fields for the substrate. Using the randomly assigning numbers, exposure parameters are assigned to the respective exposure fields. The wafers are processed according to the assigned exposure parameters.
• there is a method for randomizing exposure conditions across a substrate that comprises generating a list of random numbers.
• a random number is mapped to an exposure field.
• a list of random numbers and corresponding exposure fields is formed and is sorted by random number.
• An exposure does is assigned to each exposure field in the listed sorted by random number and the list is sorted by exposure field.
• a feature of this embodiment is that the exposure field may be printed at the assigned exposure dose.
• a method for characterizing lithography effects on a wafer comprises determining an effect to study and determimng a number of exposure fields to print. At least one reference die location is selected. A randomization procedure is performed. The reference die is printed at an exposure to make the reference die conspicuous. Each exposure field is printed at the assigned exposure dose. Electrical measurements are performed on the wafer and electrical measurements are correlated with line width.
• a system characterizes lithography effects on a wafer.
• the system comprises means for generating a list of random numbers, means for mapping a random number to an exposure field, forming a list of random numbers and corresponding exposure fields.
• a feature of this embodiment further comprises means for selecting at least one reference die location and means for printing the reference die at an exposure to make the reference die conspicuous.
• FIG. 1 outlines the steps involved in printing exposure doses according to an embodiment of the present invention
• FIG.2 A illustrates an example line width map of a substrate exposed to characterize polysilicon gate width effects versus yield according to an embodiment of the present invention
• FIG. 2B in an example process according to the present invention, depicts the correlation between electrical measurements of polysilicon CD v. inline scanning electron microscope (SEM) CD measurements;
• FIG.2C of the example process depicts the threshold voltage (V t ) roll off curve as a function of polysilicon line width
• FIG.2D of the example process shows the relative yield as a function of line width for five different poly-silicon lithography processes.
• FIG. 3 outlines the steps in involved in obtaining the data in an example process, as depicted in FIGS. 2 A - 2D, according to an embodiment of the present invention
• the present invention has been found to be useful in overcoming two challenges the user may encounter in performing exposure characterizations at the wafer level, namely confounding yield with systemic defects in which the user cannot discern and correlate a particular systemic wafer-to-wafer yield variation and the alignment of exposure fields with yield maps, in which the user may correlate a particular exposure field with yield.
• Yield would be the number of product or test die successfully passing electrical testing. Often yield may be expressed as a percentage of good die versus the number of die tested.
• an approach according to an embodiment of the present invention is to randomize exposure conditions across the wafer. Refer to FIG. 1.
• One example method is to generate a list of random numbers 210.
• a random number is assigned to each exposure field 220.
• the list of exposure fields/random numbers is sorted by random number 230.
• Exposure doses are assigned to this List sorted by random number 240.
• the list is sorted again by exposure field 250.
• Each Exposure Field is printed at an assigned dose 260.
• a group of 21 stepper shots has random numbers assigned to each shot.
• Random numbers may be generated by a number of methods that are well known. They may be generated manually through the use of random number tables or be done in a data processing system that includes computers or calculating apparatus.
• Software routines may be utilized to generate the requisite list of random numbers. Such routines may be present on a standalone computer or via a network of client/server computers. Refer to Table 1 for the case of 21 exposure fields. The Table 1 list is sorted by random number.
• Table 2 Refer to Table 2. .
• Seven levels of exposure doses are desired with three replicates of the same exposure conditions (e.g. same dose, focus, etc). The seven exposure doses are assigned to the 21 shots in groups of 3
• the list of Table 2 then is sorted by stepper shot to provide the randomized shot by dose assignment.
• fields can be excluded from the randomization list if they are systematically different. For example, some fields are only partially on the wafer and could systematically yield differently from interior fields due to focus effects.
• the challenge of aligning the stepper map to the wafer sort or parameter test (pTest) map may be addressed by intentionally rendering one off center stepper field much different than the others in such a way that the wafer sort or pTest maps explicitly thereby, determining the correspondence.
• Parameter tests may include the testing of representative components of a device at various stages in the device's fabrication. Such tests may include but are not limited to transistors, resistors, diodes, contact and via chains, etc. Simple circuits, such as ring oscillators, memory modules, etc. may be built from the transistors and other representative components. For example, at a potentially critical polysilicon layer, one field can be severely overexposed causing all die in that field to exhibit extraordinary leakage current.
• Wafer map 300 shows an example of line widths measured across a wafer intended to characterize the effect of line width on yield. Note that the reference die 310 is about 0.1 O ⁇ m smaller than the next smallest line width, the dimensions being about 0.279 ⁇ m.
• Fig. 2B shows the correlation between electrical and inline SEM measurements.
• the plot 320 is depicts a curve 325 of SEM poly CD measurements versus the deviation of the how such a SEM measurement behaves electrically. A deviation of zero means that the physical poly CD measurements exactly correlate with the electrical poly CD measurement.
• Plot 330 depicts a plot of the poly silicon CD v. threshold voltage roll off 335.
• characterizing the effect of alignment at multiple levels using randomized exposure conditions may be applied. For example, a study may be done with poly-silicon and metallization in a combination experiment. These characterizations may illustrate a statistically based framework for doing and analyzing lithography experiments across individual wafers.
• the user may follow the process 400 to fabricate a characterization wafer, as shown by example of FIG. 2 A.
• the user in his or her experience in a given wafer fabrication process may be encountering loss of wafers with a concomitant increase in cost at a particular step in a complex modern sub-micron process.
• the process may be undergoing challenges in the area of printing features in the poly-silicon layer of an example CMOS process.
• the user determines an effect to study 410.
• the number of die sites to print has to be determined 420. Usually, the number of sites to print has already been defined by the production die already in the line.
• one or more reference die locations are selected 430.
• a randomization procedure is performed 440.
• the user may follow randomization procedure 205 outlined in FIG. 1. Having done the randomization procedure 440, the user may choose to print the reference die(s) at an exposure to make them conspicuous 450 (i.e., detectable by electrical testing). After printing the reference die(s), each exposure field is printed at an assigned dose 460.
• the poly-silicon leakage as discussed in relation to FIG. 2A correlates strongly to leakage current.
• One or more reference dies are usually printed in an off-center position. The reference dies may be printed at four quadrants of the wafer.
• the particular yield limiting issue and process often guides the user as to the appropriate number and placement of reference dies.
• This approach of using a single wafer overcomes a challenge of one wafer at a time characterization, is that it is insensitive to wafer-to- wafer effects. For example, if an unrelated defect issue affects a single wafer exposed at a particular dose, then yield loss may be incorrectly attributed to the line widths printed on that particular wafer. Also, by randomizing, the effects of systematic across wafer effects on yield are reduced. Finally, this approach uses fewer wafers than the standard one wafer-at-a-time characterization.
• the present invention may be incorporated as an additional feature to wafer stepping equipment.
• Such equipment of often computer-controlled and the user may program complex routines for production, test, and characterization.
• a wafer stepper may have a routine for characterizing a wafer substrate during a given process.
• specific procedures may be programmed into the computer controlling the stepper.
• the characterization program may reside in program memory, optical, magnetic storage, or may reside in a client/server configuration as part of an internal intranet or the Internet.
• a sample substrate out of a run of 25, may be designated for test.
• the user enters into the computer controlling the wafer stepper the effects he or she wants to study.
• the computer generates a list of which die sites to print for a given mask and wafer combination.
• the computer selects reference die locations.
• the computer performs a randomization procedure. Having selected the randomization of the die location and the selecting of reference die locations, the computer commands the wafer stepper to print the die at an assigned exposure parameter.

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• 2004
  • 2004-04-27 US US10/554,791 patent/US7537939B2/en active Active
  • 2004-04-27 EP EP04729689A patent/EP1627258A2/de not_active Ceased
  • 2004-04-27 JP JP2006506530A patent/JP2007528114A/ja active Pending
  • 2004-04-27 CN CN2004800115902A patent/CN1882883B/zh not_active Expired - Fee Related
  • 2004-04-27 WO PCT/IB2004/001267 patent/WO2004097528A2/en active Application Filing

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