EP1590751A2 - Detection de proprietes (verification formelle) pour un systeme mixte constitue de sous systemes analogiques et numeriques - Google Patents

Detection de proprietes (verification formelle) pour un systeme mixte constitue de sous systemes analogiques et numeriques

Info

Publication number
EP1590751A2
EP1590751A2 EP04708308A EP04708308A EP1590751A2 EP 1590751 A2 EP1590751 A2 EP 1590751A2 EP 04708308 A EP04708308 A EP 04708308A EP 04708308 A EP04708308 A EP 04708308A EP 1590751 A2 EP1590751 A2 EP 1590751A2
Authority
EP
European Patent Office
Prior art keywords
digital
analog
time
properties
model
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04708308A
Other languages
German (de)
English (en)
Inventor
Christian Lang
Roland Syba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Melexis GmbH
Original Assignee
Melexis GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Melexis GmbH filed Critical Melexis GmbH
Publication of EP1590751A2 publication Critical patent/EP1590751A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning

Definitions

  • the invention relates to a method for detecting properties of a technical system with digital and analog components. A "formal verification" is used.
  • a simplified proof of properties of an analog-digital mixed signal system (digital and analog components) is to be carried out using a model replacement system (model).
  • the replacement system is characterized by:
  • a digital replacement model depicts the analog circuits, as already described in the prior art, cf. Lang, loc. Cit., Page 26, top and page 27, second paragraph.
  • the parameters for the analog components are also shown in the digital replacement model.
  • the analog components are grouped so that each group forms a time-independent system or a time-dependent system. These groups are treated differently. One is stateless and is replaced by combinatorial logic. The other group is replaced by finite automata. Both will be transferred to digital replacement systems. One or more of the respective type can be present from the groups (claim 5).
  • Digitization errors can be assumed, but there is still a reliable conclusion from the results of the verification of the described replacement model on the original system.
  • the original system is the real system with analog and digital components.
  • the "properties to be verified" are equally the given properties, which are to be proven, but which are also given as properties that correspond to the mathematical sentences described (requirements and claims).
  • a tightening is a reduction of the allowed value range of the analog signals.
  • a double amount of the maximum digitization error is preferably provided here, which determines the tightening.
  • the reference model (the template or the properties to be verified); the replacement model, which is verified and also
  • FIG. 1 shows functions by restricting the permitted value range a for analog signals by twice the maximum digitization error ⁇ to a '.
  • FIG. 2 shows a reference model 10 and a digital-analog one
  • the starting point of the described method is a reference model 10 and a digital-analog mixed signal system 1, as symbolically shown in FIG. 2.
  • the digital-analog mixed signal system 1 is a technical system, preferably an electronic circuit, which has inputs and outputs and consists of analog and digital components.
  • the reference model 10 is a sum of properties.
  • a “property” defines a predetermined (or: to be verified) signal sequence at the outputs of the digital-analog mixed signal system 1 for a specific signal sequence at its inputs.
  • the aim of the method is the verification result 100, which indicates whether the properties of the reference model 10 in the digital-analog mixed signal system 1 are fulfilled.
  • a fulfillment is a (positive) verification.
  • the digital-analog mixing system is converted into a digital replacement model 20.
  • the analog components of the digital-analog mixing system 1 are grouped into time-independent subsystems 2 and / or into (linear) time-dependent subsystems 3 (functionally broken down or structured), in step 90. These subsystems are replaced by combinatorial logic 2a (not shown in the figures) or by finite automatons 3a.
  • These digitized subsystems 2, 3 together with the digital components 4 of the digital-analog mixing system form the digital replacement model 20.
  • Digitization error 11 designated.
  • the properties described in the reference model 10 are tightened in a method step 92, for example by permitting
  • Range of values of the signals described in the properties is restricted, as shown in FIG. 1.
  • the result of this tightening 92 is a tightened reference model 10a.
  • the tightened reference model 10a is compared to the digital replacement model with the known methods 95 of "formal verification", cf. Bormann “Formal verification becomes a craft” loc. and WO-A 99/50766 (Bormann, Siemens AG), compared or verified.
  • the result of the verification is the verification result 100.
  • the method described above ensures that the verification result shows whether the properties of the reference model 10 in the digital-analog mixed-signal system are met when the tightened model 10a is used instead of the regular property description by the Reference model 10.
  • a replacement system 20 is characterized by:
  • the original system is broken down into time-independent and time-dependent subsystems, in method step 90.
  • the time-independent subsystems 2 are distinguished by the fact that all dynamic transition processes have subsided within one clock period of the digital replacement model 20. These subsystems can be considered stateless and are modeled by combinatorial logic. It is also that
  • Digitization of such non-linear systems is possible without problems using appropriate numerical approximations. So they can be linear or non-linear.
  • time-dependent systems dynamic transitions over several clock periods of the digital replacement model 20 have an effect.
  • These systems can be represented by finite automatons 3a in the replacement model.
  • linear analog systems closed theory for the digitization of these systems.
  • time-dependent systems that are non-linear, the way will be labeled to linearize them, for example around an operating point, or to divide these systems into non-linear time-independent systems (eg delimiters) and linear time-dependent systems.
  • non-linear time-independent systems eg delimiters
  • linear time-dependent systems eg delimiters
  • An error in the time discretization can be determined by comparing the frequency responses of the analog original system 1 and the digital replacement model.
  • the error of the time discretization can be reduced by choosing a clock frequency of the digital replacement model 20.
  • the replacement of the analog components in the digitized replacement model 20 is not without errors, e.g. because of a quantization of the analog signals or its
  • the analog-digital mixed signal system 1 also becomes these Fulfill properties. This is achieved by restricting the permitted value range "a" for analog signals y (t) by (at least) twice the amount 2 ⁇ of the maximum digitization error ⁇ , see FIG. 1. This results in a sharper property a 'as a-2 ⁇ .
  • the digitization error is reduced by an increased accuracy in the digitization of the analog-digital mixed signal system. This can include can be achieved by a more precise quantization of the analog signals or by a higher clock frequency of the replacement model 20. This means that the permitted range of values no longer has to be restricted as much.
  • the accuracy of the digitization can be increased until the verification of the digital

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention concerne un procédé pour détecter des propriétés d'un système à signaux mixtes numériques-analogiques (1) par vérification formelle d'un système de substitution numérique (20). Des paramètres de composants et d'environnement sont représentés pour les composants analogiques en tant que signaux supplémentaires dans le modèle de substitution numérique (modèle de substitution numérique, 20) et la partie analogique du système est divisée en sous-systèmes indépendant du temps et sous-systèmes dépendant du temps linéaires (90). Les sous-systèmes indépendant du temps sont considérés comme sans état et remplacés par une logique combinatoire, tandis que les sous-systèmes dépendant du temps linéaires servant à la discrétisation temporelle sont remplacés par des automates finis, la logique combinatoire et les automates finis étant ensuite transférés dans des systèmes de substitution numériques. En dépit des erreurs de numérisation, il est possible d'obtenir des informations sûres concernant le système original à partir des résultats de vérification du système de substitution. La détection des propriétés du système à signaux mixtes numériques-analogiques (1) est rendue plus rigoureuse pour les composants analogiques de sorte que, même en présence de toutes les valeurs des erreurs de numérisation, les conditions pour ces propriétés sont réunies dans le modèle de substitution numérique uniquement lorsque le système à signaux mixtes numériques-analogiques (1) réunit également les conditions pour ces propriétés. A cet effet, la plage de valeurs autorisée pour les signaux analogiques est limitée au moyen d'une valeur correspondant au double de l'erreur de numérisation maximale (92).
EP04708308A 2003-02-05 2004-02-05 Detection de proprietes (verification formelle) pour un systeme mixte constitue de sous systemes analogiques et numeriques Withdrawn EP1590751A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10304569 2003-02-05
DE10304569A DE10304569B4 (de) 2003-02-05 2003-02-05 Verfahren zum Nachweis von Eigenschaften eines aus analogen und digitalen Teilsystemen bestehenden technischen Systems
PCT/DE2004/000193 WO2004070632A2 (fr) 2003-02-05 2004-02-05 Detection de proprietes (verification formelle) pour un systeme mixte constitue de sous systemes analogiques et numeriques

Publications (1)

Publication Number Publication Date
EP1590751A2 true EP1590751A2 (fr) 2005-11-02

Family

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EP04708308A Withdrawn EP1590751A2 (fr) 2003-02-05 2004-02-05 Detection de proprietes (verification formelle) pour un systeme mixte constitue de sous systemes analogiques et numeriques

Country Status (4)

Country Link
US (1) US20060215743A1 (fr)
EP (1) EP1590751A2 (fr)
DE (1) DE10304569B4 (fr)
WO (1) WO2004070632A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7376929B1 (en) 2004-11-10 2008-05-20 Xilinx, Inc. Method and apparatus for providing a protection circuit for protecting an integrated circuit design
US7814336B1 (en) 2005-07-12 2010-10-12 Xilinx, Inc. Method and apparatus for protection of time-limited operation of a circuit
DE102006031027A1 (de) * 2006-07-05 2008-01-24 Atmel Germany Gmbh Verfahren zur Funktionskontrolle von wenigstens einem analogen Schaltungsblock
US11334702B1 (en) * 2021-02-11 2022-05-17 Siemens Industry Software Inc. Mixed-signal simulation for complex design topologies

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4044732B2 (ja) * 1998-03-30 2008-02-06 ワンスピン ソリューションズ ゲゼルシャフト ミット ベシュレンクテル ハフツング 電気回路の比較方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "Combinational Logic", WIKIPEDIA, 24 November 2002 (2002-11-24), pages 1 - 1, Retrieved from the Internet <URL:http://en.wikipedia.org/w/index.php?title=Combinational_logic&oldid=1548496> [retrieved on 20080303] *

Also Published As

Publication number Publication date
US20060215743A1 (en) 2006-09-28
WO2004070632A2 (fr) 2004-08-19
DE10304569B4 (de) 2007-05-10
DE10304569A1 (de) 2004-08-26
WO2004070632A3 (fr) 2005-01-06

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