EP1581966A2 - Method for the production of a semiconductor component - Google Patents
Method for the production of a semiconductor componentInfo
- Publication number
- EP1581966A2 EP1581966A2 EP03799455A EP03799455A EP1581966A2 EP 1581966 A2 EP1581966 A2 EP 1581966A2 EP 03799455 A EP03799455 A EP 03799455A EP 03799455 A EP03799455 A EP 03799455A EP 1581966 A2 EP1581966 A2 EP 1581966A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- component
- lateral
- power component
- insulation
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000009413 insulation Methods 0.000 claims abstract description 26
- 238000001465 metallisation Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 1
- 239000011810 insulating material Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- 230000010354 integration Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000012549 training Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Definitions
- the invention relates to a method for producing a semiconductor component which has a first vertical power component and at least one lateral, active component and / or at least a second vertical component, and a semiconductor component which can be produced using the method.
- Monolithic integration is a manufacturing process for microchips in which the various components do not have to be individually adjusted and glued on, but the entire chip is made from one piece. In addition to the lower adjustment effort, such systems are extremely robust.
- the monolithic integration of the aforementioned power components is implemented in different ways depending on the respective voltage class.
- So-called smart power processes such as BCDMOS are used for voltages up to a few 100 V.
- the different regions are separated laterally either by doping regions or by dielectric isolation.
- the power component is usually insulated from the control circuit by a pn junction.
- a pn junction is that a thyristor structure exists between the source-drain zones of the n-channel transistor and the source-drain zones of the p-channel transistor, which can ignite and thus the functionality of the inverter reduced or leads to the destruction of the component.
- This undesirable effect is called The term "latch-up effect" refers to.
- a fundamental disadvantage of SOI technology is that an undesirable control effect of the substrate cannot be avoided.
- the substrate acts via the buried insulator like a second gate electrode on transistors, which is integrated in a layer. If potential differences occur between the substrate and the corresponding layer, this can lead to threshold voltage shifts and to changes in the switching state of the transistors.
- DE 42 01 910 AI describes a method for producing a Integrated circuit with at least two vertical power components, in which influences of switching operations of a vertical power component on a control circuit or on a second vertical power component are to be largely avoided.
- the semiconductor component described in this publication is essentially characterized in that the control circuit is located above a rear etching recess and is delimited from the etching recess by an etching stop layer.
- the control circuit is also isolated in the lateral direction from the power components by LOCOS insulation.
- a disadvantage of the power component described in this publication is that a large amount of silicon area is required for the lateral insulation regions when it is produced and, on the other hand, the semiconductor component is not suitable for higher voltage classes due to this type of insulation.
- the object of the invention is to specify a semiconductor component and a method for its production which enable inexpensive integration of a vertical power component and a lateral, active component and / or further vertical power components.
- a component that solves the aforementioned task to also integrate power components of higher voltage classes on the semiconductor component.
- the object is achieved with the method according to claim 1 and the semiconductor component according to claim 10.
- a method for producing a semiconductor component which has a first vertical power component and at least one lateral, active component and / or at least a second vertical power component, with the steps:
- the method according to the invention thus makes it possible to integrate a plurality of vertical power components as well as lateral, active components on one semiconductor component.
- the electrical insulation of the various components is achieved by first etching trenches in the silicon wafer, which are filled with a dielectric.
- the depth of the trenches is set so that it corresponds to the wafer thickness after the thinning process.
- One or more trenches can be used to isolate the individual components.
- the first power component, the at least one lateral becomes active
- Component and / or the at least one second vertical power component is approximately ring-shaped and / or disk-shaped.
- the lateral, active component is disc-shaped and arranged on the front side in such a way that it is completely surrounded by the trench in the first power component.
- the inner surface of the semiconductor component containing laterally active components and the power components can be arranged outwards in rings around the laterally active component.
- a dielectric is deposited on the back of the substrate.
- the dielectric serves for the complete electrical decoupling of the wafer substrate.
- the dielectric is opened in a subsequent process step at the appropriate locations for rear-side metallization.
- At least one trench which completely surrounds at least a partial area of the front side, is preferably etched into the surface.
- the depth of the at least one trench is set such that it corresponds to the wafer thickness after the thinning process. For reasons of lateral field distribution, combinations of a dielectric with doped polysilicon are also conceivable as filling the trenches.
- a multiplicity of vertical power components and lateral, active components are arranged on a silicon substrate such that they are arranged concentrically or eccentrically around a common reference point on the substrate and in each case by a Trench, which was produced by the aforementioned method, are isolated from each other.
- the contacting of the one or more power components is preferably carried out with the following steps:
- the applied metallization is structured in a special training.
- a further, particularly suitable embodiment provides for the at least one lateral, active one
- the at least one lateral, active component is preferably arranged in a p-doped well.
- the semiconductor component according to the invention has at least one first vertical power component and at least one lateral, active component and / or at least one second vertical power component, between which at least one with a Insulation filled trench is arranged.
- the semiconductor component described is characterized in that the insulation at least partially has a dielectric and that the at least one vertical power component and the at least one lateral, active component have an approximately annular and / or disk-shaped configuration and are concentric or eccentric around a common reference point on a Silicon substrate are arranged.
- the aforementioned semiconductor component enables the integration of a plurality of vertical power components and lateral, active components on one component. It is also a significant advantage of the semiconductor component according to the invention that vertical and lateral, active components are arranged on a component in a particularly space-saving manner.
- Power components for voltages of up to 1700 V are preferably used in the semiconductor component according to the invention.
- the voltage classes vary between 600 and 1700 V. It is therefore possible to use power MOS components in a voltage class of 100 to 200 V, IGBTs in a voltage class of up to 1700 V, preferably 600 to 1200 V, as a power component. or use diodes.
- the aforementioned power components In order to avoid high field strengths in the active area in the event of a blockage, the aforementioned power components always require an edge termination structure. This is the case for components for voltages up to 1200 V. Length of these edge seals, for example, up to 600 ⁇ m. If components in a conventional design were placed next to one another on a wafer and separated from one another by a conventional trench insulation, one would apply to each individual component
- the inventive, preferably concentric arrangement of the respective functional elements to be integrated on a semiconductor component greatly reduces the space required for the edge termination structures described above.
- this particularly suitable arrangement of the functional components considerably reduces the effort involved in contacting
- the power components are arranged in a ring shape on the outside.
- the at least one lateral, active component is preferably completely surrounded by at least one filled trench and a vertical power component.
- Wafer backside are decoupled, a further, special embodiment provides to arrange the at least one lateral, active component in a doped trough.
- the dielectric preferably provides corresponding openings for contacting the power components from the rear.
- Fig. 2 shows a concentric arrangement of the
- the electrical isolation of the various components is achieved by first etching trenches 2 in the silicon substrate 1 become.
- the trenches 2 are filled with a dielectric or a combination of a dielectric with polysilicon as the insulation layer 4.
- the silicon substrate 1 is thinned from the back to the trench bottom 3 of the silicon Substrate 1 etched trench 2. In this way, the insulation layer 4 filled in the trenches 2 is exposed from the back.
- the depth of the trenches 2 is set such that it corresponds to the wafer thickness after the thinning process.
- the respective function elements 5, 6 are arranged concentrically and separately on a substrate by trench insulation 4.
- the functional elements 5, 6 could also be arranged eccentrically.
- the inner surface of the chip contains laterally, active components 6, such as components designed in bipolar, CMOS, NMOS or PMOS technology.
- the power components 5, such as IGBTs and / or diodes, are arranged in a ring around the lateral, active component 6.
- both power components 5 and / or a lateral, active component 6 in such rings around a centrally arranged and disk-shaped functional element.
- FIG. 3 shows a sectional view through a semiconductor component according to the invention.
- An IGBT 9, a diode 10 and a lateral, active component 6 are arranged on the semiconductor component, which are separated from each other in an electrically insulating manner by trench insulation 4.
- On the front is a large number of front contacts
- the lateral, active component 6 is also in a doping trough
- a dielectric 13 is applied to the back after thinning the wafer substrates. As can be seen in FIG. 3b, the dielectric 13 is opened for the rear-side contacting of the power components 6 at the corresponding locations for the rear-side metallization 8, which is finally applied on the rear side of the semiconductor component.
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10300577 | 2003-01-10 | ||
DE10300577A DE10300577B4 (en) | 2003-01-10 | 2003-01-10 | Semiconductor device with vertical power device comprising a separation trench and method for its preparation |
PCT/DE2003/004286 WO2004064123A2 (en) | 2003-01-10 | 2003-12-23 | Method for the production of a semiconductor component |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1581966A2 true EP1581966A2 (en) | 2005-10-05 |
Family
ID=32519783
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03799455A Withdrawn EP1581966A2 (en) | 2003-01-10 | 2003-12-23 | Method for the production of a semiconductor component |
Country Status (7)
Country | Link |
---|---|
US (1) | US7719077B2 (en) |
EP (1) | EP1581966A2 (en) |
JP (1) | JP4718187B2 (en) |
AU (1) | AU2003299284A1 (en) |
CA (1) | CA2511842C (en) |
DE (1) | DE10300577B4 (en) |
WO (1) | WO2004064123A2 (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007317839A (en) * | 2006-05-25 | 2007-12-06 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
JP5217348B2 (en) * | 2006-12-06 | 2013-06-19 | 株式会社デンソー | Semiconductor device |
US8362494B2 (en) * | 2007-08-08 | 2013-01-29 | Agency For Science, Technology And Research | Electro-optic device with novel insulating structure and a method for manufacturing the same |
EP2031653B1 (en) * | 2007-08-27 | 2014-03-05 | Denso Corporation | Manufacturing method for a semiconductor device having multiple element formation regions |
US7911023B2 (en) * | 2007-11-06 | 2011-03-22 | Denso Corporation | Semiconductor apparatus including a double-sided electrode element and method for manufacturing the same |
JP4678547B2 (en) * | 2007-11-06 | 2011-04-27 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
US8125002B2 (en) * | 2007-11-07 | 2012-02-28 | Denso Corporation | Semiconductor device and inverter circuit having the same |
JP4577425B2 (en) * | 2007-11-07 | 2010-11-10 | 株式会社デンソー | Semiconductor device |
JP4737255B2 (en) * | 2007-11-20 | 2011-07-27 | 株式会社デンソー | Semiconductor device using SOI substrate |
US8278731B2 (en) * | 2007-11-20 | 2012-10-02 | Denso Corporation | Semiconductor device having SOI substrate and method for manufacturing the same |
JP5444648B2 (en) * | 2008-07-03 | 2014-03-19 | 富士電機株式会社 | Manufacturing method of semiconductor device |
US7989282B2 (en) * | 2009-03-26 | 2011-08-02 | International Business Machines Corporation | Structure and method for latchup improvement using through wafer via latchup guard ring |
US20110260245A1 (en) * | 2010-04-23 | 2011-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cost Effective Global Isolation and Power Dissipation For Power Integrated Circuit Device |
US9142665B2 (en) | 2010-12-10 | 2015-09-22 | Infineon Technologies Austria Ag | Semiconductor component with a semiconductor via |
US9396997B2 (en) * | 2010-12-10 | 2016-07-19 | Infineon Technologies Ag | Method for producing a semiconductor component with insulated semiconductor mesas |
EP2887387A1 (en) * | 2013-12-20 | 2015-06-24 | Nxp B.V. | Semiconductor device and associated method |
US10546816B2 (en) * | 2015-12-10 | 2020-01-28 | Nexperia B.V. | Semiconductor substrate with electrically isolating dielectric partition |
JP6795032B2 (en) | 2016-06-03 | 2020-12-02 | 富士電機株式会社 | Semiconductor device |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4860081A (en) * | 1984-06-28 | 1989-08-22 | Gte Laboratories Incorporated | Semiconductor integrated circuit structure with insulative partitions |
US5294825A (en) * | 1987-02-26 | 1994-03-15 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
JP2788269B2 (en) | 1988-02-08 | 1998-08-20 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US5512774A (en) * | 1988-02-08 | 1996-04-30 | Kabushiki Kaisha Toshiba | Dielectrically isolated substrate and semiconductor device using the same |
DE4201910C2 (en) * | 1991-11-29 | 1995-05-11 | Fraunhofer Ges Forschung | Method for producing a semiconductor structure for an integrated power circuit with a vertical power component |
JP3014012B2 (en) * | 1992-03-19 | 2000-02-28 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JP3299374B2 (en) * | 1994-02-24 | 2002-07-08 | 三菱電機株式会社 | Thyristor and manufacturing method thereof |
US5981983A (en) * | 1996-09-18 | 1999-11-09 | Kabushiki Kaisha Toshiba | High voltage semiconductor device |
KR100218538B1 (en) * | 1996-10-17 | 1999-09-01 | 김덕중 | Semiconductor substrate and making method thereof |
US5909626A (en) * | 1997-03-28 | 1999-06-01 | Nec Corporation | SOI substrate and fabrication process therefor |
US6150697A (en) * | 1998-04-30 | 2000-11-21 | Denso Corporation | Semiconductor apparatus having high withstand voltage |
KR100281907B1 (en) * | 1998-10-29 | 2001-02-15 | 김덕중 | Intelligent power integrated circuits and methods of manufacturing the same |
EP1071133B1 (en) * | 1999-07-21 | 2010-04-21 | STMicroelectronics Srl | Process for CMOS devices of non volatile memories and vertical bipolar transistors with high gain. |
JP4631113B2 (en) * | 1999-10-26 | 2011-02-16 | 株式会社デンソー | Manufacturing method of semiconductor device |
US6524890B2 (en) * | 1999-11-17 | 2003-02-25 | Denso Corporation | Method for manufacturing semiconductor device having element isolation structure |
-
2003
- 2003-01-10 DE DE10300577A patent/DE10300577B4/en not_active Expired - Fee Related
- 2003-12-23 WO PCT/DE2003/004286 patent/WO2004064123A2/en active Application Filing
- 2003-12-23 EP EP03799455A patent/EP1581966A2/en not_active Withdrawn
- 2003-12-23 JP JP2004565915A patent/JP4718187B2/en not_active Expired - Fee Related
- 2003-12-23 AU AU2003299284A patent/AU2003299284A1/en not_active Abandoned
- 2003-12-23 US US10/541,819 patent/US7719077B2/en not_active Expired - Fee Related
- 2003-12-23 CA CA2511842A patent/CA2511842C/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
---|
See references of WO2004064123A2 * |
Also Published As
Publication number | Publication date |
---|---|
US7719077B2 (en) | 2010-05-18 |
WO2004064123A3 (en) | 2004-09-10 |
DE10300577B4 (en) | 2012-01-26 |
DE10300577A1 (en) | 2004-07-22 |
US20060172494A1 (en) | 2006-08-03 |
AU2003299284A1 (en) | 2004-08-10 |
CA2511842A1 (en) | 2004-07-29 |
CA2511842C (en) | 2014-02-04 |
AU2003299284A8 (en) | 2004-08-10 |
JP2006513563A (en) | 2006-04-20 |
WO2004064123A2 (en) | 2004-07-29 |
JP4718187B2 (en) | 2011-07-06 |
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