Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
  • H10W20/211—Through-semiconductor vias, e.g. TSVs
  • H10W20/216—Through-semiconductor vias, e.g. TSVs characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/65—Shapes or dispositions of interconnections
  • H10W70/652—Cross-sectional shapes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/019—Manufacture or treatment of bond pads
  • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/019—Manufacture or treatment of bond pads
  • H10W72/01951—Changing the shapes of bond pads
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/019—Manufacture or treatment of bond pads
  • H10W72/01951—Changing the shapes of bond pads
  • H10W72/01953—Changing the shapes of bond pads by etching
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
  • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/29—Bond pads specially adapted therefor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/921—Structures or relative sizes of bond pads
  • H10W72/922—Bond pads being integral with underlying chip-level interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/921—Structures or relative sizes of bond pads
  • H10W72/923—Bond pads having multiple stacked layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/951—Materials of bond pads
  • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/981—Auxiliary members, e.g. spacers
  • H10W72/983—Reinforcing structures, e.g. collars
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings

Definitions

• the present invention relates to a method of manufacturing a package the size of an electronic chip produced on the scale of the substrate (in English "Wafer Levai Chip Scale Package” or WLCSP).
• WLCSP Wafer Levai Chip Scale Package
• the package according to the invention will be called a chip-box.
• the invention also relates to a complex mold or stencil intended to produce said chip housing according to the method of the invention and also relates to said chip housing itself.
• the miniaturization of cases has become a vital need to meet market requirements, particularly with regard to the development of portable systems or telecommunications, but also to allow the increase in inputs / outputs of integrated circuits and to reduce the cost of packaging. .
• the dimensions of the electronic boxes must approach the dimensions of the integrated circuits (with the chip-box technology (“Chip Scale Package” in English or CSP) or the flip-chip technology, we get to have boxes with a dimension of 1 or 1.2 times the dimension of the circuit). It is also necessary that the weight of the box and the size of the connectors are reduced to the maximum in order to increase the number of inputs / outputs of the integrated circuits.
• the second failure is caused by the significant difference in thermal expansion between the housing and the receiving substrate (printed circuit).
• the large difference in thermal expansion will induce, in particular for ball housings, high stresses in the balls during temperature variations.
• these constraints can be high enough to break the connection balls.
• the miniaturization of the case therefore also requires an improvement in the reliability of the packaging.
• FIG. 1 presents a view in longitudinal section of a chip housing 1 produced according to the technique explained in document [1].
• a substrate 2 comprising integrated circuits whose input / output pads are referenced 3
• an insulating layer or passivation layer 4 To deposit said layer, one generally proceeds by spreading the spinner for polymers or by chemical vapor deposition for minerals. Then said insulating layer is opened, either by exposure of the polymer through a mask, or by lithography and etching (that is to say by deposition of a photosensitive resin, then exposure through a mask).
• the second problem relating to this manufacturing method is that, if the CSP boxes or chip boxes are mounted on the printed circuits without resin interposition (called “underfill” in the technique concerned), the connections will then be of low reliability: the Differences in thermal expansion between the CSP box and the printed circuit indeed induce stresses in the peripheral balls, especially if the integrated circuits are large.
• underfill in the technique concerned
• the problem is that the use of this resin is not necessarily desired depending on the applications and this generally adds at least one additional step.
• the use of this resin makes the repair of a component more delicate since it requires the replacement of a defective housing with a new one.
• the second innovative WLCSP box manufacturing process was presented by A. Kazama (see document [2] referenced at the end of this description).
• FIG. 2 A chip housing produced according to the technique of document [2] is illustrated in FIG. 2 in a view in longitudinal section.
• a WLCSP housing 11 comprising a substrate 12, integrated circuit pads 13 and a passivation layer 14.
• the difference compared to the previous document lies in the presence of thick blocks of polymer 18 between the face front of the substrate 12 and the fusible balls 17. It is these thick blocks of polymers which will make it possible to relax the constraints between the chip housing and the printed circuit.
• the rerouting of the input / output pads 13 is carried out by spraying a metal undercoat followed by electrolysis of Cu / Ni through a photosensitive resin. After removing the resin and the undercoat, the rerouting lines 15 are obtained; a photosensitive insulating layer 16 is then deposited using the spinning method or “spin coating” in English. This layer is then exposed through a mask in order to delimit the solder pads of the fusible balls 17. Finally, after the transfer fusible balls, the integrated circuits are singled out to obtain the chip-boxes.
• this method requires at least two lithography steps: a step to delimit the metal tracks and a step to open the passivation deposited on the metal tracks.
• the invention proposes a low-cost manufacturing method for a WLCSP package which makes it possible to integrate the packaging function of the integrated circuit on the scale of the substrate and which does not present the problems of the prior art.
• the process which is the subject of the invention consists in producing, using a mold or a stencil, a layer serving to release the stresses between the chip housing and the printed circuit, on which said chip housing will be connected, giving it a stepped shape allowing, thereafter, a rerouting of the inputs / outputs with fewer lithography steps than in the prior art, if at all.
• the method of producing a package the size of an electronic chip and produced on the scale of the substrate, said substrate comprising at least one chip and said at least one chip having input pads -outlet on one side of the substrate, called the front side comprises the following steps: a) forming, by means of a complex mold or stencil, an insulating layer of stress relaxation on said front side, said layer of relaxation covering the front face of the substrate with a relief having access wells at the level of the input-output pads, and elsewhere, projecting parts intended to relax the stresses, each projecting part having a stepped shape comprising at least a prominent area and at least one area, set back from said prominent area, intended to support an electrical connection pad, b) formation of electrically conductive tracks on the relaxation layer to connect er the input / output pads to the corresponding electrical connection pads, c) formation of electrical contact means towards the outside on the electrical connection pads.
• a layer of polymer instead of several blocks of polymer as in the prior art makes it possible to isolate the input / output pads
• the integrated circuits located on the substrate will include aluminum / copper or other input / output pads and a layer of mineral, organic passivation or both. These circuits may also have different finishes, for example, a chemical deposit of Ni / Au.
• said method further comprises, between steps b) and c) above, a step of forming an encapsulation layer on the relaxation layer with exposure of the electrical connection pads. stress relaxation layer can be achieved by different methods.
• said layer can be produced using a mold. For this, the following steps will be followed: 1) fill the mold with a determined relaxing polymer or apply said polymer directly to the front face of the substrate,
• said layer can this time be produced using a stencil.
• the following steps will then be followed: 1) apply the stencil to the front face of the substrate, 2) fill the holes in the stencil with a determined relaxing polymer, 3) anneal the polymer and separate the stencil from the substrate.
• the two actions are interchangeable: the polymer can be annealed in order to then separate the stencil from the substrate, but the stencil can also be separated, in certain cases, before annealing the polymer.
• said determined relaxing polymer used in the above embodiments will be chosen from the group consisting of polyimide, BCB or any other polymer capable of relaxing stresses.
• the rerouting step or step of forming electrically conductive tracks for connecting the input / output pads of the integrated circuits to the corresponding electrical connection pads is simplified by virtue of the complex topology of the relaxing layer created previously.
• this step of rerouting the inputs / outputs of the integrated circuits may not require a lithography step.
• the conductive material is a metal.
• the following sequence of steps can be followed: a) depositing a conductive material on the front face of the substrate covered with the relaxing layer, b) lithography, c) chemical etching, d) pickling, or alternatively the following steps: a) lithographic metallization of the front face of the substrate, b) electrolysis, c) pickling, d) chemical etching.
• the deposition of a conductive material which has been mentioned previously is a metallization.
• a metallization we will proceed by spraying, evaporation, electrodeposition or chemical deposition of one or more metals.
• the enclosures can be encapsulated in order to improve the service life.
• encapsulation can be total or partial.
• the step of forming an encapsulation layer comprises the following steps: a) deposition of a polymer layer over the entire front surface of the substrate covered with the relaxation layer, b) planarization from the front face of the substrate, c) release of the electrical connection pads.
• the step of forming an encapsulation layer comprises the following steps: a) planarization of the front face of the substrate covered with the relaxation layer, b) filling of the access shafts and recessed areas of the front face of the substrate with a thick polymer, c) release of the electrical connection pads.
• the electrical connection pads will be released by running in, by chemical mechanical polishing, by etching or by any other technique.
• planarization step of the front face of the substrate it is possible optionally to make cuts in the front face of the substrate, taking care not to entirely cut the relaxation layer. Then, an encapsulant is deposited on the rear face of the substrate and in the cutouts of the front face of the substrate. Under these conditions, the edges of the integrated circuits will also be protected near the cutting of the chip-boxes. Then, the electrical contact means must be installed outside on the electrical connection pads located on the relaxation layer.
• This step can be performed before or after planarization of the substrate, but it is preferable to perform it after planarization. In fact, planarization makes it possible to delimit the electrical connection pads.
• the means of electrical contact to the outside on the electrical connection pads will be fusible balls.
• the fusible balls will be installed on the electrical connection pads using a technique chosen from electrolysis of fusible alloy, screen printing of solder paste, transfer of balls or any other technique.
• these electrical contact means will be chosen from films and anisotropic conductive adhesives.
• This method of making WLCSP boxes can be completed by additional steps.
• the thickness of the enclosures may be reduced. For this, before or after installing the electrical contact means outwards on the electrical connection pads, the rear face of the substrate is thinned by running-in, by chemical mechanical polishing or any other technique.
• the thickness of the substrate can be reduced to 50 ⁇ m. One can even consider reducing it until reaching the active thickness of the silicon.
• the process can also be completed by the following steps: a) making trenches in the rear face of the substrate (by laser or chemical etching, by cutting or by any other technique) until reaching the metal layers represented by the studs input-output of integrated circuits or by electrically conductive tracks, b) deposit, possibly localized, of a metal layer (55) on the rear face of the substrate, c) elimination of metallization located on the surface of the rear face of the substrate .
• the invention also relates to a complex mold or stencil intended to produce a housing the size of a chip according to the method of the invention.
• this complex mold or stencil will be produced using at least one technique chosen from wet or dry etching, electroforming, bonding of several polymer films, pierced or not, molding, laser engraving or any other technique for performing complex topography.
• said mold or said stencil is made of silicon, metal, polymer or any other similar material. Note that the release of the parts is facilitated with molds or stencils in polymers.
• the invention also relates to a chip-sized package produced on the scale of the substrate, characterized in that it is produced by the method according to the invention.
• the method according to the invention has many advantages, in particular a reduction in the number of steps for producing the chip packages.
• the molding or poaching technique makes it possible at the same time to produce the topology necessary for rerouting the inputs / outputs and the layer making it possible to relax the thermomechanical constraints.
• Said mold or stencil also makes it possible to reduce the number of photolithography steps. Consequently, it reduces the number of total steps necessary for the manufacture of the chip package, and thereby reduces the manufacturing price of said package. Furthermore, once this mold or this stencil is made, it can be reused, which will also reduce the cost of manufacturing the boxes.
• FIGS. 1 and 2 illustrate the prior art presented previously in this description
• FIGS. 3a and 3b illustrate the topology of the complex mold ( FIG. 3a) and of the complex stencil (FIG. 3b) according to the invention
• FIGS. 4a to 4g illustrate a method of manufacturing WLCSP boxes according to the invention
• FIGS. 5a to 5c illustrate additional manufacturing to obtain complete encapsulation of the integrated circuit
• FIGS. 6a to 6g illustrate another method of manufacturing WLCSP packages according to the invention
• FIG. 7 illustrates the encapsulation of all the surfaces of the integrated circuit produced on the scale of the substrate.
• FIG. 4a A method of manufacturing a WLCSP package according to the present invention is illustrated in Figures 4a to 4g.
• step b the stress relaxation layer denoted 28 is produced on said substrate (FIG. 4b).
• This step is carried out either by molding the polymer on the substrate using a complex mold, or by screen printing of the polymer through a complex stencil on the substrate, or by transfer of the polymer (by making the polymer structure on another support using a mold or a complex stencil, which is then glued to the substrate).
• This step can be accompanied by a cleaning process (for example a plasma treatment) to remove the polymer residues on the input / output pads 23 of the integrated circuits.
• a cleaning process for example a plasma treatment
• this step can be completed by an electrodeposition of copper.
• This metallization step can also be carried out by chemical deposition of Ni / Au over the entire surface or by selective deposition (metallization located in access shafts and in recessed areas).
• the metal tracks must be isolated by eliminating the metallization on the surface (FIG. 4d). This step is carried out by chemical mechanical polishing, by etching or any other technique. Note that in the case of a localized chemical deposit, this step is not necessary.
• the metallization is preserved in the access wells to the studs and in all the areas set back from the machined upper surface of the relaxing layer. Then, the front face of the substrate is planarized by depositing an insulating layer denoted 29, for example by dispensing resin "underfill” which is planarized by spreading with a spinner or "spin coating” in English, by molding a polymer or by any other technique ( Figure 4e).
• this insulating layer is opened by plasma etching, by polishing or by any other technique to release the attachment studs 30 from the balls (FIG. 4f). Finally, the substrate is billed
• the last step consists in completely encapsulating the rear face of the substrate 22 and filling in the trenches made previously (FIG. 5c). This step can be carried out by molding, by exemption or any other technique of depositing insulation (noted 31).
• FIGS. 6a to 6g illustrate a second method of manufacturing the WLCSP package. This manufacturing method includes contact resumption front / rear face and the complete encapsulation of integrated circuits.
• each attachment pad 40 is surrounded by a trench to better define the weld zone.
• the same steps are carried out as those presented in FIGS. 4d to 4f and the device of FIG. 6b is obtained: the recessed areas and the access shafts above the input-output pads have been filled by deposition an insulating layer 49.
• the metallization step may be preceded by an etching step (for example by laser, by plasma, etc.) of the insulating layer at the pads.
• the metallizations 55 are isolated by lapping, by chemical mechanical polishing or by any other technique from the surface of the rear face of the substrate. This step can be carried out after an encapsulation step (step not drawn).
• the substrate is billed by placing the fusible balls 47 on the hooking pads 40 (FIG. 6f) and the singularization of the chip boxes (FIG. 6g) is carried out by cutting at the cutouts I.
• the substrate 72 includes integrated circuits composed of input / output pads 73 and a passivation layer 74; the integrated circuits are then covered with a layer 78 relieving the stresses and having access wells leaving the input / output pads 73 accessible, said input / output pads and the fusible balls 77 overhanging the relaxing layer 78 being connected by rerouting lines 75.
• An insulating layer 79 fills the access shafts and the recessed areas of the front face of the substrate, and a insulating layer 91 covers the rear face of the substrate.
• FIGS. 6g and 7 are not limiting, the two versions being able in particular to be coupled.

Landscapes

• Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
• Wire Bonding (AREA)

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• 2002
  • 2002-12-18 FR FR0216117A patent/FR2849270A1/fr active Pending
• 2003
  • 2003-12-17 EP EP03809999A patent/EP1573805A2/de not_active Withdrawn
  • 2003-12-17 WO PCT/FR2003/050188 patent/WO2004057667A2/fr not_active Ceased
  • 2003-12-17 US US10/538,889 patent/US20060128134A1/en not_active Abandoned

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