EP1573805A2 - Method for re-routing lithography-free microelectronic devices - Google Patents

Method for re-routing lithography-free microelectronic devices

Info

Publication number
EP1573805A2
EP1573805A2 EP03809999A EP03809999A EP1573805A2 EP 1573805 A2 EP1573805 A2 EP 1573805A2 EP 03809999 A EP03809999 A EP 03809999A EP 03809999 A EP03809999 A EP 03809999A EP 1573805 A2 EP1573805 A2 EP 1573805A2
Authority
EP
European Patent Office
Prior art keywords
substrate
manufacturing
layer
front face
polymer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03809999A
Other languages
German (de)
French (fr)
Inventor
François BALERAS
Fanny Delaguillaumie
Marc Zussy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1573805A2 publication Critical patent/EP1573805A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02321—Reworking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0236—Shape of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03602—Mechanical treatment, e.g. polishing, grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a method of manufacturing a package the size of an electronic chip produced on the scale of the substrate (in English "Wafer Levai Chip Scale Package” or WLCSP).
  • WLCSP Wafer Levai Chip Scale Package
  • the package according to the invention will be called a chip-box.
  • the invention also relates to a complex mold or stencil intended to produce said chip housing according to the method of the invention and also relates to said chip housing itself.
  • the miniaturization of cases has become a vital need to meet market requirements, particularly with regard to the development of portable systems or telecommunications, but also to allow the increase in inputs / outputs of integrated circuits and to reduce the cost of packaging. .
  • the dimensions of the electronic boxes must approach the dimensions of the integrated circuits (with the chip-box technology (“Chip Scale Package” in English or CSP) or the flip-chip technology, we get to have boxes with a dimension of 1 or 1.2 times the dimension of the circuit). It is also necessary that the weight of the box and the size of the connectors are reduced to the maximum in order to increase the number of inputs / outputs of the integrated circuits.
  • the second failure is caused by the significant difference in thermal expansion between the housing and the receiving substrate (printed circuit).
  • the large difference in thermal expansion will induce, in particular for ball housings, high stresses in the balls during temperature variations.
  • these constraints can be high enough to break the connection balls.
  • the miniaturization of the case therefore also requires an improvement in the reliability of the packaging.
  • FIG. 1 presents a view in longitudinal section of a chip housing 1 produced according to the technique explained in document [1].
  • a substrate 2 comprising integrated circuits whose input / output pads are referenced 3
  • an insulating layer or passivation layer 4 To deposit said layer, one generally proceeds by spreading the spinner for polymers or by chemical vapor deposition for minerals. Then said insulating layer is opened, either by exposure of the polymer through a mask, or by lithography and etching (that is to say by deposition of a photosensitive resin, then exposure through a mask).
  • the second problem relating to this manufacturing method is that, if the CSP boxes or chip boxes are mounted on the printed circuits without resin interposition (called “underfill” in the technique concerned), the connections will then be of low reliability: the Differences in thermal expansion between the CSP box and the printed circuit indeed induce stresses in the peripheral balls, especially if the integrated circuits are large.
  • underfill in the technique concerned
  • the problem is that the use of this resin is not necessarily desired depending on the applications and this generally adds at least one additional step.
  • the use of this resin makes the repair of a component more delicate since it requires the replacement of a defective housing with a new one.
  • the second innovative WLCSP box manufacturing process was presented by A. Kazama (see document [2] referenced at the end of this description).
  • FIG. 2 A chip housing produced according to the technique of document [2] is illustrated in FIG. 2 in a view in longitudinal section.
  • a WLCSP housing 11 comprising a substrate 12, integrated circuit pads 13 and a passivation layer 14.
  • the difference compared to the previous document lies in the presence of thick blocks of polymer 18 between the face front of the substrate 12 and the fusible balls 17. It is these thick blocks of polymers which will make it possible to relax the constraints between the chip housing and the printed circuit.
  • the rerouting of the input / output pads 13 is carried out by spraying a metal undercoat followed by electrolysis of Cu / Ni through a photosensitive resin. After removing the resin and the undercoat, the rerouting lines 15 are obtained; a photosensitive insulating layer 16 is then deposited using the spinning method or “spin coating” in English. This layer is then exposed through a mask in order to delimit the solder pads of the fusible balls 17. Finally, after the transfer fusible balls, the integrated circuits are singled out to obtain the chip-boxes.
  • this method requires at least two lithography steps: a step to delimit the metal tracks and a step to open the passivation deposited on the metal tracks.
  • the invention proposes a low-cost manufacturing method for a WLCSP package which makes it possible to integrate the packaging function of the integrated circuit on the scale of the substrate and which does not present the problems of the prior art.
  • the process which is the subject of the invention consists in producing, using a mold or a stencil, a layer serving to release the stresses between the chip housing and the printed circuit, on which said chip housing will be connected, giving it a stepped shape allowing, thereafter, a rerouting of the inputs / outputs with fewer lithography steps than in the prior art, if at all.
  • the method of producing a package the size of an electronic chip and produced on the scale of the substrate, said substrate comprising at least one chip and said at least one chip having input pads -outlet on one side of the substrate, called the front side comprises the following steps: a) forming, by means of a complex mold or stencil, an insulating layer of stress relaxation on said front side, said layer of relaxation covering the front face of the substrate with a relief having access wells at the level of the input-output pads, and elsewhere, projecting parts intended to relax the stresses, each projecting part having a stepped shape comprising at least a prominent area and at least one area, set back from said prominent area, intended to support an electrical connection pad, b) formation of electrically conductive tracks on the relaxation layer to connect er the input / output pads to the corresponding electrical connection pads, c) formation of electrical contact means towards the outside on the electrical connection pads.
  • a layer of polymer instead of several blocks of polymer as in the prior art makes it possible to isolate the input / output pads
  • the integrated circuits located on the substrate will include aluminum / copper or other input / output pads and a layer of mineral, organic passivation or both. These circuits may also have different finishes, for example, a chemical deposit of Ni / Au.
  • said method further comprises, between steps b) and c) above, a step of forming an encapsulation layer on the relaxation layer with exposure of the electrical connection pads. stress relaxation layer can be achieved by different methods.
  • said layer can be produced using a mold. For this, the following steps will be followed: 1) fill the mold with a determined relaxing polymer or apply said polymer directly to the front face of the substrate,
  • said layer can this time be produced using a stencil.
  • the following steps will then be followed: 1) apply the stencil to the front face of the substrate, 2) fill the holes in the stencil with a determined relaxing polymer, 3) anneal the polymer and separate the stencil from the substrate.
  • the two actions are interchangeable: the polymer can be annealed in order to then separate the stencil from the substrate, but the stencil can also be separated, in certain cases, before annealing the polymer.
  • said determined relaxing polymer used in the above embodiments will be chosen from the group consisting of polyimide, BCB or any other polymer capable of relaxing stresses.
  • the rerouting step or step of forming electrically conductive tracks for connecting the input / output pads of the integrated circuits to the corresponding electrical connection pads is simplified by virtue of the complex topology of the relaxing layer created previously.
  • this step of rerouting the inputs / outputs of the integrated circuits may not require a lithography step.
  • the conductive material is a metal.
  • the following sequence of steps can be followed: a) depositing a conductive material on the front face of the substrate covered with the relaxing layer, b) lithography, c) chemical etching, d) pickling, or alternatively the following steps: a) lithographic metallization of the front face of the substrate, b) electrolysis, c) pickling, d) chemical etching.
  • the deposition of a conductive material which has been mentioned previously is a metallization.
  • a metallization we will proceed by spraying, evaporation, electrodeposition or chemical deposition of one or more metals.
  • the enclosures can be encapsulated in order to improve the service life.
  • encapsulation can be total or partial.
  • the step of forming an encapsulation layer comprises the following steps: a) deposition of a polymer layer over the entire front surface of the substrate covered with the relaxation layer, b) planarization from the front face of the substrate, c) release of the electrical connection pads.
  • the step of forming an encapsulation layer comprises the following steps: a) planarization of the front face of the substrate covered with the relaxation layer, b) filling of the access shafts and recessed areas of the front face of the substrate with a thick polymer, c) release of the electrical connection pads.
  • the electrical connection pads will be released by running in, by chemical mechanical polishing, by etching or by any other technique.
  • planarization step of the front face of the substrate it is possible optionally to make cuts in the front face of the substrate, taking care not to entirely cut the relaxation layer. Then, an encapsulant is deposited on the rear face of the substrate and in the cutouts of the front face of the substrate. Under these conditions, the edges of the integrated circuits will also be protected near the cutting of the chip-boxes. Then, the electrical contact means must be installed outside on the electrical connection pads located on the relaxation layer.
  • This step can be performed before or after planarization of the substrate, but it is preferable to perform it after planarization. In fact, planarization makes it possible to delimit the electrical connection pads.
  • the means of electrical contact to the outside on the electrical connection pads will be fusible balls.
  • the fusible balls will be installed on the electrical connection pads using a technique chosen from electrolysis of fusible alloy, screen printing of solder paste, transfer of balls or any other technique.
  • these electrical contact means will be chosen from films and anisotropic conductive adhesives.
  • This method of making WLCSP boxes can be completed by additional steps.
  • the thickness of the enclosures may be reduced. For this, before or after installing the electrical contact means outwards on the electrical connection pads, the rear face of the substrate is thinned by running-in, by chemical mechanical polishing or any other technique.
  • the thickness of the substrate can be reduced to 50 ⁇ m. One can even consider reducing it until reaching the active thickness of the silicon.
  • the process can also be completed by the following steps: a) making trenches in the rear face of the substrate (by laser or chemical etching, by cutting or by any other technique) until reaching the metal layers represented by the studs input-output of integrated circuits or by electrically conductive tracks, b) deposit, possibly localized, of a metal layer (55) on the rear face of the substrate, c) elimination of metallization located on the surface of the rear face of the substrate .
  • the invention also relates to a complex mold or stencil intended to produce a housing the size of a chip according to the method of the invention.
  • this complex mold or stencil will be produced using at least one technique chosen from wet or dry etching, electroforming, bonding of several polymer films, pierced or not, molding, laser engraving or any other technique for performing complex topography.
  • said mold or said stencil is made of silicon, metal, polymer or any other similar material. Note that the release of the parts is facilitated with molds or stencils in polymers.
  • the invention also relates to a chip-sized package produced on the scale of the substrate, characterized in that it is produced by the method according to the invention.
  • the method according to the invention has many advantages, in particular a reduction in the number of steps for producing the chip packages.
  • the molding or poaching technique makes it possible at the same time to produce the topology necessary for rerouting the inputs / outputs and the layer making it possible to relax the thermomechanical constraints.
  • Said mold or stencil also makes it possible to reduce the number of photolithography steps. Consequently, it reduces the number of total steps necessary for the manufacture of the chip package, and thereby reduces the manufacturing price of said package. Furthermore, once this mold or this stencil is made, it can be reused, which will also reduce the cost of manufacturing the boxes.
  • FIGS. 1 and 2 illustrate the prior art presented previously in this description
  • FIGS. 3a and 3b illustrate the topology of the complex mold ( FIG. 3a) and of the complex stencil (FIG. 3b) according to the invention
  • FIGS. 4a to 4g illustrate a method of manufacturing WLCSP boxes according to the invention
  • FIGS. 5a to 5c illustrate additional manufacturing to obtain complete encapsulation of the integrated circuit
  • FIGS. 6a to 6g illustrate another method of manufacturing WLCSP packages according to the invention
  • FIG. 7 illustrates the encapsulation of all the surfaces of the integrated circuit produced on the scale of the substrate.
  • FIG. 4a A method of manufacturing a WLCSP package according to the present invention is illustrated in Figures 4a to 4g.
  • step b the stress relaxation layer denoted 28 is produced on said substrate (FIG. 4b).
  • This step is carried out either by molding the polymer on the substrate using a complex mold, or by screen printing of the polymer through a complex stencil on the substrate, or by transfer of the polymer (by making the polymer structure on another support using a mold or a complex stencil, which is then glued to the substrate).
  • This step can be accompanied by a cleaning process (for example a plasma treatment) to remove the polymer residues on the input / output pads 23 of the integrated circuits.
  • a cleaning process for example a plasma treatment
  • this step can be completed by an electrodeposition of copper.
  • This metallization step can also be carried out by chemical deposition of Ni / Au over the entire surface or by selective deposition (metallization located in access shafts and in recessed areas).
  • the metal tracks must be isolated by eliminating the metallization on the surface (FIG. 4d). This step is carried out by chemical mechanical polishing, by etching or any other technique. Note that in the case of a localized chemical deposit, this step is not necessary.
  • the metallization is preserved in the access wells to the studs and in all the areas set back from the machined upper surface of the relaxing layer. Then, the front face of the substrate is planarized by depositing an insulating layer denoted 29, for example by dispensing resin "underfill” which is planarized by spreading with a spinner or "spin coating” in English, by molding a polymer or by any other technique ( Figure 4e).
  • this insulating layer is opened by plasma etching, by polishing or by any other technique to release the attachment studs 30 from the balls (FIG. 4f). Finally, the substrate is billed
  • the last step consists in completely encapsulating the rear face of the substrate 22 and filling in the trenches made previously (FIG. 5c). This step can be carried out by molding, by exemption or any other technique of depositing insulation (noted 31).
  • FIGS. 6a to 6g illustrate a second method of manufacturing the WLCSP package. This manufacturing method includes contact resumption front / rear face and the complete encapsulation of integrated circuits.
  • each attachment pad 40 is surrounded by a trench to better define the weld zone.
  • the same steps are carried out as those presented in FIGS. 4d to 4f and the device of FIG. 6b is obtained: the recessed areas and the access shafts above the input-output pads have been filled by deposition an insulating layer 49.
  • the metallization step may be preceded by an etching step (for example by laser, by plasma, etc.) of the insulating layer at the pads.
  • the metallizations 55 are isolated by lapping, by chemical mechanical polishing or by any other technique from the surface of the rear face of the substrate. This step can be carried out after an encapsulation step (step not drawn).
  • the substrate is billed by placing the fusible balls 47 on the hooking pads 40 (FIG. 6f) and the singularization of the chip boxes (FIG. 6g) is carried out by cutting at the cutouts I.
  • the substrate 72 includes integrated circuits composed of input / output pads 73 and a passivation layer 74; the integrated circuits are then covered with a layer 78 relieving the stresses and having access wells leaving the input / output pads 73 accessible, said input / output pads and the fusible balls 77 overhanging the relaxing layer 78 being connected by rerouting lines 75.
  • An insulating layer 79 fills the access shafts and the recessed areas of the front face of the substrate, and a insulating layer 91 covers the rear face of the substrate.
  • FIGS. 6g and 7 are not limiting, the two versions being able in particular to be coupled.

Abstract

The invention concerns a method for making a wafer level electronic chip scale package, the wafer comprising at least one chip and said at least one chip including input/output contact pads on one surface of the wafer called front side, the method comprising the following steps: a) forming, by means of a mold or a complex stencil, an insulating stress-relaxing layer on said front surface, said relaxation layer covering the wafer front surface with a raised part including access wells at the input/output contact pads, and elsewhere, projecting parts designed to relax the stresses, each projecting part having a stepped shape comprising at least one prominent zone and at least one zone, recessed relative to said prominent zone, designed to support an electrical bond pad; b) forming electrically conductive tracks on the relaxation layer to connect the input/output contact pads to the corresponding electrical bond pads. The invention also concerns a mould or complex stencil for making a chip scale package using said inventive method as well as the resulting package itself.

Description

PROCEDE DE REROUTAGE DE DISPOSITIFS MICROELECTRONIQUES METHOD FOR REROUTING MICROELECTRONIC DEVICES
SANS LITHOGRAPHIEWITHOUT LITHOGRAPHY
DESCRIPTIONDESCRIPTION
DOMAINE TECHNIQUETECHNICAL AREA
La présente invention concerne un procédé de fabrication d'un boîtier à la taille d'une puce électronique réalisé à l'échelle du substrat (en anglais « Wafer Levai Chip Scale Package » ou WLCSP) . Dans la suite de la description, on appelera boîtier- puce ledit boîtier selon l'invention.The present invention relates to a method of manufacturing a package the size of an electronic chip produced on the scale of the substrate (in English "Wafer Levai Chip Scale Package" or WLCSP). In the following description, the package according to the invention will be called a chip-box.
L'invention concerne également un moule ou un pochoir complexe destiné à réaliser ledit boîtier- puce selon le procédé de l'invention et concerne aussi ledit boîtier-puce en lui-même.The invention also relates to a complex mold or stencil intended to produce said chip housing according to the method of the invention and also relates to said chip housing itself.
La miniaturisation des boîtiers est devenue un besoin vital pour répondre aux exigences du marché notamment en ce qui concerne le développement des systèmes portables ou des télécommunications, mais également pour permettre l'augmentation des entrées/sorties des circuits intégrés et pour diminuer le coût du packaging. Pour répondre à ces exigences, il faut que les dimensions des boîtiers électroniques se rapprochent des dimensions des circuits intégrés (avec la technologie boîtier-puce (« Chip Scale Package » en anglais ou CSP) ou la technologie flip-chip, on arrive à avoir des boîtiers ayant une dimension de 1 ou 1,2 fois la dimension du circuit) . Il faut également que le poids du boîtier et que la taille de la connectique se réduisent au maximum pour pouvoir augmenter le nombre d'entrées/sorties des circuits intégrés.The miniaturization of cases has become a vital need to meet market requirements, particularly with regard to the development of portable systems or telecommunications, but also to allow the increase in inputs / outputs of integrated circuits and to reduce the cost of packaging. . To meet these requirements, the dimensions of the electronic boxes must approach the dimensions of the integrated circuits (with the chip-box technology (“Chip Scale Package” in English or CSP) or the flip-chip technology, we get to have boxes with a dimension of 1 or 1.2 times the dimension of the circuit). It is also necessary that the weight of the box and the size of the connectors are reduced to the maximum in order to increase the number of inputs / outputs of the integrated circuits.
Par ailleurs, une des solutions pour réduire le coût des étapes du packaging est de réaliser le boîtier-puce à l'échelle du substrat. Or, la diminution de la taille du boîtier-puce pose un sérieux problème de fiabilité : deux risques principaux sont bien connus de l'homme du métier. Tout d'abord, l'humidité ou des effets de contamination provoquent des défaillances du circuit intégré, ces défaillances étant accélérées par la réduction des dimensions du boîtier. On doit donc améliorer la protection des circuits intégrés au sein du boîtier.In addition, one of the solutions to reduce the cost of the packaging steps is to produce the chip package on the scale of the substrate. However, the reduction in the size of the chip housing poses a serious reliability problem: two main risks are well known to those skilled in the art. First of all, humidity or contamination effects cause failures of the integrated circuit, these failures being accelerated by the reduction of the dimensions of the housing. We must therefore improve the protection of integrated circuits within the housing.
La deuxième défaillance est induite par la différence importante de dilatation thermique entre le boîtier et le substrat d'accueil (circuit imprimé) . Par exemple, pour un boîtier ayant un coefficient de dilatation thermique de 2,6 ppm/°C et le verre époxy constituant le circuit imprimé ayant un coefficient de 16 ppm/°C, la forte différence de dilatation thermique va induire, notamment pour les boîtiers à billes, de fortes contraintes dans les billes lors des variations de température. Or, ces contraintes peuvent être suffisamment élevées pour rompre les billes de connexion. La miniaturisation du boîtier nécessite donc également une amélioration de la fiabilité du packaging. ETAT DE LA TECHNIQUE ANTERIEUREThe second failure is caused by the significant difference in thermal expansion between the housing and the receiving substrate (printed circuit). For example, for a box having a coefficient of thermal expansion of 2.6 ppm / ° C and the epoxy glass constituting the printed circuit having a coefficient of 16 ppm / ° C, the large difference in thermal expansion will induce, in particular for ball housings, high stresses in the balls during temperature variations. However, these constraints can be high enough to break the connection balls. The miniaturization of the case therefore also requires an improvement in the reliability of the packaging. STATE OF THE PRIOR ART
Il existe déjà plusieurs procédés de fabrication de boîtier-puce réalisé à l'échelle du substrat ou boîtier WLCSP. Le procédé couramment utilisé est le reroutage des entrées/sorties du circuit intégré (voir figure 1 et document [1] référencé à la fin de cette description) .There are already several methods of manufacturing a chip housing made on the scale of the substrate or WLCSP package. The commonly used method is the rerouting of the inputs / outputs of the integrated circuit (see FIG. 1 and document [1] referenced at the end of this description).
La figure 1 présente une vue en coupe longitudinale d'un boîtier-puce 1 réalisé selon la technique explicitée dans le document [1] . Tout d'abord, un substrat 2, comportant des circuits intégrés dont les plots d'entrées/sorties sont référencés 3, est recouvert d'une couche isolante ou couche de passivation 4. Pour déposer ladite couche, on procède généralement par étalement à la tournette pour les polymères ou par dépôt chimique en phase vapeur pour les minéraux. Puis on ouvre ladite couche isolante, soit par insolation du polymère à travers un masque, soit par lithographie et gravure (c'est à dire par dépôt d'une résine photosensible, puis insolation à travers un masque). Ensuite débute l'étape de reroutage proprement dite : on commence par vaporiser un fond continu sur le circuit intégré, puis on effectue une électrolyse de cuivre à travers une résine photosensible ; ensuite on décape ladite résine et on effectue la gravure du fond continu. On obtient ainsi les lignes de reroutage 5. Puis, on dépose une nouvelle couche isolante 6, qui va servir de délimitation pour la soudure, et enfin, on effectue la métallisation du circuit intégré, soit par pulvérisation, soit par dépôt chimique de l'UB (de l'anglais « under bump metalization ») , où l'UBM représente la métallurgie d'accrochage de billes fusibles 7. Au final, on obtient des lignes de reroutage 5 (conductrices) , qui relient les plots d'entrées/sorties 3 aux billes fusibles 7.FIG. 1 presents a view in longitudinal section of a chip housing 1 produced according to the technique explained in document [1]. First of all, a substrate 2, comprising integrated circuits whose input / output pads are referenced 3, is covered with an insulating layer or passivation layer 4. To deposit said layer, one generally proceeds by spreading the spinner for polymers or by chemical vapor deposition for minerals. Then said insulating layer is opened, either by exposure of the polymer through a mask, or by lithography and etching (that is to say by deposition of a photosensitive resin, then exposure through a mask). Then begins the rerouting step proper: we start by vaporizing a continuous background on the integrated circuit, then we perform an electrolysis of copper through a photosensitive resin; then said resin is etched and the continuous bottom is etched. The rerouting lines 5 are thus obtained. Then, a new insulating layer 6 is deposited, which will serve as a delimitation for the soldering, and finally, the metallization of the integrated circuit is carried out, either by spraying or by deposition. UB chemical (from English “under bump metalization”), where UBM represents the metallurgy of attachment of fusible balls 7. In the end, we obtain rerouting lines 5 (conductive), which connect the studs inputs / outputs 3 to the fusible balls 7.
L'inconvénient de ce procédé est qu'il présente au moins trois étapes de lithographie. Ainsi, même si le procédé est réalisé à l'échelle du substrat, le nombre d'étapes pour le packaging du circuit intégré présente un coût important.The disadvantage of this process is that it has at least three stages of lithography. Thus, even if the process is carried out on the scale of the substrate, the number of steps for packaging the integrated circuit presents a significant cost.
Le deuxième problème relatif à ce mode de fabrication est que, si les boîtiers CSP ou boîtiers- puces sont montés sur les circuits imprimés sans interposition de résine (dénommée « underfill » dans la technique concernée) , la connectique sera alors de faible fiabilité : les différences de dilatation thermique entre le boîtier CSP et le circuit imprimé induisent en effet des contraintes dans les billes périphériques, surtout si les circuits intégrés sont larges. Pour ce type de boîtier, il est donc indispensable de rajouter une résine « underfill » sous le boîtier afin de répartir les contraintes sur les billes et la résine « underfill ». Mais le problème est que l'utilisation de cette résine n'est pas forcément souhaitée selon les applications et cela rajoute généralement au moins une étape supplémentaire. De plus, l'utilisation de cette résine rend la réparation d'un composant plus- délicate puisqu'il oblige au remplacement d'un boîtier défectueux par un nouveau. Le deuxième procédé innovant de fabrication de boîtiers WLCSP a été présenté par A. Kazama (voir le document [2] référencé à la fin de cette description) .The second problem relating to this manufacturing method is that, if the CSP boxes or chip boxes are mounted on the printed circuits without resin interposition (called “underfill” in the technique concerned), the connections will then be of low reliability: the Differences in thermal expansion between the CSP box and the printed circuit indeed induce stresses in the peripheral balls, especially if the integrated circuits are large. For this type of case, it is therefore essential to add an "underfill" resin under the case in order to distribute the stresses on the balls and the "underfill" resin. But the problem is that the use of this resin is not necessarily desired depending on the applications and this generally adds at least one additional step. In addition, the use of this resin makes the repair of a component more delicate since it requires the replacement of a defective housing with a new one. The second innovative WLCSP box manufacturing process was presented by A. Kazama (see document [2] referenced at the end of this description).
Un boîtier-puce réalisé selon la technique du document [2] est illustré dans la figure 2 suivant une vue en coupe longitudinale. De même que précédemment, on a un boîtier WLCSP 11 comportant un substrat 12, des plots de circuit intégré 13 et une couche de passivation 14. La différence par rapport au document précédent réside dans la présence d'épais pavés de polymère 18 entre la face avant du substrat 12 et les billes fusibles 17. Ce sont ces épais pavés de polymères qui vont permettre de relâcher les contraintes entre le boîtier-puce et le circuit imprimé .A chip housing produced according to the technique of document [2] is illustrated in FIG. 2 in a view in longitudinal section. As previously, there is a WLCSP housing 11 comprising a substrate 12, integrated circuit pads 13 and a passivation layer 14. The difference compared to the previous document lies in the presence of thick blocks of polymer 18 between the face front of the substrate 12 and the fusible balls 17. It is these thick blocks of polymers which will make it possible to relax the constraints between the chip housing and the printed circuit.
Le reroutage des plots d'entrée/sortie 13 est réalisé par une pulvérisation d'une sous-couche métallique suivie d'une électrolyse de Cu/Ni à travers une résine photosensible. Après avoir retiré la résine et la sous-couche, on obtient les lignes de reroutage 15 ; on dépose ensuite par la méthode dite à la tournette ou « spin coating » en anglais, une couche isolante photosensible 16. Cette couche est ensuite insolêe à travers un masque afin de délimiter les plots de soudure des billes fusibles 17. Enfin, après le report des billes fusibles, on singularise les circuits intégrés pour obtenir les boîtiers-puces.The rerouting of the input / output pads 13 is carried out by spraying a metal undercoat followed by electrolysis of Cu / Ni through a photosensitive resin. After removing the resin and the undercoat, the rerouting lines 15 are obtained; a photosensitive insulating layer 16 is then deposited using the spinning method or “spin coating” in English. This layer is then exposed through a mask in order to delimit the solder pads of the fusible balls 17. Finally, after the transfer fusible balls, the integrated circuits are singled out to obtain the chip-boxes.
Au final, on a un substrat recouvert de pavés de polymère 18 et dont les plots d'entrée/sortie 13 sont reliés aux billes fusibles 17 par des lignes de reroutage 15. Ce procédé de fabrication de boîtiers WLCSP permet de réduire les coûts de fabrication (les pavés de polymère sont déposés par sérigraphie, qui est un procédé bas coût) et de réduire les contraintes mécaniques s'exerçant au niveau des billes fusibles. Cependant, la méthode utilisée pour déposer le polymère ne permet pas d' isoler les plots d' entrée/sortie des circuits intégrés .In the end, there is a substrate covered with blocks of polymer 18 and whose input / output pads 13 are connected to the fusible balls 17 by rerouting lines 15. This method of manufacturing WLCSP boxes makes it possible to reduce the manufacturing costs (the polymer pavers are deposited by screen printing, which is a low cost process) and to reduce the mechanical stresses exerted on the fusible balls. However, the method used to deposit the polymer does not make it possible to isolate the input / output pads of the integrated circuits.
De plus, cette méthode nécessite au moins deux étapes de lithographie : une étape pour délimiter les pistes métalliques et une étape pour ouvrir la passivation déposée sur les pistes métalliques.In addition, this method requires at least two lithography steps: a step to delimit the metal tracks and a step to open the passivation deposited on the metal tracks.
Par ailleurs, les étapes de lithographies sont réalisées sur du relief ; or il s'avère que le dépôt de résine photosensible sur du relief est une opération délicate et onéreuse.Furthermore, the lithography steps are carried out on relief; however it turns out that the deposition of photosensitive resin on relief is a delicate and expensive operation.
EXPOSE DE L'INVENTIONSTATEMENT OF THE INVENTION
L'invention propose un procédé de fabrication bas coût d'un boîtier WLCSP permettant d' intégrer la fonction de packaging du circuit intégré à l'échelle du substrat et qui ne présente pas les problèmes de l' art antérieur .The invention proposes a low-cost manufacturing method for a WLCSP package which makes it possible to integrate the packaging function of the integrated circuit on the scale of the substrate and which does not present the problems of the prior art.
Le procédé, objet de l'invention, consiste à réaliser, à l'aide d'un moule ou d'un pochoir, une couche servant à relâcher les contraintes entre le boîtier-puce et le circuit imprimé, sur lequel ledit boîtier-puce va être connecté, en lui donnant une forme étagée permettant, par la suite, un reroutage des entrées/sorties avec moins d'étapes de lithographie que dans l'art antérieur, voire pas du tout. En d'autres termes, le procédé de réalisation d'un boîtier à la taille d'une puce électronique et réalisé à l'échelle du substrat, ledit substrat comportant au moins une puce et ladite au moins une puce possédant des plots d'entrée-sortie sur une face du substrat dite face avant, comprend les étapes suivantes : a) formation, au moyen d'un moule ou d'un pochoir complexe, d'une couche isolante de relaxation de contraintes sur ladite face avant, ladite couche de relaxation recouvrant la face avant du substrat avec un relief présentant des puits d'accès au niveau des plots d'entrée-sortie, et ailleurs, des parties en saillie destinées à relaxer les contraintes, chaque partie en saillie ayant une forme étagée comprenant au moins une zone proéminente et au moins une zone, en retrait par rapport à ladite zone proéminente, destinée à supporter un plot de connection électrique, b) formation de pistes électriquement conductrices sur la couche de relaxation pour connecter les plots d'entrée/sortie aux plots de connection électrique correspondants , c) formation de moyens de contact électrique vers 1 ' extérieur sur les plots de connection électrique . Ici, utiliser une couche de polymère au lieu de plusieurs pavés de polymère comme dans l'art antérieur permet d'isoler les plots d'entrée/sortie du reste des circuits intégrés.The process which is the subject of the invention consists in producing, using a mold or a stencil, a layer serving to release the stresses between the chip housing and the printed circuit, on which said chip housing will be connected, giving it a stepped shape allowing, thereafter, a rerouting of the inputs / outputs with fewer lithography steps than in the prior art, if at all. In other words, the method of producing a package the size of an electronic chip and produced on the scale of the substrate, said substrate comprising at least one chip and said at least one chip having input pads -outlet on one side of the substrate, called the front side, comprises the following steps: a) forming, by means of a complex mold or stencil, an insulating layer of stress relaxation on said front side, said layer of relaxation covering the front face of the substrate with a relief having access wells at the level of the input-output pads, and elsewhere, projecting parts intended to relax the stresses, each projecting part having a stepped shape comprising at least a prominent area and at least one area, set back from said prominent area, intended to support an electrical connection pad, b) formation of electrically conductive tracks on the relaxation layer to connect er the input / output pads to the corresponding electrical connection pads, c) formation of electrical contact means towards the outside on the electrical connection pads. Here, using a layer of polymer instead of several blocks of polymer as in the prior art makes it possible to isolate the input / output pads from the rest of the integrated circuits.
De manière générale, les circuits intégrés situés sur le substrat comporteront des plots d'entrée/sortie en aluminium, en cuivre ou autres et une couche de passivation minérale, organique ou les deux. Ces circuits pourront aussi comporter des finitions différentes, par exemple, un dépôt chimique de Ni/Au. Selon un mode particulier de l'invention, ledit procédé comprend en outre, entre les étapes b) et c) précédentes, une étape de formation d'une couche d" encapsulâtion sur la couche de relaxation avec exposition des plots de connection électrique. La couche de relaxation des contraintes peut être réalisée par différentes méthodes.In general, the integrated circuits located on the substrate will include aluminum / copper or other input / output pads and a layer of mineral, organic passivation or both. These circuits may also have different finishes, for example, a chemical deposit of Ni / Au. According to a particular embodiment of the invention, said method further comprises, between steps b) and c) above, a step of forming an encapsulation layer on the relaxation layer with exposure of the electrical connection pads. stress relaxation layer can be achieved by different methods.
Selon un mode de réalisation, ladite couche peut être réalisé à l'aide d'un moule. Pour cela, on suivra les étapes suivantes : 1) remplir le moule avec un polymère relaxant déterminé ou appliquer ledit polymère directement sur la face avant du substrat,According to one embodiment, said layer can be produced using a mold. For this, the following steps will be followed: 1) fill the mold with a determined relaxing polymer or apply said polymer directly to the front face of the substrate,
2) aligner le moule sur la face avant du substrat,2) align the mold on the front face of the substrate,
3) presser le moule sur la face avant du substrat, 4) recuire le polymère,3) press the mold on the front face of the substrate, 4) anneal the polymer,
5) retirer le moule.5) remove the mold.
Si on décide d'appliquer le polymère relaxant directement sur le substrat, on a le choix entre différentes méthodes parmi lesquelles l'étalement ou la dispense.If one decides to apply the relaxing polymer directly to the substrate, one has the choice between different methods among which spreading or dispensing.
Selon un autre mode de réalisation, ladite couche peut cette fois ci être réalisée à l'aide d'un pochoir. On suivra alors les étapes suivantes : 1) appliquer le pochoir sur la face avant du substrat, 2) remplir les orifices du pochoir avec un polymère relaxant déterminé, 3) recuire le polymère et séparer le pochoir du substrat .According to another embodiment, said layer can this time be produced using a stencil. The following steps will then be followed: 1) apply the stencil to the front face of the substrate, 2) fill the holes in the stencil with a determined relaxing polymer, 3) anneal the polymer and separate the stencil from the substrate.
Concernant cette dernière étape, les deux actions sont interchangeables : on pourra recuire le polymère pour ensuite séparer le pochoir du substrat, mais la séparation du pochoir pourra également, dans certains cas, être réalisée avant de recuire le polymère.Regarding this last step, the two actions are interchangeable: the polymer can be annealed in order to then separate the stencil from the substrate, but the stencil can also be separated, in certain cases, before annealing the polymer.
Avantageusement, ledit polymère relaxant déterminé utilisé dans les réalisations ci-dessus sera choisi parmi le groupe constitué du polyimide, du BCB ou de tout autre polymère susceptible de relaxer les contraintes .Advantageously, said determined relaxing polymer used in the above embodiments will be chosen from the group consisting of polyimide, BCB or any other polymer capable of relaxing stresses.
Après l'obtention de la couche relaxant les contraintes sur la face avant du substrat, il se peut qu'il y ait des résidus de polymère sur les plots d'entrée/sortie, ce qui risquerait d'empêcher la reprise de contact sur lesdits plots. Avantageusement, on élimine donc lesdits résidus de polymère ; on pourra pour cela utiliser un procédé de nettoyage tel qu'un traitement plasma ou toute autre technique similaire.After obtaining the stress relieving layer on the front face of the substrate, it may be that there are polymer residues on the input / output pads, which would risk preventing the resumption of contact on said pads. Advantageously, said polymer residues are therefore eliminated; for this, a cleaning process such as plasma treatment or any other similar technique can be used.
L'étape de reroutage ou étape de formation des pistes électriquement conductrices pour connecter les plots d'entrée/sortie des circuits intégrés aux plots de connection électrique correspondants est simplifiée grâce à la topologie complexe de la couche relaxante créée précédemment.The rerouting step or step of forming electrically conductive tracks for connecting the input / output pads of the integrated circuits to the corresponding electrical connection pads is simplified by virtue of the complex topology of the relaxing layer created previously.
Grâce à la topologie complexe de la couche relaxante, cette étape de reroutage des entrées/sorties des circuits intégrés peut ne pas nécessiter d'étape de lithographie. Dans ce cas, deux choix se présente à nous : - si l'on désire effectuer un dépôt de matériau conducteur sur toute la surface de la face avant du substrat, on suivra les étapes suivantes : a) dépôt d'un matériau conducteur sur la face avant du substrat recouverte de la couche de relaxation, b) séparation des lignes de reroutage et formation des plots de connexion électrique par élimination du matériau conducteur situé au niveau de la (des) zone (s) proéminente (s) des parties en saillie de la couche de relaxation par rodage mécanique ou par polissage mécano-chimique .Thanks to the complex topology of the relaxing layer, this step of rerouting the inputs / outputs of the integrated circuits may not require a lithography step. In this case, we have two choices: - if it is desired to deposit a conductive material over the entire surface of the front face of the substrate, the following steps will be followed: a) deposit of a conductive material on the front face of the substrate covered with the relaxation layer, b) separation of the rerouting lines and formation of the electrical connection pads by elimination of the conductive material located at the level of the prominent zone (s) of the protruding parts of the relaxation layer by mechanical lapping or by polishing mechanical-chemical.
En ce qui concerne les deux techniques de séparation des lignes de reroutage, elles permettent d'éliminer le métal en surface sans attaquer le métal situées dans les zones inférieures par rapport au niveau jusqu' auquel on procède à l'élimination.With regard to the two techniques for separating the rerouting lines, they make it possible to remove the metal on the surface without attacking the metal situated in the lower zones relative to the level up to which elimination is carried out.
mais si l'on ne veut déposer de matériau conducteur que dans les puits d'accès aux plots d'entrée-sortie et dans les zones en retrait par rapport à la (les) zone (s) proéminente (s) des parties en saillie de la couche relaxante, on réalisera un dépôt chimique de matériau conducteur seulement dans lesdits endroits. L'étape d'élimination du matériau conducteur en surface de la couche relaxante, c'est à dire sur la (les) zone (s) proéminente (s) des parties en saillie, pour séparer les lignes de reroutage ne sera alors pas nécessaire.but if it is desired to deposit conductive material only in the access wells to the input-output pads and in the areas set back relative to the prominent area (s) of the projecting parts of the relaxing layer, a chemical deposition of conductive material will be carried out only in said places. The step of removing the conductive material on the surface of the relaxing layer, that is to say on the prominent zone (s) of the projecting parts, in order to separate the rerouting lines will then not be necessary. .
Avantageusement, le matériau conducteur est un métal. On peut aussi utiliser les techniques traditionnelles de reroutage qui, grâce à la topologie complexe de la couche relaxante, ne nécessiteront qu'une seule étape de lithographie. Dans ce cas, on pourra suivre la suite d'étapes suivante : a) dépôt d'un matériau conducteur sur la face avant du substrat recouverte de la couche relaxante, b) lithographie, c) gravure chimique, d) décapage, ou bien la suite d'étapes suivantes : a) métallisation lithographique de la face avant du substrat, b) électrolyse, c) décapage, d) gravure chimique .Advantageously, the conductive material is a metal. One can also use traditional rerouting techniques which, thanks to the complex topology of the relaxing layer, will only require a single lithography step. In this case, the following sequence of steps can be followed: a) depositing a conductive material on the front face of the substrate covered with the relaxing layer, b) lithography, c) chemical etching, d) pickling, or alternatively the following steps: a) lithographic metallization of the front face of the substrate, b) electrolysis, c) pickling, d) chemical etching.
Avantageusement, le dépôt d'un matériau conducteur dont on a parlé précédemment est une métallisation. Pour opérer cette métallisation, on procédera par pulvérisation, êvaporation, électrodéposition ou dépôt chimique d'un ou plusieurs métaux.Advantageously, the deposition of a conductive material which has been mentioned previously is a metallization. To operate this metallization, we will proceed by spraying, evaporation, electrodeposition or chemical deposition of one or more metals.
Une fois le reroutage réalisé, on peut effectuer l' encapsulation des boîtiers afin d'en améliorer la durée de vie. Il existe différentes méthodes d' encapsulation : par sérigraphie, par moulage dispense, par étalement... De même, l' encapsulation peut être totale ou partielle. Selon un premier mode de réalisation, l'étape de formation d'une couche d' encapsulation comprend les étapes suivantes : a) dépôt d'une couche de polymère sur toute la surface avant du substrat recouverte de la couche de relaxation, b) planarisation de la face avant du substrat, c) libération des plots de connection électrique.Once the rerouting has been carried out, the enclosures can be encapsulated in order to improve the service life. There are different methods of encapsulation: by screen printing, by dispensing molding, by spreading ... Similarly, the encapsulation can be total or partial. According to a first embodiment, the step of forming an encapsulation layer comprises the following steps: a) deposition of a polymer layer over the entire front surface of the substrate covered with the relaxation layer, b) planarization from the front face of the substrate, c) release of the electrical connection pads.
Selon un deuxième mode de réalisation, l'étape de formation d'une couche d' encapsulation comprend les étapes suivantes : a) planarisation de la face avant du substrat recouverte de la couche de relaxation, b) remplissage des puits d'accès et des zones en retrait de la face avant du substrat avec un polymère épais, c) libération des plots de connection électrique.According to a second embodiment, the step of forming an encapsulation layer comprises the following steps: a) planarization of the front face of the substrate covered with the relaxation layer, b) filling of the access shafts and recessed areas of the front face of the substrate with a thick polymer, c) release of the electrical connection pads.
La libération des plots de connection électrique se fera par rodage, par polissage mécano- chimique, par gravure ou par toute autre technique.The electrical connection pads will be released by running in, by chemical mechanical polishing, by etching or by any other technique.
Après l'étape de planarisation de la face avant du substrat, on peut éventuellement effectuer des découpes dans la face avant du substrat, en prenant garde de ne pas découper entièrement la couche de relaxation. Puis, on dépose un encapsulant sur la face arrière du substrat et dans les découpes de la face avant du substrat. Dans ces conditions, les bords des circuits intégrés seront aussi protégés près la découpe des boîtiers-puces. Puis, on doit installer les moyens de contact électrique vers l'extérieur sur les plots de connection électrique situés sur la couche de relaxation. Cette étape peut être réalisée avant ou après la planarisation du substrat, mais il est préférable de la réaliser après la planarisation. En effet, la planarisation permet de délimiter les plots de connection électrique.After the planarization step of the front face of the substrate, it is possible optionally to make cuts in the front face of the substrate, taking care not to entirely cut the relaxation layer. Then, an encapsulant is deposited on the rear face of the substrate and in the cutouts of the front face of the substrate. Under these conditions, the edges of the integrated circuits will also be protected near the cutting of the chip-boxes. Then, the electrical contact means must be installed outside on the electrical connection pads located on the relaxation layer. This step can be performed before or after planarization of the substrate, but it is preferable to perform it after planarization. In fact, planarization makes it possible to delimit the electrical connection pads.
Avantageusement, les moyens de contact électrique vers l'extérieur sur les plots de connection électrique seront des billes fusibles.Advantageously, the means of electrical contact to the outside on the electrical connection pads will be fusible balls.
Dans ce cas, les billes fusibles seront installées sur les plots de connection électrique à l'aide d'une technique choisie parmi l'éleσtrolyse d'alliage fusible, la sérigraphie de pâte à braser, le transfert de billes ou toute autre technique.In this case, the fusible balls will be installed on the electrical connection pads using a technique chosen from electrolysis of fusible alloy, screen printing of solder paste, transfer of balls or any other technique.
Selon un autre cas de réalisation, ces moyens de contact électrique seront choisis parmi les films et les colles anisotropes conducteurs.According to another embodiment, these electrical contact means will be chosen from films and anisotropic conductive adhesives.
Enfin, on doit s'occuper de l'étape de séparation des boîtiers-puces. Cette séparation ou singularisation est réalisée par découpe avec une scie, découpe par gravure laser ou tout autre moyen similaire.Finally, we must deal with the step of separating the chip-boxes. This separation or singularization is carried out by cutting with a saw, cutting by laser engraving or any other similar means.
Ce procédé de réalisation de boîtiers WLCSP peut être complété par des étapes supplémentaires.This method of making WLCSP boxes can be completed by additional steps.
Tout d'abord, on peut avoir besoin de réduire l'épaisseur des boîtiers. Pour cela, avant ou après l'installation des moyens de contact électrique vers l'extérieur sur les plots de connection électrique, la face arrière du substrat est aminci par rodage, par polissage mécano-chimique ou toute autre technique. Par exemple, dans le cas du silicium, on peut réduire l'épaisseur du substrat à 50 μm. On peut même envisager de le réduire jusqu'à atteindre l'épaisseur active du silicium.First, you may need to reduce the thickness of the enclosures. For this, before or after installing the electrical contact means outwards on the electrical connection pads, the rear face of the substrate is thinned by running-in, by chemical mechanical polishing or any other technique. For example, in the case of silicon, the thickness of the substrate can be reduced to 50 μm. One can even consider reducing it until reaching the active thickness of the silicon.
On peut également compléter le procédé par les étapes suivantes : a) réalisation de tranchées dans la face arrière du substrat (par gravure laser ou chimique, par découpe ou par toute autre technique) jusqu' à atteindre les couches métalliques représentés par les plots d'entrée- sortie des circuits intégrés ou par les pistes électriquement conductrices, b) dépôt, éventuellement localisé, d'une couche métallique (55) sur la face arrière du substrat, c) élimination de la métallisation située en surface de la face arrière du substrat.The process can also be completed by the following steps: a) making trenches in the rear face of the substrate (by laser or chemical etching, by cutting or by any other technique) until reaching the metal layers represented by the studs input-output of integrated circuits or by electrically conductive tracks, b) deposit, possibly localized, of a metal layer (55) on the rear face of the substrate, c) elimination of metallization located on the surface of the rear face of the substrate .
L'invention concerne également un moule ou pochoir complexe destiné à réaliser un boîtier à la taille d'une puce selon le procédé de l'invention. Avantageusement, ce moule ou pochoir complexe sera réalisé à l'aide d'au moins une technique choisie parmi la gravure humide ou sèche, 1' électroformage, le collage de plusieurs films polymères percés ou non, le moulage, la gravure laser ou toute autre technique permettant de réaliser une topographie complexe. Avantageusement, ledit moule ou ledit pochoir est réalisé en silicium, en métal, en polymère ou tout autre matériau similaire. On notera que le démoulage des pièces est facilité avec des moules ou des pochoirs en polymères .The invention also relates to a complex mold or stencil intended to produce a housing the size of a chip according to the method of the invention. Advantageously, this complex mold or stencil will be produced using at least one technique chosen from wet or dry etching, electroforming, bonding of several polymer films, pierced or not, molding, laser engraving or any other technique for performing complex topography. Advantageously, said mold or said stencil is made of silicon, metal, polymer or any other similar material. Note that the release of the parts is facilitated with molds or stencils in polymers.
L'invention concerne aussi un boîtier à la taille d'une puce réalisé à l'échelle du substrat caractérisé en ce qu'il est réalisé par le procédé selon l'invention.The invention also relates to a chip-sized package produced on the scale of the substrate, characterized in that it is produced by the method according to the invention.
Le procédé selon l'invention présente de nombreux avantages, notamment une réduction du nombre d'étapes pour la réalisation des boîtiers-puces . En effet, la technique du moulage ou du pochage permet de réaliser en même temps la topologie nécessaire pour réaliser le reroutage des entrées/sorties et la couche permettant de relâcher les contraintes thermomécaniques. Ledit moule ou pochoir permet aussi de réduire le nombre d'étapes de photolithographie. Par conséquent, il réduit le nombre d'étapes totales nécessaire à la fabrication du boîtier-puce, et par-là même, réduit le prix de fabrication dudit boîtier. Par ailleurs, une fois ce moule ou ce pochoir réalisé, il pourra être réutilisé, ce qui réduira aussi le coût de fabrication des boîtiers.The method according to the invention has many advantages, in particular a reduction in the number of steps for producing the chip packages. In fact, the molding or poaching technique makes it possible at the same time to produce the topology necessary for rerouting the inputs / outputs and the layer making it possible to relax the thermomechanical constraints. Said mold or stencil also makes it possible to reduce the number of photolithography steps. Consequently, it reduces the number of total steps necessary for the manufacture of the chip package, and thereby reduces the manufacturing price of said package. Furthermore, once this mold or this stencil is made, it can be reused, which will also reduce the cost of manufacturing the boxes.
BRÈVE DESCRIPTION DES DESSINSBRIEF DESCRIPTION OF THE DRAWINGS
D'autres caractéristiques et avantages de l'invention apparaîtront mieux à la lumière de la description qui va suivre. Cette description porte sur les exemples de réalisation, donnés à titre explicatif et non limitatif, en ce référant aux dessins annexés parmi lesquels : les figures 1 et 2 illustrent l'art antérieur présenté précédemment dans cette description, les figures 3a et 3b illustrent la topologie du moule complexe (figure 3a) et du pochoir complexe (figure 3b) selon l'invention, les figures 4a à 4g illustrent un mode de fabrication de boîtiers WLCSP selon l'invention, les figures 5a à 5c illustrent un complément de fabrication pour obtenir une encapsulation complète du circuit intégré, les figures 6a à 6g illustrent un autre mode de fabrication de boîtiers WLCSP selon l'invention, la figure 7 illustre l' encapsulation de toutes les surfaces du circuit intégré réalisé à l'échelle du substrat.Other characteristics and advantages of the invention will appear better in the light of the description which follows. This description relates to the exemplary embodiments, given by way of nonlimiting explanation, with reference to the appended drawings among which: FIGS. 1 and 2 illustrate the prior art presented previously in this description, FIGS. 3a and 3b illustrate the topology of the complex mold ( FIG. 3a) and of the complex stencil (FIG. 3b) according to the invention, FIGS. 4a to 4g illustrate a method of manufacturing WLCSP boxes according to the invention, FIGS. 5a to 5c illustrate additional manufacturing to obtain complete encapsulation of the integrated circuit, FIGS. 6a to 6g illustrate another method of manufacturing WLCSP packages according to the invention, FIG. 7 illustrates the encapsulation of all the surfaces of the integrated circuit produced on the scale of the substrate.
Il est à noter que, pour simplifier, les figures ne sont pas dessinées à l'échelle du substrat.It should be noted that, for simplicity, the figures are not drawn to the scale of the substrate.
EXPOSÉ DETAILLE DE MODES DE REALISATION PARTICULIERSDETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
Un procédé de fabrication d'un boîtier WLCSP selon la présente invention est illustrée par les figures 4a à 4g.A method of manufacturing a WLCSP package according to the present invention is illustrated in Figures 4a to 4g.
Comme le montre la figure 4a, on démarre avec un substrat 22 comportant des circuits intégrés, chaque circuit présentant des plots d'entrée/sortie 23 et une couche de passivation 24, lesdits éléments étant obtenus par les méthodes explicités dans l'art antérieur. Pendant l'étape b, on réalise la couche de relaxation des contraintes notée 28 sur ledit substrat (figure 4b) . Cette étape est réalisée soit par moulage du polymère sur le substrat à l'aide d'un moule complexe, soit par sérigraphie du polymère à travers un pochoir complexe sur le substrat, soit par transfert du polymère (par réalisation de la structure en polymère sur un autre support à l'aide d'un moule ou d'un pochoir complexe, que l'on colle ensuite sur le substrat) .As shown in FIG. 4a, one starts with a substrate 22 comprising integrated circuits, each circuit having input / output pads 23 and a passivation layer 24, said elements being obtained by the methods explained in the prior art. During step b, the stress relaxation layer denoted 28 is produced on said substrate (FIG. 4b). This step is carried out either by molding the polymer on the substrate using a complex mold, or by screen printing of the polymer through a complex stencil on the substrate, or by transfer of the polymer (by making the polymer structure on another support using a mold or a complex stencil, which is then glued to the substrate).
Cette étape peut être accompagnée d'un procédé de nettoyage (par exemple un traitement plasma) pour retirer les résidus de polymère sur les plots d'entrée/sortie 23 des circuits intégrés. Puis, on dépose une couche métallique notéeThis step can be accompanied by a cleaning process (for example a plasma treatment) to remove the polymer residues on the input / output pads 23 of the integrated circuits. Then, we deposit a metallic layer noted
25 (par exemple par pulvérisation d'une couche de titane/cuivre) sur toute la surface du substrat (figure 4c). Si l'on désire augmenter l'épaisseur de la couche métallique, cette étape peut être complétée par une êlectrodéposition de cuivre. Cette étape de métallisation peut aussi être réalisée par dépôt chimique de Ni/Au sur toute la surface ou par un dépôt sélectif (métallisation localisées dans les puits d'accès et dans les zones en retrait) . Ensuite, on doit isoler les pistes métalliques par élimination de la métallisation en surface (figure 4d) . On effectue cette étape par polissage mécano-chimique, par gravure ou toute autre technique. On remarque que dans le cas d'un dépôt chimique localisé, cette étape n'est pas nécessaire. Dans ces conditions, la métallisation est conservée dans les puits d'accès aux plots et dans toutes les zones en retrait par rapport à la surface supérieure usinée de la couche relaxante. Puis, on planarise la face avant du substrat par un dépôt de couche isolante notée 29, par exemple par dispense de résine « underfill » que l'on planarise par étalement à la tournette ou « spin coating » en anglais, par moulage d'un polymère ou par toute autre technique (figure 4e) .25 (for example by spraying a layer of titanium / copper) over the entire surface of the substrate (FIG. 4c). If it is desired to increase the thickness of the metal layer, this step can be completed by an electrodeposition of copper. This metallization step can also be carried out by chemical deposition of Ni / Au over the entire surface or by selective deposition (metallization located in access shafts and in recessed areas). Next, the metal tracks must be isolated by eliminating the metallization on the surface (FIG. 4d). This step is carried out by chemical mechanical polishing, by etching or any other technique. Note that in the case of a localized chemical deposit, this step is not necessary. Under these conditions, the metallization is preserved in the access wells to the studs and in all the areas set back from the machined upper surface of the relaxing layer. Then, the front face of the substrate is planarized by depositing an insulating layer denoted 29, for example by dispensing resin "underfill" which is planarized by spreading with a spinner or "spin coating" in English, by molding a polymer or by any other technique (Figure 4e).
Puis, on ouvre cette couche isolante par gravure plasma, par polissage ou par toute autre technique pour libérer les plots d'accrochage 30 des billes (figure 4f) . Enfin, on réalise le billage du substratThen, this insulating layer is opened by plasma etching, by polishing or by any other technique to release the attachment studs 30 from the balls (FIG. 4f). Finally, the substrate is billed
(figure 4g) . On peut employer toutes les techniques pour réaliser les billes fusibles notées 27.(Figure 4g). All the techniques can be used to make the fusible balls marked 27.
On peut décider d'encapsuler complètement les circuits intégrés. Dans ce cas, les étapes d' encapsulation devront être insérées entre les étapes f et g vues précédemment.We can decide to completely encapsulate integrated circuits. In this case, the encapsulation steps must be inserted between steps f and g seen previously.
Tout d'abord, on peut procéder à l'amincissement de la face arrière du substrat 22 par rodage ou par toute autre technique, mais cette étape n'est pas obligatoire (figure 5a).First of all, it is possible to thin the rear face of the substrate 22 by lapping or by any other technique, but this step is not compulsory (FIG. 5a).
Ensuite, on découpe la face arrière du substrat 22 jusqu'à atteindre la couche de passivationThen, the rear face of the substrate 22 is cut out until the passivation layer is reached.
24 des circuits intégrés ' (figure 5b) . Cette opération peut être faite par découpe mécanique, par découpe laser.ou par toute autre technique. La dernière étape consiste à encapsuler entièrement la face arrière du substrat 22 et en comblant les tranchées faites précédemment (figure 5c) . Cette étape peut être réalisée par moulage, par dispense ou toute autre technique de dépôt d'isolant (noté 31) .24 of the integrated circuits' (Figure 5b). This operation can be done by mechanical cutting, by laser cutting or by any other technique. The last step consists in completely encapsulating the rear face of the substrate 22 and filling in the trenches made previously (FIG. 5c). This step can be carried out by molding, by exemption or any other technique of depositing insulation (noted 31).
Les figures 6a à 6g illustrent un deuxième mode de fabrication de boîtier WLCSP. Ce mode de fabrication comporte la reprise de contact face avant/face arrière et l' encapsulation complète des circuits intégrés .FIGS. 6a to 6g illustrate a second method of manufacturing the WLCSP package. This manufacturing method includes contact resumption front / rear face and the complete encapsulation of integrated circuits.
Les étapes de formation de la couche de relaxation sur les circuits intégrés et du reroutage sont identiques au procédé décrit précédemment (voir figures 4a à 4c) -. on obtient le dispositif présenté dans la figure 6a. Ici, la délimitation des plots d'accrochage 40 des billes 47 a une forme différente : chaque plot d'accrochage 40 est entouré d'une tranchée pour mieux délimiter la zone de soudure. Puis on effectue les mêmes étapes que celles présentées dans les figures 4d à 4f et on obtient le dispositif de la figure 6b : les zones en retrait et les puits d'accès au-dessus des plots d' entrée-sortie ont été comblés par dépôt d'une couche isolante 49.The stages of formation of the relaxation layer on the integrated circuits and of the rerouting are identical to the method described previously (see FIGS. 4a to 4c). the device presented in FIG. 6a is obtained. Here, the delimitation of the attachment pads 40 of the balls 47 has a different shape: each attachment pad 40 is surrounded by a trench to better define the weld zone. Then the same steps are carried out as those presented in FIGS. 4d to 4f and the device of FIG. 6b is obtained: the recessed areas and the access shafts above the input-output pads have been filled by deposition an insulating layer 49.
Puis, pour rendre possible la reprise de contact face avant/face arrière, on peut commencer par diminuer l'épaisseur du substrat 42 (figure 6c) . Cette étape n'est pas obligatoire, mais elle facilite la reprise de contact avec la face avant du substrat et la séparation ultérieure des boîtiers-puces. Après, selon la figure 6d, on réalise des tranchées dans la face arrière du substrat afin de délimiter les circuits intégrés (on effectue des découpes I jusqu'à atteindre la couche de passivation 44) et reprendre contact avec les plots d'entrée/sortie (on effectue des découpes II jusqu'à atteindre les plots 43) . Cette étape peut être réalisée par découpe ou par gravure. Si on opte pour la technique de gravure, on réalisera des puits au niveau des plots d' entrée/sortie 43.Then, to make contact resumption front face / rear face, one can start by reducing the thickness of the substrate 42 (FIG. 6c). This step is not compulsory, but it facilitates the resumption of contact with the front face of the substrate and the subsequent separation of the chip-boxes. Then, according to FIG. 6d, trenches are made in the rear face of the substrate in order to delimit the integrated circuits (cuts I are made until the passivation layer 44 is reached) and contact again with the input / output pads (cuts II are made until the studs 43 are reached). This step can be carried out by cutting or engraving. If you opt for the etching technique, you will make wells at the level of the input / output pads 43.
Ensuite, il faut isoler la face arrière du substrat en déposant une couche isolante 51 dans les découpes ; cette étape peut être réalisée par moulage ou sérigraphie. Pour être certain d'isoler les plots, les tranchées au niveau desdits plots sont partiellement remplies (non représenté sur la figure) . Pour la reprise de contact sur les plots d'entrée/sortie, l'étape de métallisation peut être précédée d'une étape de gravure (par exemple par laser, par plasma...) de la couche isolante au niveau des plots.Then, it is necessary to isolate the rear face of the substrate by depositing an insulating layer 51 in the cutouts; this step can be carried out by molding or screen printing. To be sure to isolate the studs, the trenches at said studs are partially filled (not shown in the figure). For contact resumption on the input / output pads, the metallization step may be preceded by an etching step (for example by laser, by plasma, etc.) of the insulating layer at the pads.
Puis on effectue la métallisation de la face arrière du substrat selon la même méthode que décrit précédemment (figure 6e) : on obtient une couche métallique 55 qui recouvre la totalité de la face arrière du substrat 42.Then the metallization of the rear face of the substrate is carried out according to the same method as described above (FIG. 6e): a metallic layer 55 is obtained which covers the entire rear face of the substrate 42.
Ensuite, on isole les métallisations 55 par rodage, par polissage mécano-chimique ou par toute autre technique de la surface de la face arrière du substrat. Cette étape peut être réalisée après une étape d' encapsulation (étape non dessinée) . Enfin, on effectue le billage du substrat en plaçant les billes fusibles 47 sur les plots d'accrochage 40 (figure 6f) et on réalise la singularisation des boîtiers-puces (figure 6g) en découpant au niveau des découpes I .Then, the metallizations 55 are isolated by lapping, by chemical mechanical polishing or by any other technique from the surface of the rear face of the substrate. This step can be carried out after an encapsulation step (step not drawn). Finally, the substrate is billed by placing the fusible balls 47 on the hooking pads 40 (FIG. 6f) and the singularization of the chip boxes (FIG. 6g) is carried out by cutting at the cutouts I.
D'autres variantes de boîtiers-puces peuvent être obtenues .Other variants of chip boxes can be obtained.
Par exemple, selon un mode de réalisation particulier, on peut assembler plusieurs de ces boîtiers-puces présentant un reroutage face avant/face arrière et combler les interstices par de la résine « underfill » . On peut aussi réaliser l'assemblage après découpe des boîtiers-puces. On obtient ainsi un module en trois dimensions.For example, according to a particular embodiment, it is possible to assemble several of these chip boxes having a rerouting on the front / rear face and to fill the interstices with “underfill” resin. It is also possible to assemble after cutting the chip boxes. A three-dimensional module is thus obtained.
On peut également réaliser l' encapsulation totale du boîtier-puce, c'est-à-dire l' encapsulation de la face avant et de la face arrière du substrat, réalisée après avoir éventuellement réduit l'épaisseur du substrat (figure 7) . Dans cet exemple, le substrat 72 comporte des circuits intégrés composés de plots d'entrée/sortie 73 et d'une couche de passivation 74 ; les circuits intégrés sont ensuite recouverts d'une couche 78 relaxant les contraintes et présentant des puits d'accès laissant accessibles les plots d'entrée/sortie 73, lesdits plots d'entrée/sortie et les billes fusibles 77 surplombant la couche relaxante 78 étant reliés par des lignes de reroutage 75. Une couche isolante 79 remplit les puits d'accès et les zones en retrait de la face avant du substrat, et une couche isolante 91 recouvre la face arrière du substrat.It is also possible to carry out the total encapsulation of the chip housing, that is to say the encapsulation of the front face and of the rear face of the substrate, carried out after possibly reducing the thickness of the substrate (FIG. 7). In this example, the substrate 72 includes integrated circuits composed of input / output pads 73 and a passivation layer 74; the integrated circuits are then covered with a layer 78 relieving the stresses and having access wells leaving the input / output pads 73 accessible, said input / output pads and the fusible balls 77 overhanging the relaxing layer 78 being connected by rerouting lines 75. An insulating layer 79 fills the access shafts and the recessed areas of the front face of the substrate, and a insulating layer 91 covers the rear face of the substrate.
Il est à noter que les versions illustrées par les figures 6g et 7 ne sont pas limitatives, les deux versions pouvant notamment être couplées. It should be noted that the versions illustrated in FIGS. 6g and 7 are not limiting, the two versions being able in particular to be coupled.
BIBLIOGRAPHIEBIBLIOGRAPHY
[1] Dr Philip GARROU, Packaging and Manufacturing Technologies Society, ref IEEE Components, octobre 2000.[1] Dr Philip GARROU, Packaging and Manufacturing Technologies Society, ref IEEE Components, October 2000.
[2] Atsushi KAZAMA, Ωeveloppment of Low-Cost and Highly Reliable Wafer Process Package, ref IEEE, Electronic Components and Technology Conférence, 2001. [2] Atsushi KAZAMA, Ωeveloppment of Low-Cost and Highly Reliable Wafer Process Package, ref IEEE, Electronic Components and Technology Conférence, 2001.

Claims

REVENDICATIONS
1- Procédé de réalisation d'un boîtier à la taille d'une puce électronique et réalisé à l'échelle du substrat, le substrat (22, 42, 72) comportant au moins une puce et ladite au moins une puce possédant des plots d'entrée-sortie (23, 43, 73) sur une face du substrat dite face avant, le procédé comprenant les étapes suivantes : a) formation, au moyen d'un moule ou d'un pochoir complexe, d'une couche isolante de relaxation de contraintes (28, 48, 78) sur ladite face avant, ladite couche de relaxation recouvrant la face avant du substrat avec un relief présentant des puits d'accès au niveau des plots d'entrée-sortie, et ailleurs, des parties en saillie destinées à relaxer les contraintes, chaque partie en saillie ayant une forme étagée comprenant au moins une zone proéminente et au moins une zone, en retrait par rapport à ladite zone proéminente, destinée à supporter un plot de connection électrique (30, 40), b) formation de pistes électriquement conductrices (25, 45, 75) sur la couche de relaxation pour connecter les plots d'entrée/sortie aux plots de connection électrique correspondants, c) formation de moyens de contact électrique (27, 47, 77) vers l'extérieur sur les plots de connection électrique.1- A method of producing a box the size of an electronic chip and produced on the scale of the substrate, the substrate (22, 42, 72) comprising at least one chip and said at least one chip having dots input-output (23, 43, 73) on a face of the substrate called the front face, the method comprising the following steps: a) forming, by means of a complex mold or stencil, an insulating layer of stress relaxation (28, 48, 78) on said front face, said relaxation layer covering the front face of the substrate with a relief having access wells at the level of the input-output pads, and elsewhere, parts in protrusion intended to relax the stresses, each protruding part having a stepped shape comprising at least one protruding zone and at least one zone, set back from said protruding zone, intended to support an electrical connection pad (30, 40), b) formation of electrically conductive tracks (25, 45, 75) on the relaxation layer to connect the input / output pads to the corresponding electrical connection pads, c) formation of electrical contact means (27, 47, 77) outward on the pads electrical connection.
2. Procédé de fabrication selon la revendication 1 caractérisé en ce -qu'il comprend en outre, entre les étapes b) et c) , une étape de formation d'une couche d' encapsulation (29, 49, 79) sur la couche de relaxation avec exposition des plots de connection électrique.2. Manufacturing method according to claim 1 characterized in that it comprises in addition, between steps b) and c), a step of forming an encapsulation layer (29, 49, 79) on the relaxation layer with exposure of the electrical connection pads.
3. Procédé de fabrication selon la revendication 1 caractérisé en ce que, pour former la couche de relaxation des contraintes (28, 48, 78) à l'aide d'un moule, on suit les étapes suivantes : 1) remplir le moule avec un polymère relaxant déterminé ou appliquer ledit polymère directement sur la face avant du substrat,3. Manufacturing method according to claim 1 characterized in that, to form the stress relaxation layer (28, 48, 78) using a mold, the following steps are followed: 1) fill the mold with a determined relaxing polymer or apply said polymer directly to the front face of the substrate,
2) aligner le moule sur la face avant du substrat,2) align the mold on the front face of the substrate,
3) presser le moule sur la face avant du substrat, 4) recuire le polymère,3) press the mold on the front face of the substrate, 4) anneal the polymer,
5) retirer le moule.5) remove the mold.
4. Procédé de fabrication selon la revendication 1 caractérisé en ce que, pour former la couche de relaxation des contraintes (28, 48, 78) à l'aide d'un pochoir, on suit les étapes suivantes :4. Manufacturing method according to claim 1 characterized in that, to form the stress relaxation layer (28, 48, 78) using a stencil, the following steps are followed:
1) appliquer le pochoir sur la face avant du substrat,1) apply the stencil on the front face of the substrate,
2) remplir les orifices du pochoir avec un polymère relaxant déterminé,2) fill the holes in the stencil with a specific relaxing polymer,
3) recuire le polymère et séparer le pochoir du substrat .3) anneal the polymer and separate the stencil from the substrate.
5. Procédé de fabrication selon la revendication 3 ou 4 caractérisé en ce que ledit polymère relaxant déterminé est choisi parmi le groupe constitué du polyi ide, du BCB ou de tout autre polymère susceptible de relaxer les contraintes .5. The manufacturing method according to claim 3 or 4 characterized in that said determined relaxing polymer is chosen from the group consisting of polyide, BCB or any other polymer capable of relaxing stresses.
6. Procédé de fabrication selon la revendication 3 ou 4 caractérisé en ce que, après l'obtention de la couche relaxant les contraintes (28, 48, 78) sur la face avant du substrat, on élimine les résidus de polymère se trouvant sur les plots d'entrée/sortie (23, 43, 73).6. Manufacturing method according to claim 3 or 4 characterized in that, after obtaining the stress relieving layer (28, 48, 78) on the front face of the substrate, the polymer residues on the input / output pads (23, 43, 73).
7. Procédé de abrication selon la revendication 1 caractérisé en ce que l'étape de formation de pistes électriquement conductrices (25, 45, 75) comprend les étapes suivantes : a) dépôt d'un matériau conducteur sur la face avant du substrat recouverte de la couche de relaxation (28, 48, 78), b) séparation des lignes de reroutage et formation des plots de connexion électrique (30, 40) par élimination du matériau conducteur situé au niveau de la (des) zone (s) proéminente (s) des parties en saillie de la couche de relaxation par rodage mécanique ou par polissage mécano-chimique.7. The manufacturing method according to claim 1 characterized in that the step of forming electrically conductive tracks (25, 45, 75) comprises the following steps: a) depositing a conductive material on the front face of the substrate covered with the relaxation layer (28, 48, 78), b) separation of the rerouting lines and formation of the electrical connection pads (30, 40) by elimination of the conductive material located at the level of the prominent zone (s) ( s) protruding parts of the relaxation layer by mechanical running-in or by chemical mechanical polishing.
8. Procédé de fabrication selon la revendication 1 caractérisé en ce que l'étape de formation de pistes électriquement conductrices (25, 45, 75) est réalisée par dépôt chimique de matériau conducteur dans les puits d'accès aux plots d'entrée- sortie et dans les zones en retrait par rapport à la (les) zone (s) proéminente (s) des parties en saillie de la couche relaxante (28, 48, 78) .8. Manufacturing method according to claim 1 characterized in that the step of forming electrically conductive tracks (25, 45, 75) is carried out by chemical deposition of conductive material in the access wells to the input-output pads and in areas set back from the (the) prominent area (s) of the projecting parts of the relaxing layer (28, 48, 78).
9. Procédé de fabrication selon la revendication précédente caractérisé en ce que le matériau conducteur est un métal.9. The manufacturing method according to the preceding claim characterized in that the conductive material is a metal.
10. Procédé de fabrication selon la revendication 1 caractérisé en ce que l'étape de formation de pistes électriquement conductrices (25,10. The manufacturing method according to claim 1 characterized in that the step of forming electrically conductive tracks (25,
45, 75) comprend les étapes suivantes : a) dépôt d'un matériau conducteur sur la face avant du substrat recouverte de la couche relaxante, b) 1ithog aphie, c) gravure chimique, d) décapage .45, 75) comprises the following steps: a) deposition of a conductive material on the front face of the substrate covered with the relaxing layer, b) 1ithog aphia, c) chemical etching, d) pickling.
11. Procédé de fabrication selon l'une quelconque des revendications 7 et 10, caractérisé en ce que le dépôt d'un matériau conducteur est une métallisation.11. The manufacturing method according to any one of claims 7 and 10, characterized in that the deposition of a conductive material is a metallization.
12. Procédé de abrication selon la revendication 1 caractérisé en ce que l'étape de formation de pistes électriquement conductrices (25, 45, 75) comprend les étapes suivantes : a) métallisation lithographique de la face avant du substrat recouverte de la couche relaxante, b) électrolyse, c) décapage, d) gravure chimique. 12. The manufacturing method according to claim 1 characterized in that the step of forming electrically conductive tracks (25, 45, 75) comprises the following steps: a) lithographic metallization of the front face of the substrate covered with the relaxing layer, b) electrolysis, c) pickling, d) chemical etching.
13. Procédé de f brication selon la revendication 2 caractérisé en ce que l'étape de formation d'une couche d' encapsulation (29, 49, 79) comprend les étapes suivantes : a) dépôt d'une couche de polymère sur toute la surface avant du substrat recouverte de la couche de relaxation, b) planarisation de la face avant du substrat, c) libération des plots de connection électrique (30, 40) .13. Brication method according to claim 2 characterized in that the step of forming an encapsulation layer (29, 49, 79) comprises the following steps: a) depositing a layer of polymer over the entire front surface of the substrate covered with the relaxation layer, b) planarization of the front face of the substrate, c) release of the electrical connection pads (30, 40).
14. Procédé de f brication selon la revendication 2 caractérisé en ce que l'étape de formation d'une couche d' encapsulation (29, 49, 79) comprend les étapes suivantes : a) planarisation de la face avant du substrat, b) remplissage des puits d'accès et des zones en retrait de la face avant du substrat avec un polymère épais, c) libération des plots de connection électrique (30, 40) .14. Brication method according to claim 2 characterized in that the step of forming an encapsulation layer (29, 49, 79) comprises the following steps: a) planarization of the front face of the substrate, b) filling the access shafts and the recessed areas of the front face of the substrate with a thick polymer, c) releasing the electrical connection pads (30, 40).
15. Procédé de fabrication selon la revendication 1 caractérisé en ce que les moyens de contact électrique (27, 47, 77) vers l'extérieur sur les plots de connection électrique (30, 40) sont des billes fusibles.15. The manufacturing method according to claim 1 characterized in that the electrical contact means (27, 47, 77) outward on the electrical connection pads (30, 40) are fusible balls.
16. Procédé de fabrication selon la revendication précédente caractérisé en ce que les billes fusibles sont installées sur les plots de connection électrique (30, 40) à l'aide d'une technique choisie parmi l' électrolyse d'alliage fusible, la sérigraphie de pâte à braser, le transfert de billes.16. Manufacturing method according to the preceding claim characterized in that the fusible balls are installed on the electrical connection pads (30, 40) using a technique chosen from electrolysis of fusible alloy, screen printing of solder paste, transfer of balls.
17. Procédé de fabrication selon la revendication 1 caractérisé en ce que les moyens de contact électrique (27, 47, 77) vers l'extérieur sur les plots de connection électrique (30, 40) sont choisis parmi les films et les colles anisotropes conducteurs .17. The manufacturing method according to claim 1 characterized in that the electrical contact means (27, 47, 77) outward on the electrical connection pads (30, 40) are chosen from films and anisotropic conductive adhesives .
18. Procédé de fabrication selon l'une quelconque des revendications 1 et 2 caractérisé en ce qu' il comprend en outre une étape de séparation des boîtiers à la taille d'une puce électronique réalisés à l'échelle du substrat.18. Manufacturing method according to any one of claims 1 and 2 characterized in that it further comprises a step of separating the packages to the size of an electronic chip made on the scale of the substrate.
19. Procédé de fabrication selon la revendication 1 caractérisé en ce que, avant ou après la formation des moyens de contact électrique (27, 47, 77) vers l'extérieur sur les plots de connection électrique, la face arrière du substrat (22, 42, 72) est aminci par rodage, par polissage mécano-chimique ou toute autre technique.19. The manufacturing method according to claim 1 characterized in that, before or after the formation of the electrical contact means (27, 47, 77) outwards on the electrical connection pads, the rear face of the substrate (22, 42, 72) is thinned by running in, by chemical mechanical polishing or any other technique.
20. Procédé de fabrication selon l'une quelconque des revendications 1 ou 2 caractérisé en ce qu'il est complété par les étapes suivantes : a) réalisation de tranchées à partir de la face arrière du substrat (42) jusqu'à atteindre les couches métalliques représentés par les plots d'entrée-sortie (43) des circuits intégrés ou par les pistes électriquement conductrices (45) , b) dépôt, éventuellement localisé, d'une couche métallique (55) sur la face arrière du substrat, c) élimination de la métallisation située en surface de la face arrière du substrat.20. The manufacturing method according to any one of claims 1 or 2 characterized in that it is supplemented by the following steps: a) making trenches from the rear face of the substrate (42) until reaching the layers metallic elements represented by the input-output pads (43) of the integrated circuits or by the electrically conductive tracks (45), b) deposit, possibly localized, of a metallic layer (55) on the rear face of the substrate, c) elimination of the metallization located on the surface of the rear face of the substrate.
21. Moule ou pochoir complexe caractérisé en ce qu'il est destiné à réaliser un boîtier à la taille d'une puce à l'aide du procédé selon l'une quelconque des revendications 1 à 20.21. Complex mold or stencil characterized in that it is intended to produce a housing the size of a chip using the method according to any one of claims 1 to 20.
22. Moule ou pochoir complexe selon la revendication 21 caractérisé en ce qu'il est réalisé à l'aide d'au moins une technique choisie parmi la gravure humide ou sèche, l'éleσtroformage, le collage de plusieurs films polymères percés ou non, le moulage, la gravure laser.22. Complex mold or stencil according to claim 21, characterized in that it is produced using at least one technique chosen from wet or dry etching, eletroforming, bonding of several polymer films, pierced or not, molding, laser engraving.
23. Moule ou pochoir complexe selon la revendication 21 ou 22 caractérisé en ce qu' il est réalisé en silicium, en métal, en polymère.23. Complex mold or stencil according to claim 21 or 22 characterized in that it is made of silicon, metal, polymer.
24. Boîtier à la taille d'une puce et réalisé à l'échelle du substrat, caractérisé en ce qu'il est réalisé par le procédé selon l'une quelconque des revendications 1 à 20. 24. Box the size of a chip and produced on the scale of the substrate, characterized in that it is produced by the method according to any one of claims 1 to 20.
EP03809999A 2002-12-18 2003-12-17 Method for re-routing lithography-free microelectronic devices Withdrawn EP1573805A2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0216117 2002-12-18
FR0216117A FR2849270A1 (en) 2002-12-18 2002-12-18 Wafer level chip scale package manufacture comprises use of mold or complex stencil to make stress relaxing insulation layer for front face of wafer
PCT/FR2003/050188 WO2004057667A2 (en) 2002-12-18 2003-12-17 Method for re-routing lithography-free microelectronic devices

Publications (1)

Publication Number Publication Date
EP1573805A2 true EP1573805A2 (en) 2005-09-14

Family

ID=32406169

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03809999A Withdrawn EP1573805A2 (en) 2002-12-18 2003-12-17 Method for re-routing lithography-free microelectronic devices

Country Status (4)

Country Link
US (1) US20060128134A1 (en)
EP (1) EP1573805A2 (en)
FR (1) FR2849270A1 (en)
WO (1) WO2004057667A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070096281A1 (en) * 2005-11-02 2007-05-03 Greenberg Robert J Implantable microelectronic device and method of manufacture
US8143173B2 (en) * 2006-11-22 2012-03-27 Seiko Epson Corporation Method for manufacturing semiconductor device
EP2304783A1 (en) * 2008-05-28 2011-04-06 MVM Technologies, Inc. Maskless process for solder bumps production
CN103065985B (en) * 2011-10-21 2015-04-22 中国科学院上海微系统与信息技术研究所 Double-face wiring packaging wafer level large thickness photosensitive benzocyclobutene (BCB) back manufacturing method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100306842B1 (en) * 1999-09-30 2001-11-02 윤종용 Redistributed Wafer Level Chip Size Package Having Concave Pattern In Bump Pad And Method For Manufacturing The Same
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
JP4174174B2 (en) * 2000-09-19 2008-10-29 株式会社ルネサステクノロジ Semiconductor device, manufacturing method thereof, and semiconductor device mounting structure
US6444489B1 (en) * 2000-12-15 2002-09-03 Charles W. C. Lin Semiconductor chip assembly with bumped molded substrate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004057667A2 *

Also Published As

Publication number Publication date
WO2004057667A3 (en) 2004-08-12
WO2004057667A2 (en) 2004-07-08
FR2849270A1 (en) 2004-06-25
US20060128134A1 (en) 2006-06-15

Similar Documents

Publication Publication Date Title
EP2162907B1 (en) Device including components embedded in cavities of a receptor plate and corresponding method
EP2038929B1 (en) Method for producing a matrix of individual electronic components and matrix produced thereby
TW200947659A (en) Semiconductor apparatus and method for manufacturing the same
FR2966283A1 (en) METHOD FOR PRODUCING A COLLAGE STRUCTURE
FR2833106A1 (en) Integrated circuit with electromechanical component includes cavity defined between two substrates for auxiliary component
CN102163589B (en) There is the wafer-level package device of self assembling type resilient lead
FR3018953A1 (en) INTEGRATED CIRCUIT CHIP MOUNTED ON AN INTERPOSER
FR2946795A1 (en) METHOD FOR POSITIONING CHIPS WHEN MANUFACTURING A RECONSTITUTED PLATE
EP2610907A1 (en) Stacked electronic device and method for manufacturing such an electronic device
EP3109900B1 (en) Method for manufacturing a plurality of dipoles in the form of islands with self-aligned electrodes
WO2005086232A1 (en) Microelectronic interconnect device comprising localised conductive pins
US20010051421A1 (en) Method of manufacturing a semiconductor device
WO2004057667A2 (en) Method for re-routing lithography-free microelectronic devices
FR2502399A1 (en) SEMICONDUCTOR DEVICE HAVING REPORTED CONTACT WITH LOW RESISTANCE
EP3809467B1 (en) Method for collective curvature of a set of electronic chips
FR2940521A1 (en) COLLECTIVE MANUFACTURING METHOD OF ELECTRONIC MODULES FOR SURFACE MOUNTING
FR3036226A1 (en) CONNECTION BY CONTAINMENT OF A MATERIAL BETWEEN TWO CONTACT ELEMENTS
FR2864342A1 (en) Electronic components e.g. ball grid array type encapsulation packages, connecting method, involves connecting conducting zones of external outputs of components appearing on wafer`s connection surface
WO2003081669A1 (en) Integrated circuit module and method for making same
WO2018002368A1 (en) Electronic device comprising an integrated bank of passive components
WO2008012481A1 (en) Process for fabricating an encapsulated integrated circuit and associated encapsulated integrated circuit
FR2848339A1 (en) Adhesion of two elements comprises nickel-silicon welding at low temperature, for encapsulation of components in integrated circuits and microelectromechanical systems
FR2969374A1 (en) METHOD FOR ASSEMBLING TWO INTEGRATED CIRCUITS AND CORRESPONDING STRUCTURE
FR2970117A1 (en) Method for manufacturing semiconductor chip of integrated circuit, involves coating non-oxidizable metal layer with certain parts of metal pads via electrolytic deposition, where metal layer is selected from one of nickel and alloys of tin
FR3093861A1 (en) Chip coating process

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050526

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK

DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20060701