Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of DC power input into DC power output
  • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
  • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
  • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
  • H02M1/4208—Arrangements for improving power factor of AC input
  • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
  • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
  • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

• the technique is applied to a PFC (Power Factor Correction) boost converter in U.S. Patent No. 5,886,586.
• the output voltage of the converter is sensed, compared to a reference voltage and supplied to an integrator stage, which is reset for each control cycle as set by a system clock.
• the integrator output is then compared in a comparator to the sensed input current in the converter and the output of the comparator is provided to control a pulse width modulator, whose output controls the boost converter switch.
• the switch controls the current supplied to the load so that the input ac line current is in phase with the input ac line voltage, i.e., the converter with attached load has a power factor of substantially unity and thus appears purely resistive, resulting in optimum power efficiency as well as reduced harmonics.
• FIG. 1 depicts a system level block diagram representation of a typical prior art active power factor correction system operating in a fixed frequency, continuous conduction mode (CCM) boost converter topology.
• the system consists of a continuous conduction mode control integrated circuit 1, based on a multiplier approach, with discrete gate drive circuitry 3 and discrete power switch 5.
• This control method based on current mode control, employs the use of a multiplier circuit, input current sensing, input voltage sensing, and output voltage sensing.
• the analog multiplier creates a current programming signal by multiplying the rectified line voltage by the output of a voltage error amplifier such that the current programming signal has the shape of the input voltage, and average amplitude, which ultimately controls the output voltage of the boost converter.
• the current loop is programmed by the rectified line voltage such that the input of the converter appears resistive.
• the output voltage is controlled by changing the average amplitude of the current programming signal. The result is a regulated output voltage and sinusoidal input current in phase and proportional to the input voltage.
• Controller IC This increases the value of such a controller compared to conventional multiplier based controllers given that there is more functionality per unit area of silicon.
• the OCC technique dramatically simplifies the continuous conduction mode (CCM) PFC control function compared to conventional "multiplier" based
• CCM PFC controllers such as the prior art Unitrode/TI UC3854.
• the number of package pins are reduced dramatically since the OCC technique does not require line voltage sensing and does not need a complicated multiplier circuit with all its associated external components.
• the simplicity of this control method thus allows a higher level of integration while allowing use of practical pre-existing power packagii along with the additional peripheral functions referred to above.
• the power switching element may also be integrated in the package.
• An example of a packaging method that can be employed is shown in International Publication WO 01/39266 published May 31, 2001.
• the present invention thus relates to an active power factor correction boost converter peferably operating in the continuous conduction mode (CCM) and incorporating selected ones of circuits for inrush current limiting, fan motor speed control and housekeeping power supply control.
• the invention is preferably implemented for continuous conduction mode because this is the most complicated PFC circuit, typically requiring many external components and package pins for the controller.
• the IC is preferably packaged with a MOSFET or IGBT Die preferably using packaging methods in WO 01/39266 above.
• PFC applications there is often a need to limit the inrush current into the power supply system since large electrolytic bulk capacitors are often used to smooth out the output of the PFC Circuit.
• One method to limit inrush current is to place an inrush limiting resistor in series with the DC bus. This resistor is then by-passed using an electromagnetic relay or an active device such as a MOSFET or a thyristor, after sensing the inrush current level and comparing the magnitude with a fixed safe reference level.
• the PFC controller provides integrated circuitry which, 1. Senses inrush current,
• the inrush currc enable signal is provided using an unused pin to a relay or an active switch after the sensed current level has fallen below a prescribed safe limit.
• a second peripheral feature included in the PFC IC is a fan speed controller.
• a fan is often used to provide power supply cooling. Often this feature has to be implemented with external circuitry dedicated to fan speed control. This feature can be included onboard the PFC controller given that the load conditions of the power supply are all available internal to the PFC controller.
• the controller also has an on-board oscillator, which can be used for the Fan speed control PWM signal eliminating redundant switching circuits.
• the fan speed can be directly controlled as a function of the PFC load current thus eliminating the need for complicated control schemes.
• the implementation of the fan speed controller is a stream of PWM pulses going from 0 to 100% duty cycle linearly proportional to the load current as seen by the PFC controller. Fixed speeds can also be programmed and activated under specific % load.
• a third peripheral feature that may be included in the PFC IC is a housekeeping power supply controller. All converter circuits need housekeeping power supplies to power the control IC and ancillary circuit functions.
• the housekeeping power supply is typically driven from a dedicated controller.
• the present invention integrates the controller function of the housekeeper supply inside the same control IC as the PFC function. The benefits are:
• the present invention thus relates to an active Power Factor Correction boost converter IC preferably operating in a continuous conduction mode (CCM) and including onboard at least one of an inrush current limiting controller, a fan speed controller and a housekeeping power supply controller.
• CCM continuous conduction mode
• the inrush current limit control circuit makes use of an existing current sensing resistor in order to measure the inrush current. It uses this information to trigger the by-pass element and sequence startup operation.
• the fan speed controller regulates fan speed linearly as a function of load current sensed using the existing current sensing circuitry including the current sensing resistor.
• the fan speed can also be controlled using predefined duty cycles steps (speeds) for a given predetermined % load. Since the load information is available inside the PFC controller, this function is greatly simplified.
• the housekeeping controller again utilizes the internal oscillator to provide an independent PWM control circuit specifically for a housekeeping power supply function.
• the existing VCC pin on the PFC controller is also used as the feedback pin for the housekeeping power supply output. This ensures the housekeeping power supply regulation is within the rating of the PFC IC.
• a power factor corrected boost converter circuit comprising: a rectifier connectable to an ac input and having a rectified dc output provided across a dc bus, an inductor having first and second terminals connected in one leg of the dc bus, a first terminal of the inductor coupled to the output of said rectifier, an integrated circuit comprising a control circuit for controlling a switch, the integrated circuit comprising a housing enclosing the control circuit, the integrated circuit having a power terminal, a ground terminal, a first control input terminal coupled to an output of the converter circuit, a second control input terminal coupled to a sensor for sensing current in the dc bus and further having an output terminal connected to the switch, a boost rectifier diode having a first terminal, the first terminal of the diode coupled to the second terminal of the inductor; the diode having a second terminal; and a storage capacitor connected to the second terminal of the diode, wherein the control circuit comprises a one cycle control circuit having an
• the invention comprises power factor corrected boost converter circuit comprising a rectifier connectable to an ac input and having a rectified dc output provided across a dc bus, an inductor having first and second terminals connected in one leg of the dc bus, a first terminal of the inductor coupled to the output of said rectifier, an integrated circuit comprising a control circuit for controlling a switch, the integrated circuit comprising a housing enclosing the control circuit, the integrated circuit having a power terminal, a ground terminal, a first control input terminal coupled to an output of the converter circuit, and a second control input terminal coupled to a sensor for sensing current in the dc bus and further having an output terminal connected to the switch, a boost rectifier diode having a first terminal, the first terminal of the diode coupled to the second terminal of the inductor, the diode having a second terminal; and a storage capacitor connected to the second terminal of the diode, wherein the control circuit comprises a one cycle control circuit having an integrator
• the invention comprises a power factor corrected boost converter circuit comprising a rectifier connectable to an ac input and having a re and second terminals connected in one leg of the dc bus, a first terminal of the inductor coupled to the output of said rectifier, an integrated circuit comprising a control circuit controlling a switch, the integrated circuit comprising a housing enclosing the control circuit, the integrated circuit having a power terminal, a ground terminal, a first control input terminal coupled to an output of the converter circuit, and a second control input terminal coupled to a sensor for sensing current in the dc bus and further having an output terminal connected to the switch, a boost rectifier diode having a first terminal, the first terminal of the diode coupled to the second terminal of the inductor, the diode having a second terminal; and a storage capacitor connected to the second terminal of the diode, wherein the control circuit comprises a one cycle control circuit having an integrator reset by a clock signal for each cycle of the clock signal, the integrator
• the invention also relates to an integrated circuit controller for a PFC boost converter.
• Fig. 1 is a block diagram of a prior art multiplier-based CCM PFC boost converter circuit
• Fig. 2 is a block diagram of a CCM PFC boost converter circuit using the OCC technique wherein the switch and controller are housed in a single module, as described in the above identified U.S. application No. 10/319,982;
• Fig. 3 shows one application of the integrated circuit of Fig. 2;
• Fig. 4 shows the block diagram of the integrated circuit of Fig. 2;
• Fig. 4A shows how power and reference voltages are generated for the integrated circuit of Fig. 2;
• Fig. 5 shows one embodiment of the invention incorporating both inrush current limiting and fan speed control
• Fig. 6 shows a second embodiment of the invention incorporating inrush current limiting, fan speed control and housekeeping power supply control.
• Figure 2 depicts a system level block diagram representation based on the OCC active power factor correction technique operating in a fixed frequency, continuous conduction mode boost converter topology.
• CCM the current in the inductor L is never allowed to become zero.
• the power switch 10 and the OCC based PFC control circuit 20 with on board power switch driver 30 are integrated into a single package 40 capable of dissipating appropriate heat from the device to a heat sink.
• Various power packages can be employed using this technique since the number of pins required to implement a full CCM PFC boost converter is reduced with the use of the OCC technique.
• the control circuit 20 is based on the OCC method in which the multiplier and input voltage sensing referred to in the prior art circuit of Fig. 1 are not required. This allows package pins and external components of the IC 40 to be reduced.
• the OCC concept is realized with a simple linear circuit incorporating integration-reset control, in which the duty cycle of the switch 10 is controlled in real-time such that the average value of the switched variable in each cycle is equal to or proportional to a control reference.
• the output voltage of the converter is compared to the control reference by an error amplifier. This error signal is integrated. The magnitude of the error controls the slope of the integrator output, which is then compared to the sensed input current to control the duty cycle of the switch.
• This control method forces the input of the converter to appear resistive, thus forcing a sinusoidal input current in phase and proportional to the input voltage, and providing a regulated DC output voltage. Integrating the controller along with the power switch in one package simplifies the complicated task of designing a continuous conduction mode PFC circuit as compared to traditional discrete multiplier based CCM PFC controllers.
• the rectifier block R provides a rectified dc voltage to the dc bus.
• An input capacitor Cin filters high frequency content.
• switch 10 When switch 10 is on, electromagnetic energy is stored in inductor L. When the switch 10 is turned off, the stored energy in inductor L is transferred via high frequency rectifier diode D to storage capacitor C out , providing power to the load. When the switch 10 again is on, diode D is reverse biased and storage capacitor C out provides power to the load.
• the duty cycle of switch 10 is controlled by
• Fig. 3 shows details of one implementation of the integrated circuit 40 applied to a PFC CCM boost converter and Fig. 4 shows the block diagram of IC 40.
• IC 40 is preferably provided with power by a power supply PS which receives power from the DC bus.
• a voltage regulator circuit comprising a resistor RX and zener diode DZ1 can be employed to provide internal power (VCC 5 V). See Fig. 4A.
• a reference voltage Vref for the error amplifier can also be provided by a similar circuit including a resistor RY and zener diode DZ2 as shown in Fig. 4A.
• the output voltage is sensed by resistor divider R réelle R 2 and provided to input VFB of IC 40, which is one input to an error amplifier 50.
• the other input of error amplifier 50 is the reference voltage Vref .
• the error amplifier 50 generates an error signal Ve.
• Ve is provided to the input of an integrator stage 70.
• the output of the integrator is provided to one input of comparator 75, where it is compared to the sensed input current, provided by the output of current buffer 78 which is fed by current sense amplifier 79.
• the input current is converted to a voltage by resistor Rs and provided to input ISNS.
• a peak current limiter 81 operates to limit the current sensed to a prec provided to the output of comparator 75.
• the output of the comparator 75 is provided to a driver stage, e.g., a clocked SR flip flop 80, the output of which is provided to control the conduction time of switch 10.
• a system clock 85 controls the system frequency.
• the output of flip flop 80 is thus a pulse width modulated signal whose pulse width determines the on time of switch 10.
• the output of the integrator 70 which is responsive to the average value of the variation of the output voltage from the desired reference V ref, is compared to the input current waveform (as determined by the voltage drop across Rs) by comparator 75 to reset flip flop 80 when the integrator output exceeds the sensed input current.
• FIG. 5 depicts a system level block diagram representation of the invention based on the "One Cycle Control" active power factor correction system operating in a fixed frequency, continuous conduction mode boost converter topology. Fig. 5 shows the inrush current limiting and fan motor speed control peripheral functions implemented.
• the control IC 40A is based on the "One Cycle Control" method described above.
• an inrush limiting resistor RIO is disposed in series with the DC bus.
• the resistor RIO is then by-passed using an electromagnetic relay Ul or an active device such as a MOSFET or a thyristor, after sensing the inrush current level and comparing the magnitude with a fixed safe reference level and determining it is below the safe level.
• the One Cycle Control PFC controller provides integrated circuitry which,
• the inrush current already available at the current sense pin is detected as a voltage across resistor RS and an enable signal is provided using an unused pin to a relay
• the one cycle control integrated circuit has been modified as shown at 40A to include a fan speed control and inrush current control.
• a fan speed control and inrush current control As described previously, with PFC applications there is often a need to limit the inrush current into the power supply system since large electrolytic bulk capacitors are often used to smooth out the output of the PFC circuit, for example, capacitor Cl.
• a resistor RIO is placed in series in the DC bus. Resistor RIO is then bypassed using a relay Ul or an active device such as a MOSFET or a thyristor after sensing the inrush current level and comparing the magnitude with the fixed safe reference level.
• the PFC controller provides integrated circuitry that senses the inrush current via resistor RS and compares the measured inrush current to a fixed reference level.
• the OCC control IC 40A controls transistor Ql. If the sensed inrush current is above the predetermined level, the resistor RIO disposed in series with the inductor LI limits the inrush current. Transistor Ql remains off. The contacts of the relay
• transistor Ql can alternatively be controlled such that it is turned on when the inrush current is above the predetermined level, and the relay contacts rewired so that resistor R1 is maintained in series with the inductor LI, thereby limiting the inrush current. Once the inrush current falls below the predetermined level, transistor Ql can be turned off, thereby deenergizing the relay coil and bypassing the resistor R10 so that the inrush current is no longer limited.
• a second peripheral feature included in the PFC IC 40A is a fan speed controller. Often this feature is implemented with external circuitry dedicated to fan speed control. According to the invention, this feature is included onboard the PFC controller given that the load conditions of the power supply are all available internal to the PFC controller.
• the controller also has an on-board oscillator 85 (see Fig. 4), which can be used for the fan speed control PWM signal eliminating redundant switching circuits.
• the fan speed can be directly controlled as a function of the PFC load current sensed across resistor RS thus eliminating the need for complicated control schemes.
• the output from IC 40A for fan speed control is a stream of PWM pulses going from 0 to 100% duty cycle linearly proportional to the load current sensed across RS as seen by the PFC controller. These PWM pulses are applied to the base of transistor Q2 to control the motor speed.
• the inrush current limit circuit makes use of existing circuitry sensing current via resistor RS for sensing PFC current to measure inrush current. It uses this information to trigger the by-pass element Ul or other active device and sequence startup operation.
• the fan speed controller regulates fan speed linearly as a function of load current sensed employing existing current sensing circuitry using resistor RS.
• the fan speed can also be controlled using predefined duty cycles steps (speeds) for a given predetermined % load.
• a third peripheral feature included in the PFC IC is a housekeeping power supply controller. All converter circuits need housekeeping power supplies to power the control IC and ancillary circuit functions.
• the housekeeping power supply is typically driven from a dedicated controller.
• the present invention integrates the controller function of the housekeeper inside the same control IC as the PFC function. The benefits are,
• VCC pin as the feedback pin for the housekeeping control section eliminates a redundant feedback pin. Inclusion onboard of this feature in the PFC controller is simplified given that the controller already has an oscillator and the VCC pin can be used as the feedback pin for the housekeeping section eliminating extra pins.
• the housekeeping controller utilizes the internal oscillator 85 (see Fig. 4) to create an independent PWM control circuit specifically for the housekeeping power supply function.
• the existing VCC pin on the PFC controller is also used as the feedback pin for the housekeeping power supply output. This ensures the housekeeping power supply regulation is within the rating of the PFC IC.
• Fig. 6 shows a circuit diagram employing an integrated circuit 40B which employs inrush current control and fan speed control as shown in Fig. 5 and which also includes a housekeeper power supply control.
• the circuit of Fig. 6 employs some additional functions to be described below.
• the inrush current limiting is achieved in the same way as shown in Fig. 5.
• Transistor Ql, relay Ul and resistor RIO are employed to limit the inrush current based on the sensed inrush current sensed via resistor RS.
• Fan motor speed control is accomplished by transistor Q2 in the same way as described with reference to Fig. 5, again based on the sensed PFC current sensed via resistor RS.
• the circuit of Fig. 6 also includes a housekeeper power supply control HK.
• Housekeeper power supply controller HK is controlled by an output HK
• a pulse width modulated signal is provided to the gate of a transistor comprising an FET Q3.
• the gate of transistor Q3 is pulse width modulated and drives the primary of a transformer TX1.
• the primary of transformer TX1 is coupled to output voltage VBUS.
• the secondary output of the transformer TX1 is rectified by a diode D6 and filtered by a capacitor C5.
• the output from diode D6 is then supplied to VCC to provide power to the chip 40B.
• VCC functions as a feedback pin to control the duty cycle of the PWM signal on IC output HK PWM.
• the integrated circuits 40A and 40B are shown so that they do not include the power switch QS as part of the integrated circuit.
• the drivers QH and QL are also disposed outside the integrated circuit.
• the transistors QH, QL and QS can also be incorporated in the integrated circuits 40A, 40B.
• Fig. 6 also shows a typical load enable opto-coupler OC which is controlled by a load enable signal which informs the controller that the load is enabled and ready to receive power.
• the advantages of the invention are (a) lower component count; (b) higher reliability due to lower parts count; (c) simpler PCB implementation; (d) minimized layout issues due to tight packaging of critical components of the control and power switching components; and (e) simplified design and development effort based on the simpler OCC method as opposed to the more complex multiplier based PFC controllers.
• IC 40 includes other standard functions shown in Fig. 4 such as under voltage/low voltage (UVLO) detection circuitry 101, soft start circuitry 102, necessary bias and reference voltage generators 103, thermal protection 104, circuit protection logic with automatic restart 105 (for such functions as over- current protecti drive control 30, level shifting circuitry 35 and peak current limiting gate drive circuitry 37 are also provided.
• UVLO under voltage/low voltage

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• 2003
  • 2003-10-27 US US10/694,313 patent/US7068016B2/en not_active Expired - Lifetime
  • 2003-10-29 KR KR1020057007808A patent/KR100671527B1/ko not_active Expired - Fee Related
  • 2003-10-29 EP EP20030781457 patent/EP1573786A2/de not_active Withdrawn
  • 2003-10-29 JP JP2004550191A patent/JP2006513682A/ja active Pending
  • 2003-10-29 AU AU2003288965A patent/AU2003288965A1/en not_active Abandoned
  • 2003-10-29 WO PCT/US2003/034331 patent/WO2004042793A2/en not_active Ceased

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