Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
  • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
  • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
  • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
  • H02M3/073—Charge pumps of the Schenkel-type
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
  • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
  • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
  • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
  • H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
  • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
  • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
  • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
  • H02M3/073—Charge pumps of the Schenkel-type
  • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
  • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
  • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
  • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
  • H02M3/073—Charge pumps of the Schenkel-type
  • H02M3/078—Charge pumps of the Schenkel-type with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters

Definitions

• the present invention relates to charge pump circuits. More particularly, the present invention relates to a negative charge pump that switches the bulk of each transistor stage to the lowest potential node to minimize body effect.
• FIG. 1 a schematic diagram depicts a commonly employed prior-art implementation of a negative charge pump formed from n-channel MOS transistors.
• Charge pump 10 includes three stages, 12, 14, and 16, driven by a four-phase clock. Each stage includes two n-channel MOS transistors and two capacitors.
• Stage 12 includes n-channel MOS transistors 18 and 20.
• N-channel MOS transistor 18 has its drain coupled to ground, its source coupled to the source of n-channel MOS transistor 20 and its gate coupled to the drain of n-channel MOS transistor 20 and to the phase-D signal of the clock through capacitor 22.
• the gate of n-channel transistor 20 is coupled to the drain of n-channel MOS transistor 18 and to the phase- A signal of the clock through capacitor 24.
• Stage 14 includes n-channel MOS transistors 26 and 28. N-channel MOS transistor
• n-channel MOS transistor 26 has its drain coupled to the sources of n-channel MOS transistors 18 and 20 from stage 12, its source coupled to the source of n-channel MOS transistor 28 and its gate coupled to the drain of n-channel MOS transistor 28 and to the phase-B signal of the clock through capacitor 30.
• the gate of n-channel transistor 28 is coupled to the drain of n-channel MOS transistor 26 and to the phase-C signal of the clock through capacitor 32.
• Stage 16 includes n-channel MOS transistors 34 and 36.
• N-channel MOS transistor 34 has its drain coupled to the sources of n-channel MOS transistors 26 and 28 from stage 14, its source coupled to the source of n-channel MOS transistor 36 and its gate coupled to the drain of n-channel MOS transistor 36 and to the phase-D signal of the clock through capacitor 38.
• the gate of n-channel transistor 36 is coupled to the drain of n-channel MOS transistor 34 and to the phase-A signal of the clock through capacitor 40.
• each of the n-channel MOS transistors 18, 20, 26, 28, 34, and 36 has its bulk connected to the most negative node (VNEG at reference numeral 42) that serves as the output of the charge pump.
• VNEG most negative node
• FIG. 16 can be turned on during the transition toward the steady state (from 0 to VNEG) when the phase-A signal of the clock goes low to sink current from the load. If the bipolar transistor turns on, the efficiency of the charge pump is compromised because the current is no longer sunk by the load but from the grounded buried-n-well collector of the bipolar transistor. Moreover another drawback of the implementation of FIG. 1 is that body effect of the n-channel MOS transistors of the charge pump increases moving from right to left of the pump. This can severely limit the performance of the charge pump in terms of maximum negative voltage in those applications where very low power supply voltages are employed.
• FIG. 2 a schematic diagram shows a prior-art solution that can be adopted to reduce but does not eliminate the body effect inside each stage of the charge pump.
• the circuit of FIG. 2 is substantially similar to the circuit of FIG. 1, except that the bulks of the two n-channel MOS transistors in each stage are coupled to the output node of the stage.
• the bulks of n-channel MOS transistors 18 and 20 are coupled to their common sources; the bulks of n-channel MOS transistors 26 and 28 are coupled to their common sources; and the bulks of n-channel MOS transistors 34 and 36 are coupled to their common sources.
• This configuration does not solve the parasitic bipolar turn-on problem in the last stage 16.
• Another technique to reduce the body effect is disclosed in United States Patent No.
• the present invention provides a n-channel MOS transistor charge pump in which the bulks of the n-channel MOS transistors are biased in such a manner as to prevent turning on the parasitic bipolar transistor inherent in the CMOS environment of the charge pump structure.
• a negative- voltage charge pump has a plurality of operating phases and comprises a plurality of stages, each stage comprising at least two n-channel MOS transistors each including bulk regions. Each of said stages also includes a parasitic bipolar transistor. The bulk regions are switchably coupled during each of the operating phases to a circuit node having a potential such that the parasitic bipolar transistor will not turn on.
• FIG. 1 is a schematic diagram depicting a common implementation of a negative charge pump employing n-channel MOS transistors.
• FIG. 2 is a schematic diagram depicting another prior-art implementation of a negative charge pump employing n-channel MOS transistors.
• FIG. 3 is a schematic diagram depicting a single stage of a negative charge pump employing n-channel MOS transistors according to the present invention.
• FIG. 4 is a schematic diagram depicting multiple stages of a negative charge pump employing n-channel MOS transistors according to the present invention. DETAILED DESCRIPTION OF THE INVENTION
• FIG. 3 a schematic diagram shows an illustrative embodiment of a single stage 50 of an illustrative charge pump that operates in accordance with the principles of the present invention.
• FIG. 3 illustrates a stage corresponding to the second stage of the charge pumps of FIGS. 1 and 2 and the same reference numerals as used in those figures will be used in FIG. 3 to identify corresponding circuit elements.
• Stage 50 includes n-channel MOS transistors 26 and 28.
• n-channel MOS transistor 26 has its drain coupled to the common sources of the two n-channel MOS transistors from the preceding stage (which in this case would be the sources of n-channel MOS transistors corresponding to reference numerals 18 and 20 of FIGS. 1 and 2) (or to ground if stage 50 is the first stage), its source coupled to the source of n-channel MOS transistor 28 and its gate coupled to the drain of n ⁇ channel MOS transistor 28 and to the phase-B signal of the clock through capacitor 30.
• n-channel transistor 28 is coupled to the drain of n-channel MOS transistor 26 and to the phase-C signal of the clock through capacitor 32.
• the phase-A signal of the clock is shown coupled to the common sources of n-channel MOS transistors 26 and 28 through capacitor 40 as it is in the charge pumps depicted in FIGS. 1 and 2.
• the bulks of n-channel MOS transistors 26 and 28 are connected together to a node
• Node 50 is coupled to the drains of both n-channel MOS transistors 52 and 54 as well as to their bulk regions.
• the source of n-channel MOS transistor 52 is coupled to the common sources of the two n-channel MOS transistors of the previous stage, and the source of n- channel MOS transistor 54 is coupled to the common sources of the two n-channel MOS transistors 26 and 28.
• the gate of n-channel MOS transistor 52 is coupled to the drain and gate of n-channel MOS transistor 28 and the gate of n-channel MOS transistor 54 is coupled to the common sources of n-channel MOS transistors 26 and 28.
• phase-A signal of the clock when the phase-A signal of the clock is high and the phase-C signal of the clock is low, the phase-B signal of the clock also goes high and turns on n-channel MOS transistor 26, allowing current to flow from capacitor 40 to capacitor 30 thus discharging capacitor 40 and charging up capacitor 30. Then the phase-A signal of the clock goes low and receives charge from the following stage while the phase-C signal of the clock goes high, transferring charge to the previous stage.
• Adding the two transistors 52 and 54 to each stage prevents the parasitic bipolar transistor from being turned on.
• the phase-C signal of the clock is high and the phase- A signal of the clock is low, the phase-B signal of the clock is also low, n-channel MOS transistor 52 is turned off and n-channel MOS transistor 54 is turned on, thus biasing node 50 to the same potential of as the common sources of n-channel MOS transistors 26 and 28, which is the lowest voltage seen by the transistors of this stage.
• phase-B signal of the clock is also high and n-channel MOS transistor 54 is turned off but n- channel MOS transistor 52 is turned on, thus assuring that the bulk regions of n-channel MOS transistors 26 and 28 are at a potential that is more negative or the same as any n+ region of the stage.
• FIG. 4 a schematic diagram shows an illustrative charge-pump circuit 60 in accordance with the present invention including multiple charge-pump stages.
• the same reference numerals as used in figures 1 and 2 will be used in FIG. 4 to identify corresponding circuit elements.
• charge-pump circuit 60 of FIG. 4 includes three stages, 62, 64, and 66, driven by a four-phase clock. Each stage includes the same two n-channel MOS transistors and two capacitors.
• Stage 62 includes n-channel MOS transistors 18 and 20.
• N-channel MOS transistor 18 has its drain coupled to ground, its source coupled to the source of n-channel MOS transistor 20 and its gate coupled to the drain of n-channel MOS transistor 20 and to the phase-D signal of the clock through capacitor 22.
• the gate of n-channel transistor 20 is coupled to the drain of n-channel MOS transistor 18 and to the phase-A signal of the clock through capacitor 24.
• stage 62 includes n-channel MOS transistors 68 and 70 having their drains coupled together to node 72 comprising the bulk regions of n-channel MOS transistors 18 and 20 as well as the bulk regions of n-channel MOS transistors 68 and 70.
• n-channel MOS transistor 68 is coupled to the drain of n-channel MOS transistor 18 and its gate is coupled to the drain of n-channel MOS transistor 20.
• the source of n-channel MOS transistor 70 is coupled to the common sources of n-channel MOS transistors 18 and 20 and its gate is coupled to the drain of n-channel MOS transistor 18.
• Stage 64 includes n-channel MOS transistors 26 and 28.
• N-channel MOS transistor 18 has its drain coupled to the sources, of n-channel MOS transistors 18 and 20 from stage 62, its source coupled to the source of n-channel MOS transistor 28 and its gate coupled to the drain of n-channel MOS transistor 28 and to the phase-B signal of the clock through capacitor 30.
• the gate of n-channel transistor 28 is coupled to the drain of n-channel MOS transistor 26 and to the phase-C signal of the clock through capacitor 32.
• stage 64 includes n-channel MOS transistors 74 and 76 having their drains coupled together to node 78 comprising the bulk regions of n-channel MOS transistors 26 and 28 as well as the bulk regions of n-channel MOS transistors 74 and 76.
• the source of n-channel MOS transistor 74 is coupled to the drain of n-channel MOS transistor 26 and its gate is coupled to the drain of n-channel MOS transistor 28.
• the source of n-channel MOS transistor 76 is coupled to the common sources of n-channel MOS transistors 26 and 28 and its gate is coupled to the drain of n-channel MOS transistor 26.
• Stage 66 includes n-channel MOS transistors 34 and 36.
• N-channel MOS transistor 34 has its drain coupled to the sources of n-channel MOS transistors 26 and 28 from stage 64, its source coupled to the source of n-channel MOS transistor 36 and its gate coupled to the drain of n-channel MOS transistor 36 and to the phase-D signal of the clock through capacitor 38.
• the gate of n-channel transistor 36 is coupled to the drain of n-channel MOS transistor 34 and to the phase-A signal of the clock through capacitor 40.
• stage 66 includes n-channel MOS transistors 80 and 82 having their drains coupled together to node 84 comprising the bulk regions of n-channel MOS transistors 34 and 36 as well as the bulk regions of n-channel MOS transistors 80 and 82.
• the source of n-channel MOS transistor 80 is coupled to the drain of n-channel MOS transistor 34 and its gate is coupled to the drain of n-channel MOS transistor 36.
• the source of n-channel MOS transistor 82 is coupled to the common sources of n-channel MOS transistors 34 and 36 and its gate is coupled to the drain of n-channel MOS transistor 34.
• Stage 66 also includes capacitor 86 coupling the phase-C signal of the clock to the sources of n-channel MOS transistors 34 and 36.
• the output of the charge pump of FIG. 4 is the VNEG node 88 at the source of n- channel MOS transistor 90.
• the drain of n-channel MOS transistor 90 is coupled to the sources of n-channel MOS transistors 26 and 28.
• the gate of n-channel MOS transistor is coupled to the drain of n-channel MOS transistor 36.
• the bulk of n-channel MOS transistor 90 is coupled to node 78.
• the last stage 66 is not used to transfer charge, but is present for the purpose of properly biasing the gate of n-channel MOS transistor 90.
• the capacitors 22, 24, 30, 32,38, 40, and 86 used in the circuits of FIGS. 3 and 4 may be formed as either poly-1 to poly-2 capacitors or as MOS capacitors. Typical values for these capacitors may be from about 500fF to about 7pF, although capacitors 38 and 86 in the last stage may have low values since they are not used to transfer charge to the load.
• charge-pump circuits according to the principles of the present invention may be realized using any number of stages.
• All transistors 34, 36, 80, and 82 have their bulk regions biased more negatively or at the same potential of any n+ junction of the stage.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Dc-Dc Converters (AREA)
• Semiconductor Integrated Circuits (AREA)
• Logic Circuits (AREA)

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• 2003
  • 2003-09-18 EP EP03759460A patent/EP1550017A4/de not_active Withdrawn
  • 2003-09-18 AU AU2003275191A patent/AU2003275191A1/en not_active Abandoned
  • 2003-09-18 CA CA002499086A patent/CA2499086A1/en not_active Abandoned
  • 2003-09-18 WO PCT/US2003/030011 patent/WO2004027996A2/en active Application Filing
  • 2003-09-18 JP JP2004568961A patent/JP2006500900A/ja active Pending
• 2005
  • 2005-04-05 NO NO20051678A patent/NO20051678L/no not_active Application Discontinuation

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