EP1540822A2 - Convertisseur analogique-numerique, echelle de comptage de courant et procede de commande d'une fonction de l'echelle de comptage de courant - Google Patents

Convertisseur analogique-numerique, echelle de comptage de courant et procede de commande d'une fonction de l'echelle de comptage de courant

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Publication number
EP1540822A2
EP1540822A2 EP03702679A EP03702679A EP1540822A2 EP 1540822 A2 EP1540822 A2 EP 1540822A2 EP 03702679 A EP03702679 A EP 03702679A EP 03702679 A EP03702679 A EP 03702679A EP 1540822 A2 EP1540822 A2 EP 1540822A2
Authority
EP
European Patent Office
Prior art keywords
transistor
output
receiving
bit
inlet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03702679A
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German (de)
English (en)
Inventor
Ari Paasio
Mika Laiho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
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Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of EP1540822A2 publication Critical patent/EP1540822A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register

Definitions

  • the present invention relates to A/D (analog-to-digital) converters, and more closely to an asynchronous shift register structure, a control logic circuit and their functioning in A/D converters .
  • the present invention further provides a current sealer and a method for controlling a function of a current sealer.
  • an input current (or an input voltage, or such) that is converted is first compared to a current of a most significant bit (MSB) .
  • MSB most significant bit
  • the current of the most significant bit is left off if the current of the most s ' ig- nificant bit is bigger than the input current that is converted. If the current of the most significant bit is smaller than the input current that is converted, the current of the most significant bit is added to the current of the second most significant bit.
  • the process is re- peated with a bit-by-bit and a current source by current source until the current source of the least significant bit (LSB) is processed.
  • the result of the conversion can be read directly from the control bits of a current source matrix.
  • a control logic of the A/D converter controls setting of the bits.
  • the control logic used in the above conversion is a successive approximation register (SAR) , which usually has two input signals, a clock and a reset, and N outputs, wherein N indicates the amount of the bits used.
  • SAR successive approximation register
  • One principle of functioning of the successive approxima- tion register is disclosed in US 4,688,018.
  • the successive approximation register comprises a shift register and a control logic.
  • the shift register is usually a synchronous shift regis- ter, which is formatted in a certain state (i.e., the control signals set the registers into a HIGH state or into a LOW state) before the conversion ' is started.
  • This formatting operation set the pointer (s) (or alike) to the most significant bit (MSB) . Thereafter when the process contin- ues, the pointer is moved towards less significant bits with a clock signal.
  • the present invention provides a simple structure and methods for A/D conversions based on a shift register implemented as a successive approximation register.
  • An A/D (analog-to-digital) converter according to the present invention further achieves lower power consumption, smaller size when integrated into a chip and less complex struc- ture than the prior art implementations.
  • the solution as disclosed in the appended claims enables the use of a D/A converter as one part of the A/D conversion or as a mere D/A converter. This provides more applications in which the D/A converter of the present invention may be implemented than in the prior art solutions.
  • the present invention also enables the use of the D/A converter alternatively for controlling a scaling factor of a current mirror.
  • an analog-to-digital converter comprising: a digital-to-analog converter part for providing an output measure of the digital-to-analog converter part; means for providing a measure that is compared with the output measure of the digital-to-analog converter part ; means for conducting a comparison result to control logic means ; and control logic means for providing control signals to the digital-to-analog converter part, wherein the control logic means comprise at least one asynchronous shift register and at least one control logic circuit.
  • the digital-to-analog ' converter part comprises: a plurality of current mirrors for providing scaled currents to corresponding switches, a plurality of switches that are controlled by the control logic circuit of a corresponding bit , means for summing up output currents of the 'switches and means for providing control voltages to the current mirrors .
  • means for providing a current that is compared with the output current of the digital-to-analog converter part comprises a NMOS transistor having an inlet for receiving a source voltage, an inlet for receiving a control voltage and an outlet for providing an output current of the transistor that is compared with the output current of the digital-to-analog converter part.
  • each control logic circuit provides the con- trol signal to the respective switch.
  • a current sealer comprising: switching means for choosing a function of the cur- rent sealer; means for scaling an input measure; means for conducting or restricting the conduction of the scaled input measure for following processes .
  • the function of the current sealer is to use the current sealer for a conversion as a part of an A/D converter or as a D/A converter or to use the current sca- ler for defining a programmable scaling factor of a current mirror.
  • the means for scaling an input measure comprises at least one scaling mirror for scaling an input current and the means for conducting or restricting the conduction of the scaled input measure for following procedures 'comprises at least one switching transistor for switching from a conductive state to a non-conductive state, or vice versa, and control logic means for provid- ing a control signal to respective switching transistor.
  • an ' asynchronous shift register for providing control signals to a control logic circuit
  • the shift reg- ister comprising: means for receiving in the asynchronous shift register of a bit a start signal or an output signal from an asynchronous shift register of a previous bit; processing means for processing the received signal in the asynchronous shift register of the bit to result an output signal; and output means for providing an output signal of the asynchronous shift register to the control logic circuit of the bit and to an asynchronous shift register of a fol- lowing bit.
  • the asynchronous shift register of the bit has a first and a second bit blocks in which: the first bit block comprises receiving means for re- ceiving a start signal or an output signal from a previous bit, processing means for processing the received signal to result an output signal of the first block of the bit and output means for providing an output signal of the first block to a second block of the bit and to a first block of a following bit; and the second bit block comprises receiving means for receiving the output signal of the first block of the bit, processing means for processing the received signal to result an output signal of the second block of the bit and output means for providing the output signal of the second block of the bit to a control logic circuit of the bit.
  • the first block of the bit comprises: a first transistor having an inlet for receiving a source voltage, an inlet for receiving a control voltage and an outlet for providing an output current of the first transistor to a second transistor; the second transistor hav- ing an inlet for receiving the output current of the first transistor, an inlet for receiving the start signal or the output ' signal from the previous bit, which is a control signal of the transistor, and an outlet for providing an output current of the transistor to form a control voltage of a fourth and a fifth transistor; a third transistor having an inlet for receiving a source voltage, an inlet for receiving a control voltage and an outlet for providing an output current of the third transistor to form the control voltage of the fourth and the fifth transistors; a current starved transistor having an inlet for receiving a source voltage, an inlet for receiving a control voltage and an outlet for providing an output current of the current starved transistor to the fourth transistor; the fourth transistor having an inlet for receiving an output current of the current starved transistor, an inlet for receiving the control the control
  • the first block of the bit comprises: a first transistor having an inlet for a source voltage, an inlet for receiving a control voltage and an outlet for providing an output current of the first transistor to a second transistor; the second transistor having an inlet for receiving the output current of the first transistor, an inlet for receiving the start signal or the output signal from the previous bit, which is a control signal of the transistor, and an outlet for providing the output current of the transistor to form a control voltage of a fourth and a fifth transistor; a third transistor having an inlet for receiving a source voltage, an inlet for receiving a control voltage and an outlet for providing an output ' current of the third transistor to form a control voltage of the fourth and the fifth transistors; the fourth transistor having an inlet for receiving a source voltage, an inlet for receiving the control voltage and an outlet for providing an output voltage to an output point of the first block; the fifth transistor having an inlet for receiving a source voltage, an inlet for receiving the control voltage and an outlet for providing an output voltage of the fifth transistor to the output point of the first block
  • the first, the second, the fourth and the current starved transistors are PMOS transistors, and the third and the fifth transistors are NMOS transistors.
  • the output signal of the first block of the bit is provided to the second block of the bit or to the first block of the following bit when the start signal or the output signal from the previous bit is received in the inlet for receiving a control voltage of the second transistor.
  • the output signal of the first block of the shift register changes from an inactive state to an active state when the start signal or the output signal from the previous bit is received in the receiving means in the first block of the bit.
  • the .second block of the bit comprises: a first transistor having an inlet for ⁇ receiving a source voltage, an inlet for receiving a control voltage, which is the output signal of the first block of the bit, and an outlet for providing an output voltage of the first transistor to an output point of the second block; a second transistor having an inlet for receiving a source voltage, an inlet for receiving a control voltage and an outlet for providing an output current and voltage of the second transistor to a third transistor; the third transistor having an inlet for receiving the output voltage of the second transistor, an inlet for receiving a control voltage, which is the output signal of the first block of the bit, and an outlet for providing an output voltage of the third transistor to an output point of the second block; and the output point of the second block of the bit for . receiving the output voltages of the first and the third transistors and providing the output signal of the second block of the bit to the control logic circuit of the bit. More preferably, the first transistor is a PMOS transistor and the second and the third transistors are NMOS transistors
  • the output signal of the second block of the bit changes from an inactive state to an active state when the output signal from the first block of the bit is re- ceived in the receiving means in the second block of the bit.
  • a control logic circuit for providing control signals to a bit of a digital-to-analog converter or to a bit of an analog-to-digital or to a current mir- ror, the control logic circuit comprising: means for providing a first control signal to an inverter or to a NOR circuit; means for providing a second control signal to the inverter or to the NOR circuit; . comparator means for providing an output voltage to the means for providing the second control signal; .
  • the ' inverter or the NOR circuit for processing the received control signal and for providing an output signal to an output point of the control logic circuit; and the output point of the control logic circuit for providing the output signal of the control logic circuit to a corresponding bit of the digital-to-analog converter or the analog-to-digital converter or the current mirror.
  • the means for providing the first control signal to the inverter or to the NOR circuit comprises : a first transistor having an inlet for receiving a source voltage, an inlet for receiving a control signal of the first transistor, which is a start signal in a first bit or an output signal of a previous bit, and an outlet for providing an output voltage to a second transistor; and the second transistor having an inlet for receiving the output voltage of the first transistor, an inlet for receiving a first control voltage and an outlet for provid- ing the first control signal to the inverter or to the NOR circuit.
  • the means for providing the second control signal to the inverter or to the NOR circuit comprises a third and a fourth transistor of the control logic circuit, wherein the third transistor has an inlet for receiving a source voltage, an inlet for receiving a control signal of the third transistor, which is a start signal in a first bit or an output signal of a previous bit, and an outlet for providing an output voltage to the fourth transistor and the fourth transistor has an inlet for receiving an output voltage of the third transistor and the out- ' put voltage from the comparator means, an inlet for receiving a second control voltage and ' an outlet for providing a second control signal to the inverter or to the NOR circuit .
  • the provision of the output voltage to the means for providing the second control signal is dependent on a comparison result of an analog-to-digital converter and the ' comparator means comprises a comparator transistor and a fifth transistor of the control logic circuit, wherein the comparator transistor has an inlet for receiving a source voltage, an inlet for receiving a control voltage, which is a comparison result of the analog-to-digital converter, and an outlet for providing an output voltage to the fifth transistor and the fifth transistor has an inlet for receiving the output voltage of the comparator transistor, an inlet for receiving a first control voltage and an outlet for providing an output voltage to the means for providing the second control signal.
  • the inverter has three transistors, and wherein a first ' transistor of the inverter has an inlet for receiving a source voltage, an inlet for receiving a control signal, which is whether the first control signal or the second control signal of the control logic circuit, and an outlet for providing an output signal of the inverter to the output point of the control logic circuit a second transistor of the inverter has an inlet for receiving an output voltage of a third transistor of the inverter, an inlet for receiving a control signal, which is whether the first control signal or the second control signal of the control logic circuit, and an outlet for providing an output signal of the inverter to the output point of the point of the control logic circuit and the third transistor of the inverter has an inlet for receiving a source voltage, an inlet for receiving a control voltage and an outlet for providing the output voltage to the second transistor of the inverter.
  • the first and the second transistors of the control logic circuit and the first transistor of the inverter are PMOS transistors
  • the third, the fourth and the fifth transistors of the control logic circuit and the comparator transistor and the' second and the third transistors of the inverter are NMOS transistors.
  • a method for providing control signals from an asynchronous shift register to a control logic circuit comprising: receiving ' a START signal or a control signal from a previous bit in an asynchronous shift register of ⁇ a bit; processing the received signal in the asynchronous shift register of the bit to result an output signal of the asynchronous shift register of the bit; and providing the processed signal from the asynchronous shift register of the bit to the control logic circuit.
  • a method for controlling a function of a current sealer comprising: . determining the function of the current sealer by switches and providing an input current to the current sealer, wherein in case the current sealer is used for conversion as a part of the analog-to-digital converter or as a digital- to-analog converter, conducting an input current through a current generator to the current sealer,- and in case the current sealer is used for defining a scaling factor of a current mirror, conducting the input current through a switch providing a variable current to the current sealer.
  • the A/D con- verter When compared to the prior art solutions, the A/D con- verter according to the present invention does not require a separate clock signal, as is required in the prior art solutions, the power consumption is reduced and the wiring in the shift register is reduced. Therefore, also the physical size of the shift register is also reduced, which enables that increased number of the A/D converters may be integrated into one chip.
  • the 'reduce of the power consumption is 'also achieved by defining the inventive concept such that during the conversion the ' states of the control signals only changes in one direction, i.e., the state changes from a HIGH state into a LOW state, or vice versa.
  • Figure 1 shows an A/D (analog-to-digital) converter according to the preferred embodiment of the present in- vention.
  • Figure 2 shows a circuit for output signals of an asynchronous shift register according to the present invention.
  • Figure 3 shows a signalling diagram for output sig- nals of an asynchronous shift register for three first bits .
  • Figure 4 shows a current starved inverter, which is applied to the circuit of Figure 2 in the present invention.
  • Figure 5 shows a block diagram of one possibility for implementing a shift register according to the present invention.
  • Figure 6 shows a shift register block LI according to one embodiment of the present invention.
  • Figure 7 shows a block LI with a current starved transistor according to the preferred embodiment of the present invention
  • Figure 8 shows a shift register block L2 with a current starved transistor according to the preferred embodiment of the present invention.
  • Figure 1 shows an A/D (analog-to-digital) converter according to the preferred embodiment of the present inven- tion. Even though, there is shown a converter with five bits, a man skilled in the art realizes that the same principles are easily implemented to the converters with more (or less) than five bits.
  • a D/A (digital-to-analog) part of the converter in a tran- sistor level while a control logic circuit of the converter is shown as a box 115.
  • Figure 1 also illustrates the possibility for choosing (with switching means) the function of the D/A converter (which is a current sealer of this embodiment of the present invention) .
  • the D/A converter is used for a conversion as a part of the A/D converter or as the D/A converter
  • an input current is conducted through a switch providing the input current from a current generator 102 to the D/A converter.
  • the D/A converter is used for defining a scaling factor of a current mirror, the input current is conducted through a switch 100 providing a variable current to the D/A con- verter .
  • Transistors 101, 103, 104, 105, 106 and 107 have inlets for a source voltage (VDD) , and outlets for conducting the output (measure) of the transistor to the following transistor.
  • the control voltage of the transistors 101 and 103 to 107 is formed from the output of the transistor 101 defined by a reference current (Iref) of a current generator 102 (or a current mirror switch 100) provided e.g., from a memory.
  • the control voltage of the transistors 101 and 103 to 107 is indicated as Vref -in the Figure 1.
  • a current mirror formed with the transistors 101 and 103 has a scaling factor (Width 103 / Length 103) ' / (Width 101 / Length 101) S. .
  • the corresponding scaling factor for a current mirror (i.e., means for scaling an input measure) formed ' by the transistors 101 and 104 (105, 106 and 107 respectively) is 2*S (4*S, 8*S and
  • the outlets of the transistors 103 to 107 conduct the out- put currents to the transistors 108 to 112, in which the transistors 108 to 112 act as switches (i.e., means for conducting or restricting the conduction of the scaled input measure for following processes) .
  • switches i.e., means for conducting or restricting the conduction of the scaled input measure for following processes.
  • the control signals of the transistors 108 and 109 are LOW and the transistors 110 to 112 are HIGH
  • the transistors 108 and 109 conduct their output currents to further .processing.
  • their output currents are summed up in a node 113, which forms an output current (I_DA) of the D/A converter.
  • the control voltages of the transistors 108 to 112 are provided as control signals B4 to B0, respectively, from the control logic circuit 115.
  • the transistors 101 and 103 to 112 are PMOS transistors in the preferred embodiment of the present invention.
  • the transis- tors 101 and 103 to 112 can also be NMOS transistors in an alternative embodiment of the present invention if the control logic of the system is applied according to the change of the transistor type from the PMOS transistors to the NMOS transistors. Also the polarity of a START signal must be changed in this alternative embodiment of the present invention according to the change of the transistor types .
  • a transistor 114 has an inlet for a source voltage (VSS) , a control voltage (VIN) and an outlet for providing a measure, e.g., a current, (I_IN) that- is converted.
  • the current (I_IN) is compared to the current (I_DA) provided by . the transistors 108 to 112, and the outcome of the comparison is indicated as C_OUT> which is further conducted to the logic circuit 115.
  • the control signal B0 changes to a LOW state, while the other control signals remains in the HIGH state, and the output current (I_DA) is 16*Iref .
  • the next step in the conversion process is that the control logic of the control logic circuit 115 waits when the comparison (i.e., C_OUT) of the quantities I_IN and I_DA is finished. Thereafter, in case C_0UT is in close approximate to VSS, i.e., the negative supply voltage, B0 is kept in the LOW state and the control signal Bl is changed to a LOW sate . In case C_OUT is in close approximate to VDD, the control signal B0 is changed to a HIGH state, in the mean time when the control signal Bl is changed to the LOW state.
  • the next step in the conversion process is to wait until the comparison result C_OUT is received in the control logic circuit. Thereafter, Bl whether remains in its LOW state or is changed to the HIGH state, when B2 is changed to a LOW state, based on the comparison result C_OUT.
  • the corresponding functions are applied with the control signals B2 to B4 , as were applied to the control signals BO and Bl . After the comparison result of a polarity of the control signal B4 is achieved, the conversion is fin- ished.
  • Figure 2 shows a circuit for output signals of an asynchronous shift register according to the present inven ⁇ tion.
  • Figure 3 shows a signalling diagram for output sig- nal . s of an asynchronous shift register for three first bits, in which a START-signal -is also the first input signal of the most significant bit (MSB) block.
  • MSB most significant bit
  • FIG. 2 there is shown six transistors, i.e., transistors 201 to 206, an inverter 207 and a node VJMID in the circuit. There are also shown three control signals BX_0 , BX_1 and BX_2 , and a comparator income C_OUT .
  • the transistor 201 has an inlet for a source voltage VDD, an inlet for receiving a control signal BX__0 and an outlet for conducting an output voltage of the transistor 201 to an inlet of the transistor 202.
  • the transistor 202 has the inlet for receiving the output voltage of the transistor 201, an inlet for receiving a control signal BX_1 and an outlet for providing an output voltage of the transistor 202 to the node V_MID .
  • the transistors 201 and 202 are PMOS transistors.
  • the transistor 203 has an inlet for receiving an output voltage from an outlet of the transistor 204 and/or of the transistor 205, an inlet for receiving a control signal BX_2 and an outlet for conducting an output voltage of the transistor 203 to the node V_MID .
  • the transistor 204 has an inlet for receiving a source voltage VSS, an inlet for receiving a control signal BX_0 • and the outlet for con ⁇ ducting the output voltage of the transistor 204 to the inlet of the transistor 203.
  • the transistor 205 has an inlet for receiving an output voltage from the transistor 206, an inlet for receiving a control signal BX_1 and the outlet for conducting the out- put voltage to the transistor 203.
  • the transistor (a comparator transistor) 206 has an inlet for receiving a source voltage VSS, an inlet for receiving a control signal C_OUT and the outlet for conducting the output voltage to the transistor 205.
  • the transistors 203 to 206 are NMOS transistors.
  • the inverter 207 has an inlet for receiving a voltage from the node V_MID and an outlet for providing an output signal OUT of the control logic circuit to the analog-to- digital converter.
  • the ' control signals BX_0 and BX_2 (e.g., START and Bl_2 in Figure 3) are in a HIGH state and the control signal BX_1 (e.g., Bl_l in Figure 3) is in a LOW state.
  • the transistors 203 and 204 switch the node V_MID into a LOW state, i.e., the output of the circuit is in a HIGH state.
  • the transistors 201 and 205 are in non-conducting state, and therefore, the path through the transistors 204 and 203 is the only path affecting to potential of the node V_MID .
  • the circuit is in this state, until the control signal BX_0 changes to a LOW state (indicated as first level of START in Figure 3) , which affects that the transistor 204 changes into a non-conducting state and the transistor 201 changes into a conducting state. Since the transistor 202 also conducts, the state of the node V_MID changes to a HIGH state and the output of the circuit changes to a LOW state. Thereafter, the comparison voltage is let to form into C OUT.
  • the directions and the amounts of the output currents of the current that is converted and the D/A converter are such that if the set bit stays in use, the potential of the C_OUT is LOW, i.e., the transistor 206 is non- ' conductive. In case the output current .of the D/A con-
  • the potential of the C_OUT sets into a HIGH state.
  • the next control signal of the shift register changes its polarity, i.e., the control signal BX_1 (e.g., Bl_l in Figure 3) changes into a HIGH state.
  • the upper' path ' of the circuit i.e., the path through the transistors 201 and 202, changes into a non-conductive state, since the transistor 202 changes into the non-conductive state.
  • the transistor 205 changes into a conductive state (since the transistor 205 has been changed into a conductive state).
  • the node V_MID whether stays in the HIGH state or is changed into a LOW state through the transistors 206, 205 and 203, depending on the comparison result C__OUT.
  • the third control signal from the shift register is to separate the transistor 206 from the node V_MID, by changing the control signal BX_2 (e.g., Bl_2 in Figure 3) into a LOW state.
  • BX_2 e.g., Bl_2 in Figure 3
  • the state of the node V_MID is not dependent on the signal C_OUT, since the transistor 203 changes into a no -conductive state.
  • Figure 4 shows a current starved inverter, which is applied to the circuit of Figure 2 in the present invention.
  • the inverter 207 may be used in the present invention to achieve a result, in which the bit is set slowly, but the set of the bit may be removed quickly.
  • the inverter 207 comprises a bias transistor 401, a PMOS transistor 402 and a NMOS transistor 403.
  • the bias transistor 401 which in this case is a NMOS transistor, has an inlet for receiving a source voltage VSS, an inlet for receiving a control voltage NBIAS and an outlet for providing an output voltage of the transistor 401 into an inlet of the transistor 403.
  • the transistor 402 has an inlet for receiving a source voltage VDD, an inlet for receiving a control voltage IN (which is the output of the node V_MID) and an outlet for providing an output voltage of the transistor 402.
  • the transistor 403 has the inlet for receiving the output voltage of the bias transistor ' 401, an inlet for receiving a control voltage IN and an outlet for providing an output voltage of the transistor 403.
  • the output voltages of the transistors 402 and 403 form an output (OUT) of the inverter 207 shown in Figure 2.
  • one structure can be a D/A converter.
  • the D/A converter may be used whether in an A/D conversion or merely in a D/A conversion.
  • the inverter (as shown with reference to Figures 2 to 4) is replaced with a two input NOR (i.e., NOT-OR) circuit to provide a possibility to choose an application in which the D/A converter is used.
  • the inverter instead of the position shown with respect to Figure 2, the inverter (in this embodiment the NOR) can be positioned to the current starved cross, which is controlled by V-MID, if required by production design or some other function alike .
  • one of the input signals of the circuit is a V_MID signal, which is shown with reference to Figure 2, and the other input signal is a normal control bit of the D/A converter.
  • the normal control signals of the D/A converter is set into a ' LOW state. Therefore, the effect of the node V_MID potential to the input of the NOR circuit is identical to the implementation with the inverter.
  • the SAR of the D/A converter must be in an initialization state. In this case, the normal control signals of the D/A converter affect the switches of the D/A converter.
  • One control logic circuit (shown in Figure 2 ) is needed for one bit, i.e., in case there are five bits in an A/D converter, there is also needed five control logic cir ⁇ cuits.
  • the number of the transistors in the A/D converter may also be reduced by using a common comparator transis- tor 206 for all control logic circuits. In case of five bits in the A/D converter (and therefore also five control logic . circuits) , the number of the comparator transistors can be reduced from five comparator transistors into one comparator transistor.
  • the shift register of the control logic is asynchronous, which means that the output signal of the previous bit block is used for acti ⁇ vating the next bit block of the shift register.
  • the asyn- chronous shift register has several advantages over syn ⁇ chronous shift registers. For example, since only one con ⁇ trol signal is needed to be conducted to the bit block, and therefore, the need for wiring in the A/D converter is reduced.
  • the control signal conducted to the bit block formats the shift register into a state in which none of the bit blocks is active, in case the shift register is in another state. When the polarity of the control signal is changed, the shift register of the most significant bit (MSB) is activated.
  • the required output signals of the shift register are con- nected to the control logic that is implemented in the preferred embodiment of the present invention.
  • a shift register corresponding to one bit produces two output signals, from which one of the output signals is used to activate the following shift register.
  • the control logic disclosed with reference to Figures 2 to 4 requires three control signals, and therefore, third control signal, in addition to two control signals of each bit, is received from a START signal in the most significant bit block. In the other bit blocks the third control signal is received from the previous bit block from such signal that activates the bit block, in case the polarity of the signal changes.
  • the same signal is used as a third control signal (e.g., BX_2 in Figure 2 or Bl_2 in Figure 3) in one control logic block and as a first signal (e.g., BX_0 in Figure 2 or START in Figure 3) of the control logic block of the following bit. Therefore in practice, the previous control logic block is switched into its final state at the same time when the following bit is already started to be set active. Due to the relatively slow response of C_OUT to the change of the control of the D/A converter, the previous bit block has enough time to switch to the last operating mode before C_OUT possibly changes due to setting the next bit block active.
  • a third control signal e.g., BX_2 in Figure 2 or Bl_2 in Figure 3
  • a first signal e.g., BX_0 in Figure 2 or START in Figure 3
  • the signals shown in Figure 3 can be implemented e.g., with a block structure shown in Figure 5.
  • Figure 5 shows a block diagram of one possibility for implementing a shift register according to the present invention.
  • the first block i.e., block LI
  • the second block i.e., block L2
  • the second block generates the signals BX_1 (i.e., Bl_l, B2_l, etc.).
  • the output signal of the first block LI is used as an input signal of a next LI block.
  • the output signal generated in the last LI block can be used to indicate when the conversion is ready. Since the blocks generate only such sig- nals that changes into one direction, it helps to design the shift register to be lower power consumption than the shift registers of the prior art solutions.
  • FIG. 6 shows a shift register block LI according to one embodiment of the present invention.
  • the transistor 601 has an inlet for receiving a control voltage, which is an input voltage received from a previous block, an inlet for receiving a current from a transistor 602 and an outlet for providing an output current of the transistor 601 to form a control voltage of the -transistors 604 and 605.
  • the transistor 602 has an inlet for receiving a source voltage VDD, an inlet for receiving a control voltage PBIAS and an outlet for providing the out- put current from the transistor 602 to the inlet of the transistor 601.
  • the transistor 603 has an inlet for receiving a source voltage VSS, an inlet for receiving a control voltage NBIAS and an outlet for providing an output current to form a control voltage of the transistors 604 and 605.
  • the transistor 604 has an inlet for receiving a source voltage VDD, an inlet for receiving a control voltage, which is formed based on the difference between the output currents of the transistors 601 and 603, and an outlet for providing an output voltage to an output point (OUT) of the block LI.
  • the transistor 605 has an inlet for receiv- ing a source voltage VSS, an inlet for receiving a control voltage, which is formed based on the difference between the output currents of the transistors 601 and 603, and an outlet for providing an output voltage to an output point of the block LI.
  • the output voltage of the block LI is in a HIGH state if the control signal of the transistors 604 and 605 is in a LOW state.
  • the control signal is in a LOW state when the output current of the transistor 603 is greater than the output current of the transistor 601.
  • the transistors 601, 602 and 604 are PMOS transistors in Fig- ure 6, while the transistors 603 and 605 are NMOS transistors .
  • the process in ' block LI, as disclosed in Figure 6, is the following.
  • the input signal (i.e., input voltage) IN of the block LI is in a HIGH state, i.e., the transistor 601 is non-conductive
  • the input point for control voltage of the inverter i.e., the transistors 604 and 605
  • the output voltage of the inverter (and also the block LI) is in a HIGH state.
  • the output current of the transistor 603 affects the control voltage of the inverter so that the control voltage of the inverter is in a LOW state.
  • the amount of the output current of the transistor 603 is controlled with a control voltage NBIAS, which may be relatively small, e.g., lOnA.
  • a limitation to the minimum control voltage is that the output current of the transistor 603 must be significantly- lower than leakage current of the transistor 601, in order to keep the control signal of the inverter in the LOW state . •
  • the block LI remains in this state until the input signal IN changes into a LOW state, where after the switch transistor 601 changes into a conductive state, i.e., the transistor 601 starts to conduct the output current of the transistor 602 into the control voltage inlet of the inverter.
  • the amount of the output current of the transistor 602- which must be bigger than the amount of the output ' current conducted from the transistor 603, is controlled with a control voltage PBIAS.
  • the control signal, of the inverter changes into a HIGH state and the output of the inverter changes into a LOW state.
  • the output of the inverter remains in the LOW state until the control signal of the transistor 601 changes -into a HIGH state, i.e., the transistor 601 changes to a non-conductive state.
  • the control signal of the transistor 601 ' changes into a HIGH state after the conversion is completed, at the same time when the START signal changes into a HIGH state for the MSB block and asynchronously propagating to the other blocks .
  • FIG 7 shows a block LI with a current starved transistor according to the preferred embodiment of the present invention, wherein the transistors 701 to 705 corresponds to the transistors 601 to 605 in Figure 6 with an exception ⁇ that there is a transistor 706 between a source voltage VDD and the transistor 704.
  • the transistor 706, between voltage source VDD and the transistor 704, is a current starving transistor.
  • the current starved transistor 706 is implemented in the preferred embodiment of the present invention to minimize a short- circuit current, which comes into a system in the situa- tion when the inverter changes its state and there is a path conducting current between the operation voltages.
  • the current starved transistor 706 is a PMOS transistor, which has an inlet for receiving a source voltage VDD, an inlet for receiving a control voltage PBIAS and an outlet for providing an output current of the transistor 706 to the inlet of the transistor 704.
  • the transistor 706 lim- ' its the short-circuit current of the inverter.
  • the amount of the short-circuit current can be limited into amount of e.g., 100 nA, instead of an amount about 1 mA of the short-circuit current without the current starved transistor 706.
  • the smaller short-circuit current is chosen, the longer it will take to reset the shift register into its formatting state, and before the shift register is in its formatting state it is not possible to start a new conversion.
  • FIG. 8 shows a shift register block L2 with a current starved transistor according to the preferred embodiment of the ' present invention.
  • the shift register block L2 has three transistors, i.e., transistors 8-01 to 803.
  • the transistors 801 and 802 form an inverter, and the transistor 803 is a current starving transistor in the shift register block L2.
  • the transistor 801 has an inlet for receiving a source voltage VDD, an inlet for receiving a control voltage IN and an outlet for providing an output voltage of the transistor 801 to an output point (OUT) of the shift register block L2.
  • the transistor 801 is a PMOS transistor.
  • the transistor 802 has an inlet for receiving a voltage provided by the current starving transistor 803, an inlet for receiving a control voltage IN and an outlet for providing an output voltage of the transistor 802 to the output point OUT of the shift register block L2.
  • the current starving transistor 803 has an inlet for receiving a source voltage VSS, an inlet for receiving a control voltage NBIAS and an outlet for providing the output current and voltage of the current starving transistor 803 to the inlet of the transistor 802.
  • the transistors 802 and 803 are NMOS transistors, a's shown in Figure 8.
  • the current starving transistor 803 is placed between source voltage VSS and transistor 802, so that the change from the LOW state into the HIGH state would not be affected by the current starving.
  • the IN of the shift register block L2 is also in a HIGH state and the OUT of the shift register block is in a LOW state due to the affect of the transistors 803 and 802, i.e., the transistor 801 is non- conductive and the transistors 803 and 802 are conductive.
  • the state of the IN of the shift register block L2 changes into a LOW state
  • the transistor 802 changes to non-conductive and the transistor 801 changes to conductive. Therefore, the OUT of the shift register block L2 changes from a ' LOW state into a HIGH state.
  • the structure and the methods can be used for refreshing information in an analog memory with principles of an A/D/A (Analog-to-Digital-to-Analog) converter.
  • A/D/A Analog-to-Digital-to-Analog
  • the amount of the A/D/A converters that must be integrated into a chip equals to the amount of the processors. Since the amount of the processors that are tend to be implemented into one chip is over 10 000, the space required by one A/D/A converter in a chip is tend to be minimized.
  • the implementation according to the embodiments of the present invention can also be used to define scaling of the current mirror on the basis of a quantity that is converted.
  • the implementation can also be used e.g., to generate constant currents to various current mode applications.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

La présente invention se rapporte à un convertisseur analogique-numérique A/N comprenant une partie de convertisseur numérique-analogique N/A, des moyens de mesure que l'on compare, des moyens d'acheminement d'un résultat de comparaison vers des moyens logiques de commande qui envoient des signaux de commande vers la partie de convertisseur N/A. La logique de commande comprend au moins un registre à décalage asynchrone achemine des signaux de commande vers le circuit de logique de commande après le traitement d'un signal de commande reçu dans le registre à décalage asynchrone, ledit signal de commande étant soit un signal DEBUT, soit un signal de commande provenant d'un registre à décalage asynchrone à bit antérieur. La présente invention se rapporte également à un procédé de commande d'une fonction d'une échelle de comptage de courant, ladite échelle comprenant des moyens de commutation, des moyens de mise à l'échelle d'une mesure saisie, et des moyens d'acheminement de la mesure saisie mise à l'échelle.
EP03702679A 2002-02-18 2003-02-17 Convertisseur analogique-numerique, echelle de comptage de courant et procede de commande d'une fonction de l'echelle de comptage de courant Withdrawn EP1540822A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FI20020324A FI20020324A0 (fi) 2002-02-18 2002-02-18 Analogia-digitaalimuunnin, virtaskaalaaja ja menetelmä virtaskaalaajan toiminnon ohjaamiseksi
FI20020324 2002-02-18
PCT/FI2003/000115 WO2003069782A2 (fr) 2002-02-18 2003-02-17 Convertisseur analogique-numerique, echelle de comptage de courant et procede de commande d'une fonction de l'echelle de comptage de courant

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EP1540822A2 true EP1540822A2 (fr) 2005-06-15

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EP (1) EP1540822A2 (fr)
AU (1) AU2003205802A1 (fr)
FI (1) FI20020324A0 (fr)
WO (1) WO2003069782A2 (fr)

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Publication number Priority date Publication date Assignee Title
JPH0761019B2 (ja) * 1986-06-19 1995-06-28 日本電気株式会社 アナログ・デイジタル変換器
US4777470A (en) * 1987-09-28 1988-10-11 Burr-Brown Corporation High speed successive approximation register in analog-to-digital converter
US5377248A (en) * 1988-11-29 1994-12-27 Brooks; David R. Successive-approximation register
EP0766405A1 (fr) * 1995-09-29 1997-04-02 STMicroelectronics S.r.l. Régistre à approximations successives sans redondance

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KINNIMENT D.J. ET AL: "Towards asynchronous A-D conversion", FOURTH INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, 30 March 1998 (1998-03-30), LOS ALAMITOS, CA, USA, pages 206 - 215, XP010274562 *
See also references of WO03069782A3 *

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FI20020324A0 (fi) 2002-02-18
WO2003069782B1 (fr) 2004-02-19
WO2003069782A3 (fr) 2003-11-20
WO2003069782A2 (fr) 2003-08-21
AU2003205802A1 (en) 2003-09-04

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