EP1508166A2 - Electronic component comprising external surface contacts and a method for producing the same - Google Patents
Electronic component comprising external surface contacts and a method for producing the sameInfo
- Publication number
- EP1508166A2 EP1508166A2 EP03755901A EP03755901A EP1508166A2 EP 1508166 A2 EP1508166 A2 EP 1508166A2 EP 03755901 A EP03755901 A EP 03755901A EP 03755901 A EP03755901 A EP 03755901A EP 1508166 A2 EP1508166 A2 EP 1508166A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- surface contacts
- electronic component
- rewiring structure
- carrier
- contacts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 94
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 229920002120 photoresistant polymer Polymers 0.000 claims description 79
- 238000000034 method Methods 0.000 claims description 76
- 230000008021 deposition Effects 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 31
- 238000005516 engineering process Methods 0.000 claims description 27
- 229910000679 solder Inorganic materials 0.000 claims description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 19
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 18
- 239000012876 carrier material Substances 0.000 claims description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 229910052763 palladium Inorganic materials 0.000 claims description 9
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- 229910000881 Cu alloy Inorganic materials 0.000 claims description 5
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 3
- 238000001746 injection moulding Methods 0.000 claims description 3
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- 229910001020 Au alloy Inorganic materials 0.000 claims description 2
- 229910001252 Pd alloy Inorganic materials 0.000 claims description 2
- 239000003353 gold alloy Substances 0.000 claims description 2
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims description 2
- MEKOFIRRDATTAG-UHFFFAOYSA-N 2,2,5,8-tetramethyl-3,4-dihydrochromen-6-ol Chemical compound C1CC(C)(C)OC2=C1C(C)=C(O)C=C2C MEKOFIRRDATTAG-UHFFFAOYSA-N 0.000 claims 7
- 230000015572 biosynthetic process Effects 0.000 claims 1
- XPPWAISRWKKERW-UHFFFAOYSA-N copper palladium Chemical compound [Cu].[Pd] XPPWAISRWKKERW-UHFFFAOYSA-N 0.000 claims 1
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 claims 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 99
- 150000001875 compounds Chemical class 0.000 description 47
- 150000002739 metals Chemical class 0.000 description 9
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 8
- 238000004049 embossing Methods 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- 239000011888 foil Substances 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 229910052742 iron Inorganic materials 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 229910000640 Fe alloy Inorganic materials 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
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- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
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- 229910002804 graphite Inorganic materials 0.000 description 2
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- 239000011159 matrix material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910000570 Cupronickel Inorganic materials 0.000 description 1
- ZLDYSCAZANNIEY-UHFFFAOYSA-N [Ni].[Au].[Au] Chemical compound [Ni].[Au].[Au] ZLDYSCAZANNIEY-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- RYZVSJQWUZPQNI-UHFFFAOYSA-N copper gold Chemical compound [Cu].[Au].[Au] RYZVSJQWUZPQNI-UHFFFAOYSA-N 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- PDHBRMFYIFYPQM-UHFFFAOYSA-N gold silver Chemical compound [Ag].[Au].[Au] PDHBRMFYIFYPQM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 238000005088 metallography Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C43/00—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor
- B29C43/32—Component parts, details or accessories; Auxiliary operations
- B29C43/58—Measuring, controlling or regulating
- B29C2043/5825—Measuring, controlling or regulating dimensions or shape, e.g. size, thickness
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Definitions
- the invention relates to an electronic component with external surface contacts and with a rewiring structure and with a semiconductor chip and a method for producing the same in accordance with the preamble of the independent claims.
- Electronic components with external surface contacts and with a rewiring structure which rewires the microscopic contact surfaces of a semiconductor chip to macroscopically large external surface contacts, have additional complex rewiring plates or rewiring foils with appropriately incorporated through contacts or with provided bonding channels as carriers of the rewiring structure.
- microscopic is understood to be an order of magnitude that can only be measured with a light microscope, while macroscopically large
- a rewiring structure is understood to mean the metallic structure itself, which can have contact connection areas in the order of magnitude of the contact areas of the semiconductor chip, rewiring lines in the micrometer and / or in the submicron range and external contact areas in the order of magnitude of the outer area contacts.
- Electronic components of this type consequently not only have a rewiring structure, but also a rewiring support which has a rewiring structure as the rewiring body and is cast into the plastic housing compound.
- the metal layers on the rewiring Tension carriers from which the rewiring structure is constructed can have roll structures if the rewiring carriers have insulating foils or insulating plates laminated with rolled foils. They can have a roughly crystalline structure if the metal layers are sprayed on or vapor-deposited on the rewiring carrier or applied by means of sinter metallography or produced by means of a dipping process. This results in a wide variety of crystallographic metal structures for the rewiring layers and is a characteristic of the metals deposited as a rewiring structure.
- a redistribution structure for an electronic component is associated with the fact that an additional redistribution body, which has the redistribution structure, has to be included in the plastic housing of the electronic component, thus requiring additional space for the electronic component and complex manufacturing processes for one Rewiring bodies are connected.
- a semiconductor component with contacts located on the underside of the outer surfaces and a method for the production thereof are known, the outer surface contacts having chemically or galvanically selectively deposited metal.
- the known method is suitable for the production of external surface contacts and has the disadvantage that a rewiring body cannot be represented, and the electronic component has the disadvantage that it does not have any rewiring structure.
- the object of the invention is to reduce the space requirement of an electronic component with rewiring structure and to create an electronic component that is structurally compatible has no rewiring carrier for a rewiring structure and is inexpensive to manufacture.
- an electronic component with external surface contacts and with a rewiring structure and with a semiconductor chip that has contact surfaces is specified.
- the outer surface contacts are electrically connected to the contact surfaces of the semiconductor chip at least via the rewiring structure.
- the semiconductor chip and the rewiring structure are embedded in a plastic housing compound, while the outer surface contacts on the underside of the electronic component are freely accessible. Further, the outer area contacts and the rewiring structure have chemically or galvanically selectively sustane- ⁇ nes metal.
- Such an electronic component has the advantage that the space requirement for attaching a rewiring structure is minimized by the fact that no rewiring supports are to be provided for the rewiring structure, but this function is taken over directly by the embedding of the rewiring structure in the plastic housing compound.
- the electronic component has the advantage that the metal material of the rewiring structure has a chemically or galvanically selectively deposited metal, which is distinguished by its fine crystallinity and also opens up the possibility of extremely finely structured rewiring. tion structures partially in the submicron range, as far as it relates to the rewiring lines of the rewiring structure.
- the size of the contact pads or bond fingers required to connect the rewiring structure to the contact areas of the semiconductor chip is dependent on the size or the magnitude of the contact areas and the connection technology between the contact areas of the semiconductor chip and contact pads of the rewiring structure. While with a flip-chip connection technology inner surface contacts of the order of a few square micrometers can be realized, with the bonding technology the miniaturization of the contact surfaces of the semiconductor chip and the contact connection surfaces of the rewiring structure is achieved by the
- Bond wire diameter determined and can not be minimized as a result, since the bond wires have diameters between 15 and 50 microns.
- the semiconductor chip can be mounted on the rewiring structure by means of flip-chip technology, the contact areas of the semiconductor chip being electrically connected to contact connection areas of the rewiring structure via inner area contacts.
- these inner surface contacts can be a few square micrometers in size, so that the flip-chip technology with inner surface contacts can have an extremely dense contact structure and thus an extremely fine grid dimension for the spacing of the contact connection surfaces can be realized.
- a semiconductor chip using flip-chip technology can be mounted on the rewiring structure, the contact surfaces of the semiconductor chip being connected to contacts via internal contact balls. Clock pads of the rewiring structure are connected.
- Such a technology which works with contact balls or bumps made of solder material, has structures that require a connection area of several tens of square micrometers between the contact area of the semiconductor chip and the contact connection areas of the rewiring structure. The user can thus choose from three different orders of magnitude, the largest area requirement occurring in the case of bond connections between contact areas of the semiconductor chip and contact connection areas of the rewiring structure, which, because of the bond wires, require several hundred square micrometers.
- contact bumps or contact balls that are smaller by an order of magnitude can be used for the connection between contact areas and contact connection areas, and finally electrical connections that are smaller by another order of magnitude can be implemented in a flip-chip technique with internal surface contacts.
- the electronic component With all three orders of magnitude for the connection between contact areas and contact connection areas, the electronic component has the advantage that there is a considerable saving in space since the rewiring structure does not require an additional rewiring carrier.
- the electronic component is equipped with a semiconductor chip using bonding technology
- its rear side can be mounted on the rewiring structure via an insulating adhesive layer.
- the contact areas on the active top side of the semiconductor chip are connected via bond wires to contact connection areas of the rewiring structure in the vicinity of the semiconductor chip, the area contacts being based on the structure of the electronic component according to the invention can be arranged below the area of the semiconductor chip, so that with this embodiment of the invention, surface contacts can be distributed over the entire underside of the electronic component and the rewiring structure enables a so-called "fan-in" arrangement for the outer surface contacts despite bond connection technology.
- the electronic component can additionally have vias which are chemically or galvanically selectively deposited on the rewiring structure and which connect the underside of the electronic component with the outer surface contacts to the opposite top of the electronic component.
- This provision of chemically or galvanically selectively deposited through contacts enables stacking of several individual electronic components to form a stacked module with a continuous electrical connection from the top component of the stack to the bottom component of the stack.
- the through contacts are embedded in the plastic housing compound and surround the respective semiconductor chip.
- the chemically or galvanically deposited metal can comprise nickel or a nickel alloy.
- an etchable carrier material made of copper or iron alloys for chemical or galvanic deposition can be used for the deposition of such a chemically or galvanically produced nickel alloy, so that an etching removal of the carrier material for the rewiring structure and the external surface contacts is possible because the etching process at the interface with the nickel can be stopped by a reduced etching rate.
- Chemically or galvanically deposited metals also offer the same advantages Silver or silver alloys or gold or gold alloys. In each of these cases, an etchable carrier made of copper or an iron alloy can be used. Palladium or a palladium alloy can also be used chemically or galvanically on a preformed etchable carrier to form the rewiring structure and the outer surface contacts.
- a layer sequence of palladium-nickel-palladium can be constructed in a similar form, and finally layer sequences can also be used which consist of palladium-copper-palladium or gold-copper-gold, but the noble-metal layers of gold or palladium must be made sufficiently thick there to be able to cope with etching To survive attack on the copper or the iron of the carrier material.
- a method for producing an electronic component with outer surface contacts and with a rewiring structure, the outer surface contacts and the rewiring structure having chemically or galvanically selectively deposited metal can be carried out with the following method steps.
- recesses are made in an electrically conductive carrier in a predetermined grid dimension for chemical or galvanic deposition of the outer surface contacts of the electronic component. Different materials are used for the outer surface contacts and for the top of the carrier.
- a structured photoresist layer is applied to such a carrier, leaving the cutouts for the outer surface contacts and for areas in which the rewiring structure is to be deposited chemically or galvanically. This is followed by a method step in which the material for the surface contacts and for the rewiring structure is chemically or galvanically deposited on the carrier in the exposed surfaces of the photoresist layer. After the deposition has been completed, the structured and insulating photoresist layer can be removed. Thus, the electrically conductive carrier now has outer surface contacts in its recesses and a rewiring structure that was structured by the photoresist layer.
- a semiconductor chip is now applied to this rewiring structure by connecting the contact areas of the semiconductor chip to contact connection areas of the rewiring structure.
- the semiconductor is then embedded chips and the rewiring structure in a plastic package.
- the carrier is then separated from the cast component, exposing the outer surface contacts.
- a solder-stop layer on the component side, which has the surface contacts, can be applied while leaving the outer surface contacts free.
- Such a method has the advantage that it can be used to implement electronic components that are not available in such compact form with a functional rewiring structure and that cannot be produced with the previously known means for representing a rewiring structure. Rather, new ways are described here in order to introduce a rewiring structure directly into the plastic housing compound without an additional carrier, so that the otherwise required rewiring carrier can be saved.
- the rewiring structure can be provided in order to achieve a so-called "fan-out” effect, in which contact areas of a semiconductor chip are spread over a larger area with a macroscopic grid size by a microscopic grid size corresponding rewiring structure are to be distributed and, on the other hand, a "fan-in” effect can be achieved for semiconductor chips connected via bonding wires, in which the Surface below the semiconductor chip external surface contacts can be arranged for more intensive use of the underside of the component.
- Another advantage of the present invention is that such a carrier can be prepared for several or even a large number of electronic components, on which a large number of electronic components are created in parallel or simultaneously by the same steps as for a single electronic component be used. Only after the carrier has been removed or separated from the plastic housing compound can the plastic housing compound be divided into individual electronic components.
- Such an exemplary embodiment of the method can considerably reduce the costs for the production of electronic components, in particular if the loss carrier is provided in the form of a wafer, because in this case proven semiconductor wafer technologies can preferably be used to produce the rewiring structures.
- the creation of recesses in a predetermined grid dimension in a metallic carrier can be done in two different methods.
- the cutouts can be made using embossing technology, and on the other hand the cutouts can be made using etching technology.
- embossing tools have to be prepared in the embossing technique, which insert the recesses extremely precisely into a copper plate, for example, in the etching technique, a very fine structuring of the outer surface contacts can be achieved by first covering the carrier material with a structured photoresist layer and then the recesses be etched out of the carrier plate in areas where no photo paint layer is present. After both process variants, a carrier material is finally available, which can be provided extremely precisely with external surface contacts in subsequent steps.
- the first photoresist layer is removed and a second structured photoresist layer is applied, which leaves those surface regions which are to be provided with a rewiring structure free. These areas can then be galvanically or chemically filled with a metal in a second deposition step, and the second structured photoresist layer can then be removed.
- the carrier material has a rewiring structure and an underlying structure made of external surface contacts, which are arranged in a predetermined grid dimension.
- the advantage of this second method variant is that the deposition process for the outer surface contacts is separated from the deposition process for the rewiring structure, so that considerably thicker surface contacts can be realized compared to the thickness of the rewiring structure.
- an electrically conductive film is used as the carrier, into which recesses for forming surface contacts of the electronic component are stamped.
- One of the- like electrical conductive film can be removed from the plastic housing material after completion of the electronic components and thus facilitates the manufacture of a variety of electronic components, since no carrier material is etched from the underside of the electronic components.
- an electrically conductive carrier material such as a conductive film
- a non-conductive carrier material can also be used for the carrier, on which a conductive layer is deposited. This conductive layer can be a metal layer or a layer of graphite.
- the carrier made of a film is mechanically supported by an adapted molding tool for the step of embedding the component in a plastic housing compound.
- an adapted molding tool for the step of embedding the component in a plastic housing compound.
- this procedure has the advantage that the molding tool can be used several times and only the foil is consumable, such foils being much cheaper to produce compared to a mechanically stable carrier made of metal ,
- Through contacts can be provided on the carrier.
- a further structured photoresist layer is applied to the carrier after completion and deposition of the surface contacts and the rewiring structure in a thickness that is greater than the thickness of the semiconductor chip provided for the electronic component.
- the structured photoresist layer leaves the outer surface contacts free, which are used for the deposition of the through contacts. they are.
- the further photoresist layer has openings in this area, which are then filled up chemically or galvanically to make vias.
- This further photoresist layer which is adapted to the thickness of the semiconductor chip, can then be removed, so that external surface contacts, a rewiring structure and additional through contacts, which extend from the underside of the electronic component to the top of the electronic component, are now completed on the carrier.
- a semiconductor chip using known technology, such as flip-chip technology or bonding technology, can be fitted into a structure prepared in this way and electrically connected.
- a plastic housing compound One possibility of embedding the components now present in a plastic housing compound can be done by means of a molding tool for an injection molding technique, the molding tool having cavities that are adapted to the outer housing shape of the plastic housing compound. Another possibility of applying a plastic housing compound is to use a dispensing method in which the plastic housing compound is sprayed on.
- a carrier in the form of a wafer is provided, which is first provided with cutouts, all process steps for the production of a large number of electronic components then being carried out together and finally after removal of the carrier in the form of a wafer the large number of electronic components , which are packaged in a plastic housing compound, are separated into a plurality of individual electronic components by dividing the plastic housing compound.
- the device according to the invention and the method according to the invention increase the design options for existing packaging systems for semiconductor chips and at the same time reduce the space required for an electronic component with a semiconductor chip. Furthermore, the costs for the production of such electronic components are reduced in that a complex rewiring body is unnecessary. Instead, a removable copper plate with additional recesses to form the outer surface contacts can be formed, these recesses being carried out by an embossing process during the production of the copper plate or by a one-sided etching before the application of surface contacts and rewiring structures.
- smaller cutouts for the outer surface contacts of the through contacts te are provided and larger cutouts for the outer surface contacts, for example to arrange macroscopic solder bumps or solder balls on the outer surface contacts and through contacts with diameters in the order of magnitude of bond wires on the surface contacts.
- a special photoresist and a special technique for producing the photoresist layer can be used, so that vertical side walls of the openings in the photoresist layer for the vias are created during exposure and development of the photoresist layer.
- the openings for the through contacts can also be filled with refractory soldering material, which is evenly distributed in the openings for the through contacts in a flow process. The through contacts can then be cleaned from the top and also provided with an additional layer of precious metal.
- the electronic component according to the invention is extremely robust. All contacts are embedded in corresponding resin components of the plastic housing compound, so that the risk of damage to the rewiring structure or the through contacts is minimized during a test and handling phase.
- the omission of the rewiring carrier means that the overall component height is extremely low, so that components with a component height of less than 400 micrometers can typically be realized, which makes double-stacked components with a height of less than 900 micrometers possible.
- FIG. 1 shows a schematic cross-sectional view of an electronic component of a first embodiment of the invention
- FIG. 2 shows a schematic cross-sectional view of an electronic component of a second embodiment of the invention
- FIG. 3 shows a schematic cross-sectional view of an electronic component of a third embodiment of the invention
- FIG. 4 shows a schematic cross-sectional view of a first stack of two electronic components of the third embodiment of the invention
- FIG. 5 shows a schematic cross-sectional view of a second stack of two electronic components of the third embodiment of the invention
- FIG. 6 shows a schematic cross-sectional view of a third stack of four electronic components of the third embodiment of the invention
- FIG. 7 shows a partially broken perspective view of a fourth stack of two electronic components of a further embodiment of the invention, characters
- FIG. 8 shows a schematic cross-sectional view of a carrier plate with structured photoresist layer
- FIG. 9 shows a schematic plan view of a carrier plate with a structured photoresist layer
- FIG. 10 shows a schematic cross-sectional view of a carrier plate with etched cutouts for external surface contacts
- FIG. 11 shows a schematic top view of a carrier plate with etched cutouts for external surface contacts
- FIG. 12 shows a schematic cross-sectional view of a carrier plate with a structured photoresist layer for the selective deposition of a rewiring structure and for the deposition of external surface contacts
- FIG. 13 shows a schematic plan view of a carrier plate with a structured photoresist layer for the selective deposition of a rewiring structure and for the selective deposition of external surface contacts
- FIG. 14 shows a schematic cross-sectional view of a carrier plate with an electrodeposited Wiring structure and with galvanically separated external surface contacts
- FIG. 15 shows a schematic plan view of a carrier board with a rewiring structure deposited on the carrier board and of external surface contacts
- FIG. 16 shows a schematic cross-sectional view of a carrier plate with an applied semiconductor chip
- FIG. 17 shows a schematic top view of a carrier plate with an applied semiconductor chip
- FIG. 18 shows a schematic cross-sectional view of a carrier plate provided with a plastic housing compound
- FIG. 19 shows a schematic plan view of a carrier plate provided with a plastic housing compound
- FIG. 20 shows a schematic cross-sectional view of an electronic component after the carrier has been removed from the component
- FIG. 21 shows a schematic bottom view of an electronic component after the carrier has been removed from the component
- FIG. 22 shows a schematic cross-sectional view of an electronic component after application of a solder stop layer
- FIG. 23 shows a schematic bottom view of an electronic component after application of a solder stop layer
- FIG. 24 shows a schematic cross-sectional view of a
- Carrier plate with a structured first photoresist layer for the selective deposition of external surface contacts
- FIG. 25 shows a schematic top view of a carrier plate with a structured photoresist layer for the selective deposition of external surface contacts
- FIG. 26 shows a schematic cross-sectional view of a carrier plate with electrodeposited outer surface contacts
- FIG. 27 shows a schematic plan view of a carrier plate with outer surface contacts deposited on the carrier plate
- FIG. 28 shows a schematic cross-sectional view of a carrier plate with a structured second photoresist layer for the selective deposition of a rewiring structure
- FIG. 29 shows a schematic plan view of a carrier plate with a second photoresist layer for the selective deposition of a rewiring structure
- FIG. 30 shows a schematic cross-sectional view of a carrier plate with an electrodeposited rewiring structure
- FIG. 31 shows a schematic plan view of a carrier board with a rewiring structure deposited on the carrier board
- FIG. 32 shows a schematic cross-sectional view of a
- Carrier plate with a structured additional photoresist layer for the selective deposition of through contacts
- FIG. 33 shows a schematic plan view of a carrier plate with a further structured photoresist layer for the selective deposition of through contacts
- FIG. 34 shows a schematic cross-sectional view of a carrier plate with electrodeposited through contacts after removal of the photoresist layer
- FIG. 35 shows a schematic plan view of a carrier plate with through contacts deposited on the carrier plate after removal of the photoresist layer
- FIG. 36 shows a schematic cross-sectional view of a carrier plate provided with a plastic housing compound
- FIG. 37 shows a schematic plan view of a carrier plate provided with a plastic housing compound
- FIG. 38 shows a schematic cross-sectional view of an electronic component after application of a solder stop layer
- FIG. 39 shows a schematic bottom view of an electronic component after application of a solder stop layer.
- FIG. 1 shows a schematic cross-sectional view of an electronic component of a first embodiment of the invention.
- Reference symbol 2 denotes surface contacts of the electronic component 1.
- Reference symbol 3 denotes a rewiring structure which, like the surface contacts, has a chemically or galvanically deposited metal.
- the reference number 4 denotes a semiconductor chip with an active top side 9 and a passive rear side 8.
- the reference number 5 denotes contact areas on the active 0 top side 9 of the semiconductor chip 4.
- the reference number 7 denotes contact connection areas of the rewiring structure which correspond to the positions of the contact areas 5 of the Semiconductor chips 4 can be adapted.
- the reference symbol 12 denotes the underside of the electronic component on which the surface contacts 2 are arranged in a grid dimension r.
- the reference symbol d denotes the thickness of the semiconductor chip 4, which is less than the thickness D of the plastic housing composition 6.
- this electronic component 1 has the microscopic contact areas 5 of the semiconductor chip 4 to macroscopically large external area contacts 2 via rewiring lines 27 are performed, no rewiring carrier. Rather, the function of the rewiring carrier or rewiring body is taken over by the plastic housing compound 6, so that the space requirement of the electronic component 1 can be minimized.
- the semiconductor chip 4 is arranged in the plastic housing compound on the rewiring structure 3, which has a chemically or galvanically selectively deposited metal, using flip-chip technology.
- the microscopic contact areas 5 are partially connected to external area contacts 2 with the help of the rewiring structure 3, which are arranged beyond the edge of the semiconductor chip 4 in the plastic housing compound 6.
- This arrangement is also called a "fan-out" arrangement. It is advantageously used in this embodiment of the invention in order to accommodate a sufficient number of macroscopic surface contacts 2 on the underside 12 of the electronic component 1.
- inner surface contacts 28 are only a few square micrometers in size, while the outer surface contacts 2 can be several tens to several hundred square micrometers in size.
- inner contact balls or bumps can also produce the connection between the contact surfaces 5 of the semiconductor chip 4 and the contact connection surfaces 7 of the rewiring structure 3.
- Such internal contact bumps or contact balls increase the thickness D of the plastic housing composition 6 by almost 50 microns, since internal ones Contact balls or bumps are made much thicker than the microscopic inner surface contacts 28, which can be represented in thicknesses of a few micrometers.
- the component 1 can have a solder stop layer 18 on the underside 12, which covers the underside of the rewiring structure 3 and only leaves the outer surface contacts 2 free.
- the outer surface contacts 2 can also have chemically or galvanically deposited metal and can have the same material as the rewiring structure 3.
- Nickel, palladium, gold or silver are used as chemically or galvanically deposited metals or a layer sequence of these metals is provided. Alloys of these metals can also be used. Layer sequences of gold nickel gold, palladium nickel palladium, gold silver gold have proven successful for layer sequences of these metals, the intermediate layer also being able to have copper if the outer layers have a thickness which can withstand any etching attack by a copper etch. However, this requirement only has to be met if a sacrificial cathode made of copper is used for the galvanic deposition of the surface contacts and the rewiring structure in the manufacture of such an electronic component.
- rewiring lines 27 can be represented in a line width in the submicron range.
- FIG. 2 shows a schematic cross-sectional view of an electronic component 1 of a second embodiment of the invention.
- Components with the same functions as in FIG. 1 are identified by the same reference symbols and are not discussed separately.
- a difference between the second embodiment of the invention according to FIG. 2 and the first embodiment of the invention according to FIG. 1 is that the semiconductor chip is not arranged in the plastic housing composition 6 using flip-chip technology, but with its rear side 8 via an insulating adhesive layer 29 is mounted on the rewiring structure 3.
- the contact areas 5 arranged on the active top side 9 of the semiconductor chip 4 are connected via bond wires 10 to the contact connection areas 7, which are embodied here as bond fingers 30, to the rewiring structure and thus to the outer area contacts 2.
- the order of magnitude of the bond fingers 30 and the contact areas 5 depends on the diameter of the bond wires 10 and is of the order of magnitude of several tens of micrometers, preferably between 15 and 50 micrometers.
- the outer surface contacts 2 can be arranged below the semiconductor chip 4, which is also referred to as a "fan-in" arrangement.
- a metallic chip island is not provided under the semiconductor chip 4 in this second embodiment of the invention, a centrally arranged outer surface contact 2 via the rewiring structure 3 and a speaking bond connection 10 a ground connection to the active top of the semiconductor chip 4, which can take over the function of grounding a chip island.
- FIG. 3 shows a schematic cross-sectional view of an electronic component of a third embodiment of the invention.
- Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
- the third embodiment of the invention according to FIG. 3 differs from the previous embodiments of the invention in that through contacts 11 are arranged on the rewiring structure and extend from the bottom 12 of the electronic component 1 to the top 13 of the electronic component 1.
- the material b of the via 11 can likewise have a chemically or galvanically deposited metal or can be produced by means of molten solder.
- the outer surface contact 2, which belongs to the through contact 11, can have a coating on its underside, which facilitates soldering of the through contact 11 to other through contacts 11. The same can be carried out on the top 13 for the via 11.
- Both the outer surface contact 2 and the through contact 11 can have significantly smaller diameters than the macroscopic outer surface contacts 2 for the connection to the contact surfaces 5 of the semiconductor chip 4. This makes it possible to arrange surface contacts 11 around the semiconductor chip 4, which the Do not significantly increase the space requirement of the plastic housing compound 6.
- the total thickness H of such an electronic component can be less than 400 micrometers, preferably in the range from 250 to 300 micrometers. Such a low height of the electronic component 1 is achieved in particular by the flip-chip assembly of the semiconductor chip 4 and by the use of inner surface contacts 28 for the connection between the contact surfaces 5 of the semiconductor chip 4 and the contact connection surfaces 7 of the rewiring structure 3.
- FIG. 4 shows a schematic cross-sectional view of a first stack of two electronic components 1 of the third embodiment of the invention.
- Components with the same functions as in the previous figures are identified by the same reference symbols and are not discussed separately.
- Such a stack of two electronic components 1 of the third embodiment of the invention, as shown in FIG. 4, can be realized with a total height H of less than 900 micrometers, preferably the total height H is between 500 and 600 micrometers.
- the height H can be reduced further.
- the thickness of the rewiring carrier is saved in this stack compared to stacks with U wiring boards or rewiring bodies, since in this embodiment of the invention only rewiring structures are made from a chemically or galvanically deposited metal and no supporting rewiring carriers are required.
- FIG. 5 shows a schematic cross-sectional view of a second stack of two electronic components 1 of the third embodiment of the invention.
- Components with the same functions as in the previous figures are identified by the same reference numerals and are not discussed separately.
- the stack shown here in FIG. 5 differs from the stack in FIG. 4 in that solder balls 31 or solder bumps are arranged on the surface contacts 2 of the lower electronic component 1, which connect the electronic component 14 from several electronic components 1 to one another higher-level circuit structure, for example on a circuit board, facilitate.
- FIG. 6 shows a schematic cross-sectional view of a third stack of four electronic components 1 of the third embodiment of the invention. Components with same
- the total height H of this module 14 made of vertically stacked electronic components 1 is less than 1.8 millimeters, preferably between 1000 and 1200 micrometers, and using thinly ground semiconductor chips 4, total thicknesses of 250 micrometers can be achieved. In the total height H will In this embodiment of the invention, at least four times the thickness of a rewiring carrier in the form of a rewiring plate is saved, so that extremely compact electronic modules 14 can be produced.
- FIG. 7 shows a partially broken perspective view of a fourth stack of two electronic components 1 of a further embodiment of the invention.
- Components with the same functions as in the previous figures are identified by the same reference numerals and are not discussed separately.
- the number of vias 11 in this embodiment of the invention is thirty-six.
- thirty-six rewiring lines 27 are to be provided in the individual component levels. With this high number of rewiring lines, it is essential that these rewiring lines 27 between the contact connection areas 7 and the through contacts 11 can be made correspondingly narrow, which can be achieved in particular by copper lines or nickel lines.
- the through contacts 11 can have a significantly smaller diameter than outer surface contacts 2, so that a relative compact electronic module 14 with corresponding through contacts can be realized.
- FIGS. 8 to 23 show basic sketches of the production of an electronic component 1 by means of a first implementation example of the method according to the invention.
- Components in the following FIGS. 8 to 23, which fulfill the same functions as in the previous figures, are identified with the same reference symbols and are not discussed separately.
- FIG. 8 shows a schematic cross-sectional view of a carrier plate 26 with a structured photoresist layer 17.
- the structured photoresist layer 17 has openings 32 at the positions at which depressions or cutouts for external surface contacts are to be introduced into the carrier 15 in a grid dimension r.
- FIG. 9 shows a schematic plan view of a carrier plate with structured photoresist layer 17.
- the circular openings 32 in the photoresist layer 17 correspond to the dimensions of the recesses to be produced for external surface contacts of an electronic component in a predetermined grid dimension r.
- the arrows A-A indicate the sectional planes in which the associated cross-sectional views of FIG. 8 and the following cross-sectional views are included.
- FIG. 10 shows a schematic cross-sectional view of a carrier plate 26 with etched cutouts 16 for external surface contacts of an electronic component.
- the recesses 16 in the carrier plate 26 made of copper or a copper alloy are etched relatively flat in this lead-through method. drive the present invention. Iron or an iron alloy can also be provided as the carrier material for this first exemplary embodiment of the method.
- FIG. 11 shows a schematic top view of a carrier plate 26 with etched cutouts 16 for external surface contacts. These recesses are only limited in principle to nine recesses and are arranged in a matrix with a grid dimension r. However, the number of external surface contacts can be increased as desired, as shown in FIG. 7.
- FIG. 12 shows a schematic cross-sectional view of a carrier plate 26 with a structured photoresist layer 17 for the selective deposition of a rewiring structure and for the simultaneous selective deposition of external surface contacts.
- a carrier plate 26 made of copper or a copper alloy prepared in this way has openings in the photoresist layer 17 which correspond on the one hand to the geometry of the outer surface contacts 2 and on the other hand to openings 32 which correspond to the rewiring structure 3 to be formed.
- the flat geometry is shown in the next figure.
- FIG. 13 shows a schematic plan view of a carrier plate with a structured photoresist layer 17 for the selective deposition of a rewiring structure and for the selective deposition of external surface contacts 2.
- the depressions 16 already shown in FIG. 1 are shown, which are from the photoresist layer 17 are kept free and additionally structures are provided for rewiring 3, the microscopic contact areas of the semiconductor chip 4 with the macroscopically large ones Connect surfaces of the outer surface contacts 2, which are to form in the cutouts 16.
- FIG. 14 shows a schematic cross-sectional view of a carrier plate 26 with an electrodeposited rewiring structure 3 and with an electrodeposited outer surface contacts 2 after removal of the photoresist layer 17 shown in FIGS. 12 and 13 the rewiring structure 3 is produced in a galvanic deposition step in which the metallic carrier 15 is placed on the cathode potential of a corresponding electrolyte bath. Due to the insulation by the photoresist layer 17, as shown in FIG. 13, it is prevented that large-area deposition of metal on the carrier plate 26 can take place. Rather, a finely crystalline metal such as nickel, palladium, gold or silver is deposited in the thickness of the photoresist layer in the openings provided in the structured photoresist 17 shown in FIG.
- a finely crystalline metal such as nickel, palladium, gold or silver is deposited in the thickness of the photoresist layer in the openings provided in the structured photoresist 17 shown in FIG.
- FIG. 15 shows a schematic plan view of a carrier plate 26 with a rewiring structure 3 deposited on the carrier plate 26 and the outer surface contacts 2 after removal of the photoresist layer 17 shown in FIG. 13. While in this plan view only nine outer contact surfaces 2 can be seen, the number the outer contact surfaces 2 can be increased as desired. In this embodiment of the invention, a central outer contact surface 2 is in the center of the
- FIG. 11 shows the microscopically small contact connection areas 7 of each rewiring line, the size ratio shown here between microscopic contact connection areas 7 and external area contacts 2 not being drawn to scale, especially since the contact connection areas 7 can only be a few square micrometers in size, while the external contact areas up to a few hundred square micrometers.
- FIG. 16 shows a schematic cross-sectional view of a carrier plate 26 with an applied semiconductor chip 4.
- the semiconductor chip 4 is shown in FIG.
- the inner surface contacts 28 can have materials that enable diffusion soldering on the rewiring structure 3. In diffusion soldering, intermetallic phase transitions occur which ensure an extremely stable electrical connection between the contact surfaces of the semiconductor chip 4 and the contact connection surfaces 7 of the rewiring plate via the inner surface contacts 28.
- FIG. 17 shows a schematic top view of a carrier plate 26 with an attached semiconductor chip 4.
- This top view of the semiconductor chip 4 can be seen from the rear 8, which is why the microscopic contact areas 5 and the associated contact connection areas 7 of the rewiring structure 3 are shown in broken lines.
- the contact pads 7 are in a so-called “fan Out "arrangement moved outwards, since the base area of the semiconductor chip 4 is not sufficient to accommodate the macroscopic outer surface contacts in the area.
- the outer surface contacts 2 are thus visible in this embodiment of the invention and the illustration in FIG. 17. From the rewiring structure 3 only short rewiring line sections 27 can be seen, since the rest of the rewiring structure is covered by the semiconductor chip 4.
- FIG. 18 shows a schematic cross-sectional view of a carrier plate 26 provided with a plastic housing compound 6.
- FIG. 19 shows a schematic plan view of a carrier plate provided with a plastic housing compound 6, so that the top 0 13 of the electronic component represents an unstructured smooth surface made of a plastic housing compound 6.
- the electronic component which is arranged in the plastic housing compound, is not yet functional, since the metallic carrier plate 26 short-circuits all outer surface conductors and parts of the rewiring structure.
- the metal carrier plate 26 provided as the sacrificial plate which in this exemplary embodiment of the invention consists of a carrier material a that differs from the galvanically deposited b of the outer surface contacts and the rewiring structure, up to the interface between the materials a and b, or the interface between etched off the material a and the plastic housing compound 6.
- the structure shown in FIG. 18 can be immersed in a corresponding etching bath. Due to the difference in the etching rates for copper or copper alloys or nickel and nickel alloys as materials a and b, the etching process can be ended relatively precisely when the transition region between copper and nickel is reached.
- FIG. 20 shows a schematic cross-sectional view of an electronic component 1 after the carrier material has been removed from the component 1, so that the outer surface contacts and also the rewiring structure are now exposed at least on one side and can be accessed from the outside.
- FIG. 21 shows a schematic bottom view of an electronic component 1 after removal of the metallic carrier from the component 1. Both the outer surface contacts 2 and the rewiring structure with their contact connection surfaces 7 are initially exposed on the underside 12 of the electronic component. By attaching a structured solder stop layer, however, the rewiring areas can be covered and only the outer surface contacts 2 remain exposed.
- FIG. 22 shows a schematic cross-sectional view of an electronic component 1 after application of a solder mask 18.
- This solder mask 18 is applied to the underside of the electronic component in order to protect the rewiring structure 3 and, at the same time, the possibility of attaching solder balls on the outer surface contacts to the latter itself limit and prevent the material from flowing along the U wiring lines of the rewiring pattern 3.
- FIG. 23 shows a schematic bottom view of an electronic component 1 after application of a solder stop layer 18. In part, the plastic housing compound 6 can still be seen in the exposed areas of the outer surface contacts, since the openings in the solder resist layer were chosen to be somewhat larger than the diameter of the outer surface contacts second
- a carrier film with embossed recesses for external surface contacts is used.
- the film can be a film which is surface-activated for chemical deposits or an electrically conductive film for galvanic deposits or a film which is coated with a conductive substance such as graphite or metal.
- the further advantage of a method which is based on a carrier film is that the film material and thus the material of the carrier fundamentally have different properties than the material of the surface contacts which, according to the present invention, have a chemically or galvanically deposited metal. Copper can thus also be used directly as the material of the surface contact. Furthermore, the layer sequences of gold, copper, gold, or palladium, copper, or nickel, copper and gold can be produced without any problems, since an etching step is unnecessary when using a carrier film 21.
- the cutouts are arranged in a predetermined grid dimension, which corresponds to the grid dimension of a higher-level circuit, for example on a printed circuit board, in order to connect the electronic component with a to connect the higher-level circuit electrically.
- Cutouts are covered with a first photoresist layer, which is intended to prevent deposition of surface contact material on the surfaces of the carrier film protected by the photoresist layer, so that only the material of the surface contacts is deposited in the cutouts.
- the film can be removed from the underside of the electronic device after removal of the molding tool shown in the previous figures. be removed from the electronic component or dissolved in a corresponding solution without damaging the rewiring structure embedded in the plastic housing compound and the outer surface contacts protruding from the plastic housing compound.
- the electronic component is then completely manufactured and, compared to other technologies, has an extremely low component height, which is less than 400 micrometers, preferably between 250 and 300 micrometers. This component height can further be minimized if the semiconductor chip is thinned to thicknesses d below 100 micrometers before installation.
- a carrier made of a metal or a carrier plate which is at least provided with a metal layer is again assumed.
- further cutouts are provided for external surface contacts of through contacts to be realized.
- the size of one of the recesses can differ from the other recesses in such a way that their diameter is smaller, for example.
- the smaller diameter of the other cutouts ensures that the later vias through the housing of the electronic component have a smaller diameter and thus also take up less space in the electronic component.
- embossed recesses as used in this third exemplary embodiment of the method do not differ in any way from the etched recesses 16 as used in the first method.
- the embossing can be less expensive since these recesses can be made by an embossing roller, whereas a photoresist layer which has to be structured accordingly is usually to be provided during the etching.
- the number of additional surface contacts is four on each side and corresponds to eight hidden contact surfaces of a semiconductor chip, as was already the case in the first two Exemplary embodiments are shown.
- the ninth central contact in this top view is short-circuited with one of the contacts arranged on the edge via a rewiring line and therefore does not require an additional through contact on the edge of the electronic component.
- FIG. 24 shows a schematic cross-sectional view of a carrier plate 26 with a structured first photoresist layer 19 for the selective deposition of external surface contacts in the recesses 16 and 23 provided for this purpose.
- the first photoresist layer 19 is applied to the carrier 15 and the areas are developed. in which surface contacts are provided.
- FIG. 25 shows a schematic top view of a carrier plate 26 with a first photoresist layer 19 for the selective deposition of external surface contacts.
- FIG. 25 differs from FIG. 43 only in that the upper side of the carrier 15, as shown in FIG. 24, is now covered with the first photoresist layer 19 and only the cutouts 16 and 23 are left free for separating the outer surface contacts.
- FIG. 26 shows a schematic cross-sectional view of a carrier plate 26 with galvanically deposited outer surface contacts 2 after removal of the first photoresist layer.
- the cutouts, which were still visible in FIGS. 24 and 25, are now completely filled with a chemically or galvanically deposited metal and the top of the carrier 15 is free to receive a further structured photoresist layer.
- FIG. 27 shows a schematic plan view of a carrier plate 26 with outer surface contacts 2 deposited on the carrier plate 26.
- the material of the surface contacts 2 both in the recesses for outer surface contacts 2 and in the recesses for surface contacts 2 with subsequent through contacts is completely identical due to the common deposition process .
- different material for the cutouts 23 and the cutouts 16 can be deposited by splitting with further photoresist layers.
- this is not provided in this exemplary embodiment of the invention, especially since each additional photoresist step or photolithography step increases the process costs.
- FIG. 28 shows a schematic cross-sectional view of a carrier plate 26 with a structured second photoresist layer 20 for the selective deposition of a rewiring structure.
- the materials of the rewiring structure and the outer surface contacts 2 can be selected differently, since two separate photoresist steps, each with a photoresist mask, are provided for the deposition of the outer surface contacts 2 and for the deposition of the rewiring structure.
- the thickness of the outer surface contacts 2 can differ significantly from the thickness of the rewiring structure 3, since in this third implementation example, similarly to the second implementation example, two photoresist steps 19 and 20 are provided for structuring the rewiring structure 3 and outer surface contacts 2.
- FIG. 29 shows a schematic top view of a carrier plate with a second structured photoresist layer 20 for selective deposition of the rewiring structure 3.
- This rewiring structure 3 is provided not only in the areas of the rewiring lines 27, but also on the surface contacts 2 that have already been deposited. For each of the surface contacts 2, a surface contact with smaller dimensions is provided on the edge, which contacts with through contacts in further course of the process is connected.
- FIG. 30 shows a schematic cross-sectional view of a carrier plate 26 with an electrodeposited rewiring structure 3 and the previously deposited outer surface contacts 2 after removal of the second structured photoresist layer 20, which was shown in FIGS. 28 and 29.
- the rewiring structure 3 is exposed on the carrier plate 26 and is accessible for further process steps.
- FIG. 31 shows a schematic plan view of a carrier plate 26 with a rewiring structure 3 deposited on the carrier plate 26 after the photoresist layer has been removed.
- This rewiring structure 3 is already somewhat more complicated than the first two exemplary embodiments of the method, since not only macroscopic external contact surfaces 33 of the rewiring structure 3 cover the outer surface contacts 2, but also rewiring lines 27 lead to the microscopic contact connection surfaces 7 and to the smaller surface contacts 23 of the through contacts to be deposited.
- FIG. 32 shows a schematic cross-sectional view of a carrier plate 26 with a structured further photoresist layer 24 for the selective deposition of through contacts.
- the thickness D of the photoresist layer 24 corresponds to the future thickness of the plastic housing compound and has openings 25, which are aligned with the additional outer surface contacts 2 for the future through contacts.
- a photoresist thickness D of up to 1 mm can be achieved and at the same time openings 25 with relatively vertical walls can be realized, in particular by the so-called projection exposure of a correspondingly thick photoresist.
- only a thickness of up to 400 micrometers is provided for the components according to the invention, so that the representation of openings 25 with relatively vertical walls is unproblematic.
- an additional structure of through contacts is achieved on the existing rewiring structure 3 by deposition on the previous structure or by filling the openings 25 with the appropriate metal material.
- FIG. 33 shows a schematic plan view of a carrier plate with a further structured photoresist layer 24 for the selective deposition of through contacts.
- This top view is only schematic insofar as the course of the rewiring lines and the surface contacts for the connection to the contact surfaces of a semiconductor chip can also be seen, but are covered by the further structured photoresist layer with openings 25 for through contacts.
- FIG. 34 shows a schematic cross-sectional view of a carrier plate 26 with galvanically deposited through contacts 11 after removal of the further photoresist layer 24, which is shown in FIG
- FIG. 34 provides a metallic frame for a future electronic component, since all electrically conductive components, whether Through contacts 11, outer surface contacts 2 and rewiring lines 27, contact connection surfaces 7 and external contact surfaces 33 are now implemented and are held together and supported by the carrier 15.
- FIG. 35 shows a schematic plan view of a carrier plate 26 with through contacts deposited on the carrier plate 26 and the rewiring structure 3 and the position of contact connection areas 7 and outer area contacts 2 after removal of the further photoresist layer 24, which was shown in FIGS. 52 and 53. As can be seen from FIG. 35, a sufficient area remains between the vias in the center to place a semiconductor chip.
- the semiconductor chip 4 is then applied using flip-chip technology, as has already been shown in the preceding exemplary embodiments of the method.
- the height of the through contacts 11 is greater than the height of the semiconductor chip 4, so that when a plastic housing compound is subsequently applied, the semiconductor chip 4 with the rewiring structure 3 can be completely embedded in the plastic housing compound.
- FIG. 36 shows a schematic cross-sectional view of a carrier plate 26 provided with a plastic housing compound 6, the semiconductor chip 4 and the rewiring structure 3 and the through contacts 11 and the through contacts 11 being completely embedded in a plastic housing compound 6 by the application of the plastic housing compound 6, but the through contacts 11 lie on the top side of the electronic one Component free, since the height or thickness of the through contacts 11 corresponds to the thickness D of the plastic housing compound 6.
- the undersides of the rewiring structure and the undersides of the outer surface remain contacts free of plastic housing compound 6, since they are protected by the carrier plate 26.
- the carrier plate 26 can also serve as a molding tool in the injection molding of the plastic housing compound 6.
- the metallic carrier plate 26 short-circuits the outer surface contacts 2 and the rewiring structure 3, so that the electronic component can neither be tested nor is it functional.
- FIG. 37 shows a schematic top view of a carrier plate provided with a plastic housing compound.
- the through contacts 11 lie freely on the upper side 13 of the electronic component 1 and can thus be contacted by a higher-level circuit board or by an identical electronic component.
- the outer surface contacts 2 are freely accessible and the through contacts can be electrically connected both on the underside and on the 0-top side, but the rewiring structure is freely accessible from its underside, which increases the risk of Damage to the relatively sensitive rewiring lines means.
- the metallic carrier plate is removed by means of etching technology, the material difference between the carrier material a that is shown in FIG. 36 and the material b of the outer surface contacts 2 and the rewiring structure 3 ensuring an etching stop.
- FIG. 38 shows a schematic cross-sectional view of an electronic component 1 after application of a solder resist layer 18.
- This solder stop layer 18 is applied to the entire underside 12 of the electronic component 1. It is particularly important that the solder stop layer in particular covers the rewiring structure 3 except for the outer surface contacts 2.
- the outer surface contacts 2 thus remain freely accessible both for the through contacts 11 and for the outer surface contacts which are connected to the contact surfaces 5 of the semiconductor chip 4 via the rewiring structure 3.
- FIG. 39 shows a schematic bottom view of an electronic component 1 after application of a solder stop layer 18.
- This solder stop layer 18 can be arranged in such a way that it leaves a small edge around each outer surface contact 2, so that the plastic housing compound 6 is visible at these points ,
- An electronic component 1, which was produced using the third exemplary embodiment of the method, has the advantage that electronic contacts 1 of the same type can now be stacked vertically in any number via through contacts 11, in order to produce highly complex and extremely dense electronic components 14 such as those Figures 4 to 7 show.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10224124 | 2002-05-29 | ||
DE10224124A DE10224124A1 (en) | 2002-05-29 | 2002-05-29 | Electronic component with external surface contacts and process for its production |
PCT/DE2003/001663 WO2003103042A2 (en) | 2002-05-29 | 2003-05-23 | Electronic component comprising external surface contacts and a method for producing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1508166A2 true EP1508166A2 (en) | 2005-02-23 |
Family
ID=29557416
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03755901A Withdrawn EP1508166A2 (en) | 2002-05-29 | 2003-05-23 | Electronic component comprising external surface contacts and a method for producing the same |
Country Status (4)
Country | Link |
---|---|
US (1) | US20060091561A1 (en) |
EP (1) | EP1508166A2 (en) |
DE (1) | DE10224124A1 (en) |
WO (1) | WO2003103042A2 (en) |
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US9691635B1 (en) | 2002-05-01 | 2017-06-27 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
US7633765B1 (en) | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
DE10320646A1 (en) | 2003-05-07 | 2004-09-16 | Infineon Technologies Ag | Electronic component, typically integrated circuit, system support and manufacturing method, with support containing component positions in lines and columns, starting with coating auxiliary support with photosensitive layer |
US7425759B1 (en) * | 2003-11-20 | 2008-09-16 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal and filler |
US10811277B2 (en) | 2004-03-23 | 2020-10-20 | Amkor Technology, Inc. | Encapsulated semiconductor package |
US11081370B2 (en) | 2004-03-23 | 2021-08-03 | Amkor Technology Singapore Holding Pte. Ltd. | Methods of manufacturing an encapsulated semiconductor device |
DE102004022884B4 (en) * | 2004-05-06 | 2007-07-19 | Infineon Technologies Ag | Semiconductor device with a rewiring substrate and method of making the same |
US7768113B2 (en) * | 2005-05-26 | 2010-08-03 | Volkan Ozguz | Stackable tier structure comprising prefabricated high density feedthrough |
US7919844B2 (en) * | 2005-05-26 | 2011-04-05 | Aprolase Development Co., Llc | Tier structure with tier frame having a feedthrough structure |
DE102006006825A1 (en) * | 2006-02-14 | 2007-08-23 | Infineon Technologies Ag | Semiconductor component e.g. ball grid array semiconductor component, has semiconductor chip with protective casing, and soldering ball arranged in recess of electrical insulating layer and connected with connecting carrier |
DE102006032073B4 (en) * | 2006-07-11 | 2016-07-07 | Intel Deutschland Gmbh | Electrically conductive composite of a component and a carrier plate |
US7550857B1 (en) | 2006-11-16 | 2009-06-23 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
US7868465B2 (en) * | 2007-06-04 | 2011-01-11 | Infineon Technologies Ag | Semiconductor device with a metallic carrier and two semiconductor chips applied to the carrier |
US7955953B2 (en) * | 2007-12-17 | 2011-06-07 | Freescale Semiconductor, Inc. | Method of forming stacked die package |
JP5563814B2 (en) | 2009-12-18 | 2014-07-30 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
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KR101340348B1 (en) | 2011-11-30 | 2013-12-11 | 주식회사 심텍 | Embedded chip package board using mask pattern and method for manufacturing the same |
KR101488590B1 (en) | 2013-03-29 | 2015-01-30 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
JP2016535462A (en) * | 2014-09-26 | 2016-11-10 | インテル コーポレイション | Integrated circuit package having wire bonded multi-die stack |
EP3557608A1 (en) * | 2018-04-19 | 2019-10-23 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit |
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- 2003-05-23 WO PCT/DE2003/001663 patent/WO2003103042A2/en not_active Application Discontinuation
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Also Published As
Publication number | Publication date |
---|---|
US20060091561A1 (en) | 2006-05-04 |
WO2003103042A3 (en) | 2004-04-08 |
DE10224124A1 (en) | 2003-12-18 |
WO2003103042A2 (en) | 2003-12-11 |
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