EP1496424A2 - Steuereinrichtung für Informationsverarbeitungsgerät - Google Patents

Steuereinrichtung für Informationsverarbeitungsgerät Download PDF

Info

Publication number
EP1496424A2
EP1496424A2 EP04253699A EP04253699A EP1496424A2 EP 1496424 A2 EP1496424 A2 EP 1496424A2 EP 04253699 A EP04253699 A EP 04253699A EP 04253699 A EP04253699 A EP 04253699A EP 1496424 A2 EP1496424 A2 EP 1496424A2
Authority
EP
European Patent Office
Prior art keywords
voltage
frequency
profile
resources
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP04253699A
Other languages
English (en)
French (fr)
Other versions
EP1496424A3 (de
Inventor
Anthony C. Toshiba Research Europe Ltd. Dolwin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP1496424A2 publication Critical patent/EP1496424A2/de
Publication of EP1496424A3 publication Critical patent/EP1496424A3/de
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to processing apparatus utilising dynamic scaling of voltage (DVS), and in particular although not exclusively to a controller for such apparatus.
  • the invention is especially applicable to software defined radio (SDR), but is not so limited and may be applied to other re-configurable electronic systems.
  • Basic dynamic scaling voltage DVS processing modules exist in the prior art, for example the Intel TM Speedstep TM technology applied to many laptop computers in which the processor is allowed to enter a "sleep" mode when not in use in order to reduce power consumption from the battery.
  • Recently processing modules have emerged which are able to operate at a number of different voltage and frequency or clock speed rates. Power consumption in a processor is a function of both voltage and clock speed or frequency, and as is known a quadratic reduction in power consumption can theoretically be achieved by reducing both these parameters.
  • Transmeta TM provides Longrun TM power management technology which adjusts the voltage and clock speed of a processor in order to ensure the processor minimises the amount of time spent in idle, in which the processor is "on" but not used for processing.
  • a problem with such approaches is that they are not well suited to tasks with hard deadlines, for example ensuring that a data block received by a wireless terminal is decoded by a Viterbi decoder algorithm within a set number of milliseconds.
  • Processing execution time deadlines for certain operations in such systems are often defined by standard protocols in order that, for example the terminal can inter-operate with a base station in a wireless cellular or local area network.
  • the present invention provides a controller for a processing apparatus having multiple processing resources at least some of which have controllable voltage and/or frequency operational parameters.
  • the controller comprises or accesses an operations data-structure comprising a number of execution parameters for each operation the apparatus is to perform.
  • execution parameters for each operation may comprise a voltage-frequency profile, a start time, worst case cycle count, and actual execution cycle count statistics for previous executions of the operation. These statistics are preferably updated over time as the operation is performed numerous times in order to provide a historical statistical basis for parameters such as average execution cycle count.
  • a voltage-frequency profile calculating means provides or periodically updates the stored voltage-frequency profile for each operation based on these parameters.
  • the voltage-frequency profile is arranged to minimise power consumption for each operation, for example by having the processing resource performing the operation initially at a low voltage-frequency, then only if the operation execution time overruns a predetermined limit (for example the average execution time) increase the voltage-frequency used by the processing resource in order to complete the operation within the hard execution time deadline.
  • the voltage-frequency of the processing resource performing the operation can be initially kept lower than normal in the expectation that even at this level the operation is likely to be completed before the operation deadline. Then if the operation is still being performed past a predetermined time, perhaps close to the deadline, then the voltage-frequency can be increased significantly in order to quickly finish the operation in order to meet the deadline. In the worst case cycle count, the power consumed will be the same as it would have been had the operation been performed at a constant higher (albeit for a shorter time) voltage-frequency level;.
  • the present invention provides a controller according to claim 1.
  • the architecture of a processing apparatus comprises a plurality of processing resources R1 - Rn, a controller 1, a control plane 2, a data plane 3 and a data-bus controller 4.
  • the processing apparatus might be used in a wireless communications terminal for receiving and sending signals to a base station according to one or more protocols such as UMTS and GSM for example.
  • the apparatus is particularly suited to software defined radio (SDR) applications, and for convenience and ease of explanation the embodiment will be described with respect to mobile wireless communications applications, although it is not so limited.
  • SDR software defined radio
  • the processing resources R could be ASIC's for specific wireless communications processing such as a Viterbi decoder for example, they could also be reconfigurable digital signal processing (DSP) blocks with multiple uses, or similarly reconfigurable field programmable gate arrays (FPGA's)
  • DSP digital signal processing
  • FPGA field programmable gate array
  • the data plane 3 is a logical entity comprising a data-bus coupled to a memory resource and input/output interfaces to otherresources, for example analogue-to-digital converters, digital-to-analogue converters, channel decoder, equaliser and vocoder.
  • the memory is used to store sampled signal symbols as well as those symbols and associated data following various stages in the processing chain to obtain decoded traffic data.
  • the data-bus controller 4 controls access between the various resources R and the memory and other data plane components; allowing for example a resource to read appropriate data and then write data back to the memory following processing by the resource.
  • the control plane 2 is another logical entity comprising a control-bus between the resources R and the controller 1. Both the data and control planes could also be implemented as a cross-bar or network for example.
  • the controller 1 controls operation of the data plane 3 via the data-bus controller 4 in order to ensure that the data in the data plane passed to the right resource R for processing and that demands for data transfer by competing entities are handled appropriately.
  • the fabric used to transfer data might also be capable of being switched to run at different v-f depending on the configuration of the system.
  • the data plane would be configured by the controller, via the 'data bus controller/arbiter'. Those skilled in the art will be familiar with the operation of data bus controllers.
  • the controller ensures that data in the data plane is properly processed by the various resources R, in the right order and if possible in parallel by splitting operations into tasks or groups of tasks that can be performed using different resources. Additionally, the controller 1 controls the voltage-frequency (v-f) of each resource R in such a way that the required processing is carried out with a minimum of power consumption. Many of the processing tasks will have predetermined deadlines by which processing must be finished and so the controller 1 is arranged to control the processing in the apparatus according to this constraint whilst at the same time minimising power consumption. This is advantageous in portable terminals having processing tasks with hard deadlines such as wireless communications terminals for example.
  • FIG. 2 shows the controller 1 schematically, and figure 3 shows the control structures embodied by the controller 1 for each resource; including two sets of resources R using different time bases, for example GSM and UMTS.
  • the controller 1 comprises a dispatcher 10 which controls forwarding of control messages to the appropriate resource R.
  • the dispatcher 10 determines what control messages to send to what resource R at what time according to a process timetable 11.
  • the process timetable 11 is a data-structure which comprises a list of control messages each having an associated resource identifier and a start time.
  • the start time is usually relative to a predetermined time reference such as a10ms radio frame in the case of WCDMA.
  • Wireless communications signals are transmitted within frames to which a receiver synchronises itself in order to properly receive and process the signals.
  • a frame sync source 12 derived from an internal clock signal for example is supplied to the dispatcher 10 to ensure that the processing operations are properly synchronised as between each other.
  • Each control message will contain a transmission time, destination, a command, voltage-frequency setting and configuration information.
  • the nature and timing of the control messages in the process timetable 11 is determined by a dynamic scheduler 13.
  • the scheduler 13 writes or updates control messages in a shadow process timetable 14 which is another data-structure having the same structure as the active process timetable 11.
  • the active process timetable 11 is typically loaded with the contents of the shadow process timetable 14 at some convenient time, for example at the end/start of a frame.
  • a shadow timetable is used because changes to the timetable would take a finite amount of time to write into the table and while this is happening the timetable would have incomplete data and so may result in faulty commands being sent to the resources.
  • the controller updates the control messages for various operations as events change. For example an operation may finish early freeing up one of the resources earlier than expected and the controller may therefore re-assign a later scheduled operation to the newly freed up processing resource R.
  • Figure 4 shows a schedule for operations O1 - 010 which are distributed over time and over 5 processing resources R1 - R5. Some of the operations require data from a previous operation and so can't be started until after that operation has been completed, whereas other operations can run in parallel.
  • Schedulers for scheduling operations over a number of processing resources are known in the art. Typically prior art schedulers will schedule operations based on their worst case cycle count, that is the number of processing cycles that the processing resource will have to perform in the worst case situation in order to complete the operation. From this it can be determined what the maximum execution time of an operation is and this is then used to schedule the operation in with the other required operations. However often operations will not require their worst case cycle count and instead will finish early. Dynamic schedulers can dynamically change the schedule to take account of the fact that operations sometimes finish early, and perhaps start a later scheduled operation early. Such dynamic schedulers are also known in the art.
  • the controller 1 also comprises an operations control block data-structure 15 which comprises a control block or record 16 for each operation the processing apparatus is to carry out.
  • the record 16 of each operation comprises a number of parameters associated with the operation including its worst case cycle count, a resource identifier (R1 - Rn), a voltage frequency (v-f) profile, and preferably execution time statistics corresponding to previous executions of the operation in the processing apparatus. These include past execution times, (execution time ⁇ , executing time 1.7), that can be used to implement filtering of the values before statistics are calculated.
  • the controller also comprises a voltage frequency profile calculator 17 which determines the v-f over the worst case execution time of the operation, and is used to control the v-f operating parameters of the resource R performing the operation.
  • a quantiser 18 adjusts the output of the v-f profile calculator 17 to one of the achievable or practical v-f points associated with the resource R. The quantiser and profile calculation can be done in a single block e.g. when only 2 voltage settings are being used. The quantised v-f profile for the processing resource R associated with the operation is then written to that operation's control block or record 16.
  • the v-f profile for each operation will typically start off at a certain level and then, if necessary increase this level as the operation's hard deadline is approached, as shown in Figure 5a. This takes advantage of the fact that on many occasions the operation will not require its worst case cycle count and will therefore finish early. By keeping the v-f low at first, many executions of the operation will be performed using this low v-f only, and therefore on average power consumption associated with this operation will be reduced. In the instances where the operation requires its worst case cycle count, or a cycle count approaching this, then the v-f is increased in order to ensure the operation is finished by its deadline.
  • the v-f profile for each operation is influenced by the historical execution statistics for that operation. For example if the operation has an average execution time or cycle count that has a low standard deviation, in other words there is not much variation, then the initial v-f level can be set low such that the average execution time will be reached at this low v-f near the hard deadline. The v-f level can then be raised significantly in order to ensure the operation finishes before its hard deadline for those executions when the operation requires more than its average number of cycle counts. For operations having a high standard deviation, that is there is a lot of variation in the execution times, then the v-f level will initially be higher in order to ensure that the operation finishes before its hard deadline for all execution situations.
  • Figure 5b shows the cycle period vs.
  • cycle number for three standard deviation values, for an average execution cycle count of 500 and a standard deviation that varies between 30 and 10000.
  • cycle count for three standard deviation values, for an average execution cycle count of 500 and a standard deviation that varies between 30 and 10000.
  • the calculation is based on cycle count but a conversion can be made from execution time to cycle count and similarly a conversion could also be made with higher level metrics such as average and deviation of the number of iterations of a turbo decoder which could be mapped to the equivalent cycle count statistics.
  • the dynamic scheduler 13 can be arranged to retrieve the v-f profiles from the appropriate operation's control block 16 for each operation or task it writes to the process timetables 11 and 14 as indicated in Figure 2.
  • the dynamic scheduler 13 may retrieve parameters such as the operation's worst count, average count, deadline and from these derive a voltage frequency profile as indicated in Figure 3.
  • Each of the resources R has its own supply voltage and clock frequency, and the controller sets the voltage-frequency for each module. Because each module R can operate off a separate clock the interface to the data plane will be asynchronous, and in addition it must also buffer the different operating voltages.
  • the resources R are usually specialized data processing blocks with limited control code, that is they receive data, process it and then pass it on.
  • the controller 1 determines how and when each resource operates. All data transfer between resources goes via the data plane. All control messages and measurement reports go via the control plane.
  • the data plane is also regarded as a resource and so its characteristics can also be controlled via the data bus controller. For example its v-f may be adjusted when interacting with a particular resource R.
  • Each resource executes an operation when instructed to do so by the controller 1.
  • the dispatcher reads the Process Timetable and sends messages to each resource just before the resource is expected to process data.
  • the message will contain configuration information and a command word. In this way the resources can be statically scheduled to implement the required functionality.
  • One of the commands that can be sent to a resource is a voltage-frequency command.
  • This command will set the supply voltage to the resource and also the operating frequency.
  • the resource comprises a counter to count the actual number of cycles.
  • the resource may contain a timer, operating off a standard clock. This is used to time how long the operation takes to complete i.e. the actual execution time.
  • On completion the resource will send, in a message, the execution time and operation handle to the controller.
  • the cycle operation time will vary due to the voltage-frequency ramping itself but also because the operation may take a different number of cycles to complete.
  • the reasons for changes in cycle count include: the processing required is dependant on the data for example a voice decoder; the resource shares a data bus with another resource so may be blocked while the second resource uses the bus; the system may dynamically modify the processing implemented by the resource as a result of a change in an external condition for example, the number of iterations of Turbo decoder may change as a result of a change in the channel conditions.
  • the controller 1 calculates the actual cycle count from the actual execution time using its knowledge of what the voltage-frequency ramp was. An alternative to measuring the execution time is to use a counter in the resource to count the number of cycles directly.
  • the controller 1 stores execution times/cycle counts sent by each resource, at the end of each operation, in the respective operation control block data record 16.
  • the operation control block 15 is initialized with the worst-case cycle count and start time relative to frame period i.e. earliest time operation can start because of availability of data from other operations; and its relative timing deadline when an operation is created. If the statistics of this operation are known at design time the average cycle count and standard deviation may also be set at initialisation. In this case a flag is set to indicate that the actual execution times are not required and in addition the voltage-frequency profile needs only be calculated when the relative timing deadline changes.
  • the controller 1 includes a statistics calculator 19 to update statistics such as the average cycle count and standard deviation for each operations control block record 16.
  • the dynamic scheduler 13 receives a definition of the data flow between operations which includes a set of required operations and their timing constraints from a Configuration Management Module. For example in a SDR terminal, this may correspond to receiving cellular calls in GSM.
  • the operations required to achieve the reception and transmission of the GSM signals are then downloaded to the scheduler 13.
  • the scheduler 13 determines an initial schedule by splitting the operations up and allocating them to different processing resources R at appropriate times as illustrated in Figure4.
  • the scheduler 13 then reads the v-f profile data for each operation from the appropriate operation control blocks 16, and writes appropriate control messages to the shadow process timetable 14. At an appropriate point (in absolute time) these are loaded into the active process timetable 11 and forwarded by the dispatcher 10 to the appropriate resource R.
  • a completion message is sent to the controller 1 and includes the execution time and/or execution cycle count for the operation. This information is forwarded to the appropriate control block 16 where it is added to the statistical information stored on the operation.
  • the scheduler 13 also monitors the operation end times and may dynamically reschedule later operations if the completed operation finished early.
  • the v-f profile for each operation is calculated from the statistical execution time data stored in the operation blocks 16, and is quantised to practical v-f points for the resource R and then stored in the operations block 16 for that operation (or delivered directly to the dynamic scheduler).
  • the v-f profile is updated periodically as the statistical data mounts.
  • the process timetable is preferably updated as follows:
  • some resources may be able to self modify their voltage-frequency setting internally. So in such a scenario the configuration message sent to a resource will contain a set of voltage-frequency values and their associated relative timings. So when these values are changed only the configuration command needs to be modified.
  • a further enhancement to this scheme uses more than one process timetable 11 (and associated shadow 14), as is illustrated in Figure 3(system 1 and 2).
  • Each timetable runs from a different timebase and frame sync. This can be used when two systems such as GSM and UMTS are being implemented on the same platform. In such a system the two frame sync time periods are different and operate out of phase with each other, and without multiple timetables the common denominator would be very high and hence the timetable would be very long.
  • This can be further extended to each operation on a resource or each resource with multiple operations has its own timetable, v-f profile, calculator, etc. This simplifies access to the timetable.
  • the overlapping of resources e.g. data bus
  • GSM and UMTS is possible but scheduling becomes difficult because of the different timebases i.e. the scheduling would have to run across a common multiple making it very big.
  • only one of voltage or frequency may be adjusted such that a separate voltage profile or frequency profile is calculated for the operations to be performed.
  • the frequency might be set so the operation completes at a specific time and this might simplify the scheduler and reduce resource requirements e.g. output data will only be written into global memory at the end of an operation and then be immediately read by another operation hence freeing up RAM.
  • processor control code for example on a carrier medium such as a disk, CD- or DVD-ROM, programmed memory such as read only memory (Firmware), or on a data carrier such as an optical or electrical signal carrier.
  • a carrier medium such as a disk, CD- or DVD-ROM
  • programmed memory such as read only memory (Firmware)
  • a data carrier such as an optical or electrical signal carrier.
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • the code may comprise conventional programme code or microcode or, for example code for setting up or controlling an ASIC or FPGA.
  • the code may also comprise code for dynamically configuring re-configurable apparatus such as reprogrammable logic gate arrays.
  • the code may comprise code for a hardware description language such as Verilog TM or VHDL (Very high speed integrated circuit Hardware Description Language).
  • Verilog TM or VHDL Very high speed integrated circuit Hardware Description Language
  • the code may be distributed between a plurality of coupled components in communication with one another.
  • the embodiments may also be implemented using code running on a field-(re)programmable analog array or similar device in order to configure analog hardware.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Power Sources (AREA)
  • Communication Control (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Circuits Of Receivers In General (AREA)
EP04253699A 2003-07-08 2004-06-21 Steuereinrichtung für Informationsverarbeitungsgerät Ceased EP1496424A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0315956 2003-07-08
GB0315956A GB2403823B (en) 2003-07-08 2003-07-08 Controller for processing apparatus

Publications (2)

Publication Number Publication Date
EP1496424A2 true EP1496424A2 (de) 2005-01-12
EP1496424A3 EP1496424A3 (de) 2006-11-29

Family

ID=27741788

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04253699A Ceased EP1496424A3 (de) 2003-07-08 2004-06-21 Steuereinrichtung für Informationsverarbeitungsgerät

Country Status (4)

Country Link
US (1) US7328073B2 (de)
EP (1) EP1496424A3 (de)
JP (1) JP4157502B2 (de)
GB (1) GB2403823B (de)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1557743A3 (de) * 2004-01-26 2006-11-29 Kabushiki Kaisha Toshiba Dynamische Spannungssteuerung
WO2007077516A1 (en) * 2006-01-06 2007-07-12 Koninklijke Philips Electronics, N.V. Power aware dynamic scheduling in multiprocessor system employing voltage islands
WO2009107094A3 (en) * 2008-02-26 2009-10-22 Nxp B.V. Systems and methods for task scheduling in multi-mode software defined radio devices
US8689037B2 (en) 2009-12-16 2014-04-01 Qualcomm Incorporated System and method for asynchronously and independently controlling core clocks in a multicore central processing unit
WO2014070338A1 (en) * 2012-11-05 2014-05-08 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
US8775830B2 (en) 2009-12-16 2014-07-08 Qualcomm Incorporated System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature
US8909962B2 (en) 2009-12-16 2014-12-09 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
FR3014215A1 (fr) * 2013-12-03 2015-06-05 Thales Sa Procede de gestion des ressources de calcul d'applications logicielles
US9104411B2 (en) 2009-12-16 2015-08-11 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
US9128705B2 (en) 2009-12-16 2015-09-08 Qualcomm Incorporated System and method for controlling central processing unit power with reduced frequency oscillations
US9176572B2 (en) 2009-12-16 2015-11-03 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
CN105930289A (zh) * 2010-07-30 2016-09-07 富士通株式会社 多核处理器系统、分配程序、控制程序、分配方法以及控制方法
US9563250B2 (en) 2009-12-16 2017-02-07 Qualcomm Incorporated System and method for controlling central processing unit power based on inferred workload parallelism
CN106569884A (zh) * 2015-10-12 2017-04-19 沈阳高精数控智能技术股份有限公司 一种基于动态电压调节技术的可靠性低功耗调度方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7885409B2 (en) 2002-08-28 2011-02-08 Rockwell Collins, Inc. Software radio system and method
KR100722314B1 (ko) 2005-03-24 2007-05-28 중앙대학교 산학협력단 Ｄｖｓ를 이용한 멀티미디어 신호처리 장치
KR100806284B1 (ko) * 2005-12-08 2008-02-22 한국전자통신연구원 동적 전압 스케일링을 적용한 고효율 프로세서
US7720506B1 (en) 2006-07-28 2010-05-18 Rockwell Collins, Inc. System and method of providing antenna specific front ends for aviation software defined radios
US7831255B1 (en) 2006-07-31 2010-11-09 Rockwell Collins, Inc. System and method of providing automated availability and integrity verification for aviation software defined radios
GB2444518A (en) 2006-12-07 2008-06-11 Symbian Software Ltd Process priority profiles in a computer system
TWI326818B (en) * 2006-12-15 2010-07-01 Inst Information Industry Dynamic voltage scheduling method, system thereof and record medium
KR100852188B1 (ko) 2007-02-27 2008-08-13 삼성전자주식회사 동적 전압 스케일링 시스템 및 방법
US7941681B2 (en) * 2007-08-17 2011-05-10 International Business Machines Corporation Proactive power management in a parallel computer
US20100058086A1 (en) * 2008-08-28 2010-03-04 Industry Academic Cooperation Foundation, Hallym University Energy-efficient multi-core processor
JP2011070565A (ja) * 2009-09-28 2011-04-07 Nec Personal Products Co Ltd クライアント端末及びシンクライアントシステム
KR101124332B1 (ko) * 2010-07-02 2012-03-19 주식회사 하이닉스반도체 비휘발성 메모리 장치 및 그 설정정보 처리방법
JP5572527B2 (ja) * 2010-11-09 2014-08-13 パナソニック株式会社 通信処理装置及び通信処理方法
US8074093B1 (en) * 2011-06-03 2011-12-06 Johnson Daniel L Method and system for optimizing the completion of computing operations
US10114448B2 (en) 2014-07-02 2018-10-30 Intel Corporation Autonomous C-state algorithm and computational engine alignment for improved processor power efficiency
GB2572684B (en) * 2015-12-18 2020-04-08 Imagination Tech Ltd Controlling operation of a GPU
GB2545507B (en) 2015-12-18 2019-07-17 Imagination Tech Ltd Controlling scheduling of a GPU
GB2545508B (en) 2015-12-18 2019-04-10 Imagination Tech Ltd Controlling operation of a GPU
CN109191344B (zh) * 2018-09-10 2024-01-12 深圳市天英联合科技股份有限公司 课程资源的组织方法、装置、设备和存储介质
CN118614140A (zh) * 2023-01-06 2024-09-06 哲库科技(上海)有限公司 用于动态调整数据面层2时钟频率或电压的装置及方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5222239A (en) * 1989-07-28 1993-06-22 Prof. Michael H. Davis Process and apparatus for reducing power usage microprocessor devices operating from stored energy sources
US5640563A (en) * 1992-01-31 1997-06-17 International Business Machines Corporation Multi-media computer operating system and method
US5812860A (en) * 1996-02-12 1998-09-22 Intel Corporation Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control power consumption
US6378081B1 (en) * 1998-10-01 2002-04-23 Gateway, Inc. Power conservation without performance reduction in a power-managed system
US6298448B1 (en) * 1998-12-21 2001-10-02 Siemens Information And Communication Networks, Inc. Apparatus and method for automatic CPU speed control based on application-specific criteria
US6823516B1 (en) * 1999-08-10 2004-11-23 Intel Corporation System and method for dynamically adjusting to CPU performance changes
US7100061B2 (en) * 2000-01-18 2006-08-29 Transmeta Corporation Adaptive power control
JP2002099432A (ja) * 2000-09-22 2002-04-05 Sony Corp 演算処理システム及び演算処理制御方法、タスク管理システム及びタスク管理方法、並びに記憶媒体
US20030061260A1 (en) * 2001-09-25 2003-03-27 Timesys Corporation Resource reservation and priority management

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1557743A3 (de) * 2004-01-26 2006-11-29 Kabushiki Kaisha Toshiba Dynamische Spannungssteuerung
US7418358B2 (en) 2004-01-26 2008-08-26 Kabushiki Kaisha Toshiba Dynamic voltage controller
WO2007077516A1 (en) * 2006-01-06 2007-07-12 Koninklijke Philips Electronics, N.V. Power aware dynamic scheduling in multiprocessor system employing voltage islands
WO2009107094A3 (en) * 2008-02-26 2009-10-22 Nxp B.V. Systems and methods for task scheduling in multi-mode software defined radio devices
US8630170B2 (en) 2008-02-26 2014-01-14 Nxp, B.V. Systems and methods for task scheduling in multi-mode software defined radio devices
US8689037B2 (en) 2009-12-16 2014-04-01 Qualcomm Incorporated System and method for asynchronously and independently controlling core clocks in a multicore central processing unit
US9563250B2 (en) 2009-12-16 2017-02-07 Qualcomm Incorporated System and method for controlling central processing unit power based on inferred workload parallelism
US8775830B2 (en) 2009-12-16 2014-07-08 Qualcomm Incorporated System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature
US8909962B2 (en) 2009-12-16 2014-12-09 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
US9128705B2 (en) 2009-12-16 2015-09-08 Qualcomm Incorporated System and method for controlling central processing unit power with reduced frequency oscillations
US9176572B2 (en) 2009-12-16 2015-11-03 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
US9081558B2 (en) 2009-12-16 2015-07-14 Qualcomm Incorporated System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on tempature
US9104411B2 (en) 2009-12-16 2015-08-11 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
CN105930289A (zh) * 2010-07-30 2016-09-07 富士通株式会社 多核处理器系统、分配程序、控制程序、分配方法以及控制方法
WO2014070338A1 (en) * 2012-11-05 2014-05-08 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
EP2881839A1 (de) * 2013-12-03 2015-06-10 Thales Verfahren zur Rechnerressourcenverwaltung für Softwareanwendungen
FR3014215A1 (fr) * 2013-12-03 2015-06-05 Thales Sa Procede de gestion des ressources de calcul d'applications logicielles
US9740259B2 (en) 2013-12-03 2017-08-22 Thales Method for managing software application computing resources
CN106569884A (zh) * 2015-10-12 2017-04-19 沈阳高精数控智能技术股份有限公司 一种基于动态电压调节技术的可靠性低功耗调度方法
CN106569884B (zh) * 2015-10-12 2020-03-10 沈阳高精数控智能技术股份有限公司 一种基于动态电压调节技术的可靠性低功耗调度方法

Also Published As

Publication number Publication date
GB2403823B (en) 2005-09-21
GB0315956D0 (en) 2003-08-13
JP2005073231A (ja) 2005-03-17
GB2403823A (en) 2005-01-12
EP1496424A3 (de) 2006-11-29
US20050024927A1 (en) 2005-02-03
US7328073B2 (en) 2008-02-05
JP4157502B2 (ja) 2008-10-01

Similar Documents

Publication Publication Date Title
US7328073B2 (en) Controller for processing apparatus
US7418358B2 (en) Dynamic voltage controller
US6965763B2 (en) Event coordination in an electronic device to reduce current drain
EP0865167B1 (de) Verfahren zur Energieeinsparung in einem digitalen schnurlosen Kommunikationsgerät
US9329671B2 (en) Power-efficient inter processor communication scheduling
Luo et al. Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems
KR101054119B1 (ko) 무선 송수신기에서 슬립 모드들의 제어
EP1499955B1 (de) Verfahren und vorrichtung zur zeitsteuerungs- und ereignisverarbeitung in drahtlosen systemen
EP1553502A2 (de) Rekonfigurierbares Signalverarbeitungsmodul
US10564708B2 (en) Opportunistic waking of an application processor
CN108605289B (zh) 低功率蜂窝调制解调器系统架构
JP2008515355A (ja) 無線機分離のためにデジタルシグナルプロセッサを制御するための装置、および関連する方法
WO2008040847A1 (en) Control of schedulation
US20220011844A1 (en) Methods and apparatus for adaptive power profiling in a baseband processing system
WO2008146099A1 (en) Data processing system, method for processing data and computer program product
Grosse et al. Methods for power optimization in SOC-based data flow systems
US8966300B2 (en) DFVS-enabled multiprocessor
CN108227893B (zh) 串口控制器、微控制系统及微控制系统中的唤醒方法
WO2004006089A1 (en) A processor system and method for controlling signal timing therein
Gorjiara et al. An Algorithm to Avoid Power Command Jitter in Middleware-Based Distributed Embedded Systems
GB2381609A (en) Controlling signal timing in processor systems to reduce power consumption
Dargie Dynamic Power Management in Embedded Systems

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20040630

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK

AKX Designation fees paid

Designated state(s): DE FR

17Q First examination report despatched

Effective date: 20071122

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 20180316