GB2381609A

GB2381609A - Controlling signal timing in processor systems to reduce power consumption

Info

Publication number: GB2381609A
Application number: GB0214375A
Authority: GB
Inventors: Olivier Patrick Boireau; Matthew John George Westcott
Original assignee: Sendo International Ltd
Current assignee: Sendo International Ltd
Priority date: 2002-05-28
Filing date: 2002-06-20
Publication date: 2003-05-07
Anticipated expiration: 2022-06-20
Also published as: GB2381609B; GB0212261D0; GB0214375D0

Abstract

A method for controlling a timing of signals in a processor-based system includes the steps of scheduling of one or more tasks for a processor to perform; and determining whether the scheduled one or more tasks were performed by the processor at a scheduled time. A signal timing of the processor-based system is adjusted in response to the step of determining. A load monitor and battery powered device are also described. In this manner, a signal timing, for example clock rates, used in the processor-based system are adjusted based on the processor load, to maximise processor performance for a minimum power consumption.

Description

PROCESSOR LOAD MONITORING SYSTEM Field of the Invention The present invention relates to a processor load monitoring method, and in particular to a method of monitoring the load of a processor and of adjusting a clock signal provided to the processor, and possibly peripheral components of the processor, in accordance with the load of the processor.

Background of the Invention For battery powered devices, it is important that the power consumption of the device be kept to a minimum, in order for the battery to be able to provide power for as long as possible without requiring recharging or replacement of the battery. This is particularly important for devices such as mobile communications devices (e. g. mobile cellular telephones), portable computers, personal digital assistants (PDAs), etc, where a user of such a device requires use of the device for prolonged periods of time when it is not possible to recharge the battery. Furthermore, these devices comprise components such as displays, radio (RF) transceivers and the like, which have a relatively high power consumption.

There is therefore a continual need for ways of reducing the overall power consumption of a device.

An area in which the power consumption of a device can be reduced is that of the processor system, which if run inefficiently can consume a relatively large amount of power, but which if run efficiently can consume a significantly less amount of power.

The clock rate of a component, whether the component is a processor or a peripheral component within the processor system, affects the power consumption of that component.

When such components operate at high clock rates, their power consumption is increased relative to when operating at lower clock rates. Therefore, by reducing the clock rate of a component, the power consumption of that component can be reduced. However, by reducing the clock rate of the component, the performance of the component, i. e. the speed at which it is able to perform its tasks, is reduced, which can be undesirable.

A known method of achieving a balance of reducing the power consumption of a component whilst maintaining a sufficient level of performance is to put that component into a sleep mode, by stopping the clock or reducing the clock rate of the component, when it is not required to perform a specific task. The component is then brought out of sleep mode, or'woken up', when it is required to perform a task, by restarting the clock or increasing the clock rate to the usual rate for the component.

A problem with this method is that for some components, in particular the processor, it is not always necessary for them to work at their maximum speed in order to

perform a specific task. Therefore, by providing the component with its maximum clock rate, the power consumption of the device is higher than is necessary.

As previously mentioned, there is a continual need for ways of reducing the overall power consumption of a device. In light of the identified shortcomings of the above-mentioned method, there is a need for providing components with more suitable clock rates, allowing them to perform their required tasks whilst being more efficient in their power consumption.

Statement of Invention According to a first aspect of the present invention, there is provided a method for controlling a signal timing in a processor-based system, as claimed in Claim 1.

According to a second aspect of the present invention, there is provided a processor, as claimed in Claim 9.

According to a third aspect of the present invention, there is provided a processor-based system, as claimed in Claim 10.

According to a fourth aspect of the present invention, there is provided a portable device, as claimed in Claim

11.

According to a fifth aspect of the present invention, there is provided a processor-based system, as claimed in Claim 12.

According to a sixth aspect of the present invention, there is provided a battery-powered device, as claimed in Claim 17.

Further aspects of the present invention are claimed in the dependent Claims.

For the present invention, the load of the processor is determined by whether or not a task scheduled by the load monitor is performed at the time scheduled, or whether it was performed after the scheduled time.

If the task was performed at substantially the time for which it was scheduled, since the processor was able to perform the task at substantially the specified time for which it was scheduled, the processor did not have other tasks of higher priority waiting to be performed at that time. Therefore, it is likely that the capacity of the processor is not being fully used, and so the clock rate can be reduced without impacting significantly on the ability of the processor to perform its required tasks.

However, if the task were not performed at the time for which it was scheduled, this would be due to the processor being busy performing other tasks of higher priority. Therefore it is likely that the present

capacity of the processor is not sufficient for it to perform its tasks at their scheduled times, and so the clock rate should be increased in order to increase the performance of the processor.

The increasing/decreasing of the clock rate provided to the processor, depending on the load of the processor, provides the advantage over the prior art of providing the processor with a clock rate more suitable to its work load, allowing the processor to perform its required tasks whilst being more efficient in its power consumption.

Brief Description of the Drawings Exemplary embodiments of the present invention will now be described, with reference to the accompanying drawings, in which: FIG. 1 illustrates a part of a processor system with which the present invention may be implemented; FIG. 2 illustrates a mechanism for adjusting a clock rate of a processor in accordance with the preferred embodiment of the present invention; FIG. 3 illustrates a mechanism for adjusting a clock rate of a processor in accordance with an alternative embodiment of the present invention;

FIG. 4 illustrates a mechanism for adjusting a driving voltage of a processor system; FIG. 5 illustrates a mechanism for adjusting a driving voltage of a processor system in accordance with the preferred embodiment of the present invention; and FIG. 6 illustrates a flow chart of a preferred method of the present invention.

Description of Preferred Embodiments FIG. 1 illustrates an example of part of a processor system 100 that handles the provision of clock signals to a processor (CPU) 110 and peripheral components of the processor 110 within the processor system 100, such as a traffic controller (TC) 120, display driver (LCD) 130, general purpose input/output ports (GPIO) 140 etc.

As can be seen, an oscillator 150 provides a clock signal to the processor system 100. This clock signal is used as an origin for further clock signals within the processor system 100. It will therefore be referred hereinafter as the seed clock signal. For the illustrated embodiment the seed clock signal has a frequency of 12MHz.

The processor system 100 comprises a Digital Phased Locked Loop (DPLL) 160, which has as an input the 12MHz seed clock signal from the oscillator 150. The DPLL 160 uses the seed clock signal to generate as an output a

reference clock signal (RFCLK), by multiplying and/or dividing the seed clock signal.

The processor system 100 further comprises a clock management unit 170, which has as an input the reference clock signal generated by the DPLL 160. The clock management unit 170 uses the reference clock signal from the DPLL 160 to provide individual clock signals for the processor 110 and its peripheral components, multiplying and/or dividing the reference clock signal accordingly for each of the processor 110 and peripheral components. Thus, in the illustrated embodiment, the clock management unit 170 provides a CPUCLK clock signal to the processor 110, a TCCLK clock signal to the traffic controller 120,

an LCDCLK clock signal to the display driver 130 and a GPIOCLK clock signal to the general purpose input/output ports 140, along with any further clock signals required within the processor system 100. However, it is within the contemplation of the invention that the CPUCLK clock signal, as provided by the clock management unit 170, may be applied to any time-driven device/function in the processor system 100, and is not limited to those described above.

The clock rates provided to each of the processor 110 and peripheral components 120,130, 140 are dependent jointly on the generation of the reference clock signal REFCLK by the DPLL 160, and individually on the generation of the specific clock signals CPUCLK, TCCLK, LCDCLK and GPIOCLK by the clock management unit 170.

The DPLL 160 and clock management unit 170 are each configurable by the processor 110, for example by way of a bus 190, such that the processor 110 is able to adjust the clock signals provided by them. In this way, the processor 110 is able to alter the clock signals provided to itself and to the peripheral components, both universally through reconfiguration of the DPLL 160 and/or individually through reconfiguration of the clock management unit 170.

The processor system 100 illustrated in FIG. 1 and described above is provided for illustrative purposes only, and provides an example of an implementation for the present invention. The present invention is not limited to the specific features thereof.

According to the present invention, a processor, for example the processor 110 illustrated in FIG. 1, comprises a load monitor 180, which is in the form of a software application running thereon.

The load monitor 180 monitors the load of the processor and, depending on the load of the processor, increases or decreases the rate of a clock signal provided to the processor. The load monitor determines the load of the processor by scheduling a task to be performed by the processor at a specific time and, once the task has been performed, the load monitor determines whether the task was performed at the specified time.

Preferably, the task is scheduled to be performed at an absolute time, such as a specific hour, minute, second, millisecond etc. of the day. However, the task may alternatively be scheduled to be performed at a relative time, for example after a period of time relative to the time at which it was scheduled. Alternatively, the task may be scheduled to be performed at a relative time, for example after a period of time relative to an event.

The load monitor 180, in the context of the present invention, is preferably a software application that continuously runs in the background. When scheduling a task, the load monitor 180 schedules the task with the operating system, which controls which tasks are performed and when they are to be performed.

In accordance with the embodiments of the present invention, the task scheduled by the load monitor could be: (i) Store time (which is then accessed by load monitor) and, once the time is stored,'wake up'the load monitor; or (ii) Simply"wake up'the load monitor 180, whereby the load monitor itself checks the time it was awoken.

It is envisaged that, although the load monitor is running in the background, it will not actually do anything until the operating system allocates processor time to it. Therefore, the term'wake up', in this context, should be viewed as processor time allocated to the load monitor 180. The load monitor is itself a task,

and hence could be the scheduled task. Alternatively, the scheduled task could be to save the time, and then request the load monitor be woken up to process the time information.

Although not illustrated, the processor system preferably further comprises a real time clock (RTC), which may be provided within the processor system 100, or may be provided external to the processor system 100. In this way, the RTC provides a timing source for the load monitor 180, processor 110 etc.

Any suitable task may be scheduled by the load monitor 180 for the processor 110 to perform. However, preferably the task also includes a requirement that the processor 110 stores the absolute time of performing the load monitor task in an area of memory (not shown). In an enhanced embodiment of the present invention, the load monitor task may be to just store an absolute timing value in memory. In this manner, the memory indicates the absolute time when the processor was not too busy and was able to perform such a scheduled task. The load monitor task is preferably given a low priority, in particular the lowest possible priority. In this way, the processor 110 will only perform the load monitor task when there are no other tasks of higher priority waiting to be processed.

After the processor has performed the load monitor scheduled task, the load monitor 180 compares the actual time of performing the task to the scheduled time, and

then determines whether the task was performed at the specified time, or whether the task was performed after the specified time. Where the task was scheduled to be performed at an absolute time, the actual time the task was performed is compared to the specified time it was scheduled to be performed.

If the task was performed by the processor 110 at substantially the time for which it was scheduled, it can be assumed that the processor 110 did not have any other tasks of higher priority waiting to be performed.

Therefore, it is likely that the capacity of the processor 110 is not being fully used. Advantageously, the inventor of the present invention has therefore implemented a mechanism to recognise that, if this is the case, the processor 110 is being provided with an unnecessarily high clock rate.

Therefore, the clock signal (CPUCLK in FIG. 1) provided to the processor 110 is to be reduced, reducing the performance of the processor 110. Such a reduction in processor performance is acceptable since it would appear that the capacity of the processor 110 is not being fully used. This has the benefit of reducing the power consumption of the processor 110.

Preferably a range of clock rates are available, having a minimum clock rate, for example a rate of 4MHz, a maximum clock rate, for example a rate of 120MHz, and a plurality of clock rates there between. The range of clock rates are preferably dependent on the characteristics of the

seed clock signal and the DPLL 160, and/or clock management unit 170, which are only capable of multiplying and/or dividing their respective input clock signals.

Thus, if the load monitor task is performed at the scheduled time, preferably the load monitor 180 checks the present rate of the clock signal to see if it is at the minimum rate. If the clock signal is at its minimum rate, the clock signal is maintained; otherwise, the load monitor initiates a decrease of the clock rate to the next clock rate in the range.

However, if the task were not performed at the time for which it was scheduled, this would be due to the processor 110 being too busy performing other tasks of higher priority. Therefore it is likely that the capacity of the processor 110 is not sufficient for it to perform the various tasks waiting at their scheduled times.

Therefore, the clock signal (CPUCLK in FIG. 1) provided to the processor 110 is to be increased, as shown in FIG.

2. The increase in clock rate, increases the performance of the processor 110 in order for it to be better able to perform the various tasks waiting at their scheduled times.

Referring now to FIG. 2, a timing diagram 200 showing the respective increase in clock rate for the processor 110 (of FIG. 1) is shown, when the processor is determined as being busy. The timing diagram 200 shows clock rate (for

the processor) 210 versus time 220. As shown, the clock rate for the processor starts too low. Each increase in clock rate results from the load monitor (180 of FIG. 1) determining that the processor has failed to execute the load monitor scheduled task at the desired time.

As a result, the processor clock rate is successively increased, until it reaches a steady state clock rate 140, when it is performing at its optimum to execute its scheduled tasks, whilst keeping its associated power consumption to a minimum. In this steady state, the clock rate is effectively oscillating between the two clock rates either side of a theoretical ideal clock rate.

As previously mentioned, it is preferable that a range of clock rates are available, having a minimum clock rate, for example, a rate of 4MHz, a maximum clock, for example a rate of 120MHz, and a plurality of clock rates there between. Therefore, if the task is not performed at the time for which it was scheduled, preferably the load monitor checks the present rate of the clock signal to see if it is at the maximum rate. If the clock signal is at its maximum rate, the clock signal is maintained; otherwise, the load monitor initiates an increase of the clock rate to the next clock rate in the range.

In accordance with the preferred embodiment of the present invention, the load monitor 180 may initiate the increase/decrease in the clock rate by reconfiguring the DPLL 160 and/or the clock management unit 170

accordingly. Alternatively, the load monitor 180 may request another application (not shown) running on the processor 110 to increase/decrease the clock rate.

In this way, the processor 110 is provided with a more suitable clock rate, allowing it to perform its required task whilst being more efficient with regard to power consumption.

A clock signal provided to a component is required to have a minimum driving voltage. The higher the clock rate, the higher the minimum required driving voltage.

Accordingly, the lower the clock rate, the lower the minimum required driving voltage. Therefore, in addition to the clock rate provided to the processor 110 being increased or decreased, the driving voltage of the clock rate may also be increased or decreased, in accordance with a further embodiment of the present invention. In this way, the power consumption of the processor 110 can be improved further.

Referring now to FIG. 3, a timing diagram 300 illustrates the effect of reducing the voltage provided to hardware logic devices is shown. By reducing the voltage, the time taken for switching between logical states to be achieved is increased. This results in the edges of the signal becoming less vertical. In this way, there is an increased delay between the point at which the switching is initiated, and the new logical state being achieved 310. This delay causes a delay in further hardware logic

devices, which receive the signal, from recognising the change in logical states.

As will be appreciated, the delay is propagated through all hardware logic devices. As will also be understood by those skilled in the art, where the delay is sufficient, not all required switching would take place before the next clock cycle. This, although beneficial in terms of reduced power consumption, causes uncertainty in the behaviour of the logical hardware.

Thus, in accordance with a further embodiment of the present invention, the above technique can be applied in conjunction with the reduced clock rate, as shown in the timing diagram 400 of FIG. 4. By reducing the clock rate, the affect of the additional delay in switching is reduced, since there is a longer period of time 410 between clock cycles. Hence, the opportunity to reduce the clock rate of the processor, further enables the voltage to be driven at a lower voltage, therefore further reducing the power consumption of the device.

The voltage regulator (125 of FIG. 1) provides a voltage supply, for example up to 1.8v, to at least the CPU 110.

The voltage regulator 125 may also provide a voltage supply to the DPLL 160 and clock manager 170. Preferably, the voltage supplied by the voltage regulator 125 is controlled by the CPU 180 via a GPIO (as illustrated).

In this regard, the CPU may reduce the driving voltage from 1.8v to, for example, 1.3v as required.

It is often the case that peripheral components, such as the traffic controller, GPIOs etc. have generally rigid voltage supply requirements of, for example, 2.9v, whereby it is not possible for the voltage supplied to them to be altered. Where this is the case, it is preferred that a separate voltage regulator (not shown) provides the 2.9v voltage supply to such peripheral components.

Referring to FIG. 5, there is illustrated an embodiment of a method of monitoring the load of a processor, for example the processor 110 of FIG. 1, according to the present invention.

The method comprises the first step 510 of scheduling a task to be performed by the processor (110 of FIG. 1) at a specific time.

Preferably, the task is scheduled to be performed at an absolute time, such as a specific hour, minute, second, millisecond etc. of the day. However, the task may alternatively be scheduled to be performed at a relative time, for example after a period of time relative to the time at which it was scheduled, or other event.

Any suitable task may be scheduled for the processor to perform. However, preferably the task is for the processor to store in an area of memory (not shown) the absolute time of performing the task. The task is preferably given a low priority, in particular the lowest

possible priority. In this way, the processor will only perform the task when there are no other tasks of higher priority waiting to be processed.

The next step 520 of the method of the present invention is to compare the actual time of performing the task to the scheduled time, and then to determine, in step 525, whether the task was performed at the specified time, or whether the task was performed after the specified time.

Where the task was scheduled to be performed at an absolute time, the actual time the task was performed is compared to the specified time it was scheduled to be performed.

If the task was performed at substantially the time for which it was scheduled, the processor was able to perform the task at substantially the specified time for which it was scheduled, and so did not have any other tasks of higher priority waiting to be performed. Therefore, it is likely that the capacity of the processor is not being fully used. If this is the case, the processor is consuming power whilst, for short periods of time at least, not performing any useful tasks.

Therefore the clock signal (CPUCLK in FIG. 1) provided to the processor is to be reduced, reducing the performance of the processor, which is acceptable since it would appear that the capacity of the processor 110 is not being fully used, as well as reducing the power consumption of the processor.

Preferably a range of clock rates are available, having a minimum clock rate, for example of 4MHz, a maximum clock, for example rate of 120MHz, and a plurality of clock rates there between.

Thus, if the task is performed at the scheduled time, preferably the present rate of the clock signal is checked to see if it is at the minimum rate, as in step 530. If the clock signal is at its minimum rate, the clock signal is maintained; otherwise, it is decreased to the next clock rate in the range, as in step 535.

However, if the task were not performed at the time for which it was scheduled, this would be due to the processor being busy performing other tasks of higher priority. Therefore it is likely that the capacity of the processor is not sufficient for it to perform the various tasks waiting at their scheduled times.

Therefore the clock signal (CPUCLK in FIG. 1) provided to the processor is to be increased, increasing the performance of the processor in order for it to be better able to perform the various tasks waiting at their scheduled times.

Therefore, if the task is not performed at the time for which it was scheduled, preferably the present rate of the clock signal is checked to see if it is at the maximum rate, as in step 540. If the clock signal is at its maximum rate, the clock signal is maintained;

otherwise, it is increased to the next clock rate in the range, as in step 545.

In this way, the processor is provided with a more suitable clock rate, allowing it to perform its required task whilst being more efficient with regard to power consumption.

Furthermore, the driving voltage of the clock signal may also be increased/decreased in accordance with the clock rate to further improve the power consumption of the processor.

According to a further aspect of the present invention there is provided a processor system comprising a processor, for example the processor 110 illustrated in FIG. 1, and a load monitor application running thereon for monitoring the load of the processor, such as the load monitor 180 described above.

Preferably, the load monitor 180 continuously monitors the CPU load and adjusts the clock rate for the processor 110 accordingly. However, the load monitor 180 may alternatively be stopped once a substantially optimum clock rate of the processor 110 has been achieved. Where this is the case, the load monitor 180 may be restart either by an event, or at the expiration of a timer (not shown).

Where the load monitor 180 is continuously running, it will be appreciated by those skilled in the art that for

processor systems utilising sleep modes to conserve power, having an application continuously running could prevent a processor from being put into sleep mode. The processor 110 determines whether it is able to go into sleep mode (i. e. whether it has completed all tasks required of it at that point in time) by checking to see if any tasks are required to be performed. Therefore, if there are no tasks to be performed other than tasks scheduled by the load monitor 180, the load monitor 180 and all tasks scheduled by the load monitor 180 are ended. The processor 110 is put into sleep mode. On being awoken from sleep mode, the load monitor 180 can be restarted.

In enhanced embodiment to the present invention, when the task scheduled by the load monitor 180 is not performed at the specified time, the length of the delay in performing the task may be used as a further indication of the load of the processor 110. In this way, where there is a range of clock rates that can be provided to the processor 110, the delay in performing the task determines how far up/down the range the clock rate for the processor is increased/decreased.

For processor systems that make use of sleep modes in order to conserve power, the initial rate of the clock signal provided to the processor 110 following wake up of the processor 110 from sleep mode may be the minimum clock rate in the range. Such a technique is used in order to minimise initially the power consumption of the processor 110. If the minimum clock is insufficient for

the processor 110 to effectively perform the tasks schedule, the clock rate will be increased as described above with regard to FIG. 2.

However, in certain instances it may be that the tasks for which the processor 110 is awoken require the maximum (or relatively high) clock rate. In this regard, waiting for the clock rate to be increased incrementally from the initially provided minimum clock rate may cause the tasks to be completed too slowly. Therefore, where this is the case, it may be preferable on the first determination following wake up of the processor 110 for it to increase the clock rate to its maximum. This approach is used when it is determined that initial minimum the clock rate is insufficient. In this way, the increase in the clock rate to the maximum rate ensures that the tasks are not substantially delayed. Then, if the maximum clock rate is not required, it will be decreased incrementally until a more suitable clock rate is obtained. This approach is described in a further enhanced embodiment of the present invention, illustrated in FIG. 6.

Referring now to FIG. 6, a timing diagram 600 showing the respective increase in clock rate for the processor 110 (of FIG. 1) is shown, when the processor is awoken from a sleep mode. The timing diagram 600 shows clock rate (for the processor) 610 versus time 620. As shown, the clock rate for the processor starts at its minimum. In order to avoid an incremental increase until it reaches its steady state clock rate, a high (perhaps even maximum) clock rate is used 630.

As a result, the processor clock rate is initially set, following sleep mode, at an acceptable rate for the scheduled tasks to be performed. Once the high priority tasks have been accomplished, and the load monitor has determined that the processor has some spare capacity, the processor clock rate is decreased, again until it reaches a steady state clock rate 640.

At this time, the processor is performing at its optimum to execute its scheduled tasks, whilst keeping its associated power consumption to a minimum. In this steady state, the clock rate is effectively oscillating between the two clock rates either side of a theoretical ideal clock rate.

Since the load monitor 180, as thus far described, will not determine the load of the processor 110 until the task it scheduled has been performed, the clock rate provided to the processor 110 will remain at the minimum rate until the task is performed. Therefore, a further situation that may arise when initially providing the minimum clock rate following a wake up from sleep mode is that, if the load on the processor 110 is particularly high, it could be that the task scheduled by the load monitor 180 will not be performed for a relatively long period of time. Since the clock rate provided to the processor 110 will not be increased until the load monitor's task has been performed, the clock rate provided to the processor 110 will remain at the minimum rate. This may cause a potentially substantial delay in

the processor 110 performing the various tasks that it was awoken for.

In order to overcome this, the load monitor 180 may schedule a second task, substantially at the same time as the first task. The second task is provided with a high priority such that even if the processor 110 is busy, it will be performed ahead of tasks having a lower priority (and therefore less likely to suffer as great a delay as would the first task having a low priority).

The second task is preferably scheduled to be performed at some time after the first task. Therefore, even if the processor 110 is too busy for the first task to be performed (due to its low priority), because of the high priority of the second task, the second task should be performed substantially when scheduled.

In this way, if the second task is performed before the first task, the load monitor 180 knows that the processor 110 is too busy to perform the first task. Thus, even though the first task has not been performed, the load monitor 180 can increase the clock rate provided to the processor 110, minimising the delay to the tasks for which the processor 110 was awoken being performed.

The scheduling of a second task may also be used to ensure against delays in the first task being performed at times other than just after the processor 110 is woken up from sleep mode.

Referring back to FIG. 1, in an extension to the present invention, as the clock rate of the present invention is varied, preferably the clock rates etc of the various peripheral components are also varied in line with the clock rate of the processor 110.

For example, the processor 110 may be capable of operating with a clock rate of 120MHz, whilst the GPIO port 140 may be capable of operating with a clock rate of 60MHz. In general, it is necessary for the processor 110 to have a clock rate of at least the same as, or faster than, the clock rate of the GPIO 140 in order for the processor 110 to reliably receive signals provided to the GPIO 140.

Therefore, when the clock rate of the processor 110 is between 60MHz and 120MHz, the GPIO 140 can have a clock rate of 60MHz. This allows the processor 110 to reliably receive signals provided to the GPIO 140 whilst still allowing the GPIO 140 to operate at maximum speed.

However, when the clock rate to the processor 110 is below 60MHz, if the clock rate of the GPIO 140 remains at 60MHz, the processor 110 will not be able to reliably receive signals provided to the GPIO 140. Therefore, it is necessary for the clock rate provided to the GPIO 140 to be reduced in line with the clock rate of the processor 110.

Therefore, the peripheral components are also provided with more suitable clock rates, dependent on the clock

rate of the processor 110. Not only does this ensure that the processor 110 is able to inter-operate with the peripheral devices, but also provides the further benefit of making the power consumption of the peripheral devices more efficient. This may be achieved, for example, using a lookup table 115 providing the required clock signals of each peripheral device for each of the processor 110 clock signals within the range of processor 110 clock signals.

For clarity, the present invention provides: a load monitor for monitoring the load of a processor and, depending on the load of the processor, increasing or decreasing the rate of a clock signal provided to the processor; and the load monitor determines the load of the processor by scheduling a task to be performed by the processor at a specific time and, once the task has been performed, determining whether the task was performed at the specified time.

Furthermore, features of the method according to the present invention include: scheduling a task to be performed by the processor at a specific time ; once the task has been performed, determining whether the task was performed at the specified time; and if the task was performed after the specified time, increasing the rate of a clock signal provided to the processor; or

if the task was performed at the specified time, reducing the rate of the clock signal provided to the processor.

Thus, the load of the processor is determined by whether or not a task scheduled by the load monitor is performed at the time scheduled, or whether it was performed after the scheduled time. This, in effect, provides an indication of whether the processor is busy, i. e. operating at its capacity, or not.

However, if the task were not performed at the time for which it was scheduled, this would be due to the processor being busy performing other tasks of higher priority. Therefore it is likely that the present capacity of the processor is not sufficient for it to perform its tasks at their scheduled times, and so the clock rate should be increased in order to increase the performance of the processor.

All other features and implementations herein described and/or illustrated in the drawings are considered solely as preferred additions and/or alternatives, and are not limiting on the scope of the present invention.

Whilst the specific and preferred implementations of the embodiments of the present invention are described above, it is clear that one skilled in the art could readily apply variations and modifications of such inventive concepts.

Claims

Claims 1. A method for controlling a timing of signals in a processor-based system, the method comprising the steps of: scheduling of one or more tasks for a processor to perform; determining whether said scheduled one or more tasks were performed by said processor at a scheduled time; the method characterised by the steps of: adjusting a signal timing of said processor-based system, in response to said step of determining.
2. The method for controlling a timing of signals according to Claim 1, wherein said step of determining includes determining a processor load, the method further characterised by the steps of: adjusting a signal timing of said processor and/or any peripherals of said processor in said processor-based system according to said processor load.
3. The method for controlling a timing of signals according to Claim 1 or Claim 2, wherein said step of adjusting a signal timing is performed by increasing or decreasing a clock rate applied to devices in said processor-based system.
4. The method for controlling a timing of signals according to any preceding Claim, the method further characterised by the step of:

<Desc/Clms Page number 29>

adjusting a driving voltage applied to one or more devices in said processor-based system.
5. The method for controlling a timing of signals according to any preceding Claim, the method further characterised by the step of: allocating a priority to a number of tasks to be performed by said processor, such that said step of determining whether said scheduled one or more tasks were performed indicates whether the processor is busy or not.
6. The method for controlling a timing of signals according to any preceding Claim, the method further characterised by the step of: enabling said processor to enter a sleep-mode; and setting a minimum clock rate to be applied to said processor when initially leaving said sleep mode, to conserve power consumption; prior to said steps of scheduling, determining and adjusting.
7. The method for controlling a timing of signals according to any of preceding Claims 1 to 5, the method further characterised by the step of: enabling said processor to enter a sleep-mode ; and setting a high clock rate to be applied to said processor when initially leaving said sleep mode, to ensure said processor is able to complete any tasks ; prior to said steps of scheduling, determining and adjusting.

<Desc/Clms Page number 30>
8. The method for controlling a timing of signals according to any preceding Claim, the method further characterised by the steps of: scheduling a second task for said processor to perform, of a higher priority than said first scheduled task; determining whether said scheduled second task was performed by said processor at a scheduled second time; and adjusting a signal timing of said processor-based system, in response to said step of determining the performance of said scheduled second task.
9. A processor comprising, or operably coupled to, a load monitor and adapted to perform any of the method Claims 1 to 8.
10. A processor based system adapted to perform any of the method Claims 1 to 8.
11. A portable device comprising the processor of Claim 9 or the processor-based system of Claim 10.
12. A processor based system, comprising: a processor for performing tasks, the processor based system characterised by: a load monitor function, operably coupled to said processor, such that said load monitor schedules one or more tasks for said processor to perform and determines whether said scheduled one or more tasks were performed by said processor at a scheduled time, wherein a signal

<Desc/Clms Page number 31>

timing of said processor is adjusted according to said load monitor determination.
13. The processor based system according to Claim 12, wherein said timing of processing signals is adjusted by said processor or a clock management function operably coupled to, and under control of, said processor in response to said determination.
14. The processor based system according to Claim 12 or Claim 13, wherein said load monitor function is periodically switched off when said signal timing applied to said processor or peripheral components approaches an optimum timing.
15. The processor based system according to any of preceding Claims 12 to 14, wherein said load monitor function schedules a, preferably low priority, task for said processor, wherein said task includes one or more of the following: (i) Storing an absolute time of performing the task in a memory element operably coupled to said processor; (ii) An absolute time; and/or (iii) Providing a wake up signal to said load monitor function.
16. The processor based system according to any of preceding Claims 12 to 15, wherein said load monitor function schedules a, preferably low priority, task for said processor task to be performed at one of:

<Desc/Clms Page number 32>

(i) An absolute time; (ii) A relative time to the time scheduled; or (iii) A relative time following an event.
17. A battery powered device, for example a mobile cellular phone, comprising the processor-based system according to any of Claims 12 to 16.
18. A method for controlling a timing of signals substantially as hereinbefore described with reference to, and/or as illustrated by, FIG 5 of the accompanying drawings.
19. A processor based system substantially as hereinbefore described with reference to, and/or as illustrated by, FIG 1 of the accompanying drawings.