EP1491995A2 - Fifo-Speicher - Google Patents

Fifo-Speicher Download PDF

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Publication number
EP1491995A2
EP1491995A2 EP20040102921 EP04102921A EP1491995A2 EP 1491995 A2 EP1491995 A2 EP 1491995A2 EP 20040102921 EP20040102921 EP 20040102921 EP 04102921 A EP04102921 A EP 04102921A EP 1491995 A2 EP1491995 A2 EP 1491995A2
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Prior art keywords
read
write
buffer
input data
receiving
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Granted
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EP20040102921
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English (en)
French (fr)
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EP1491995B1 (de
EP1491995A3 (de
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Heyun H. Liu
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Texas Instruments Inc
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Texas Instruments Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9084—Reactions to storage capacity overflow
    • H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/108—Reading or writing the data blockwise, e.g. using an extra end-of-block pointer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/123—Contention resolution, i.e. resolving conflicts between simultaneous read and write operations

Definitions

  • This invention is in the field of integrated circuit memory architecture, and is more specifically directed to the architecture of memories as used in first-in-first-out (FIFO) buffers.
  • FIFO first-in-first-out
  • Ethernet networking involves the use of packet-based communications, by way of which each communication is transmitted in multiple packets, each packet including identification information such as the destination and source addresses for the message, and the position of the packet within the sequence that makes up the overall communication.
  • identification information such as the destination and source addresses for the message
  • This approach enables the efficient deployment of high-capacity networks, which may be quite complex in structure, in a manner that permits high fidelity in the successful and efficient transmitting of digital data of varying types and sizes.
  • Ethernet technology has played a large part in the development and deployment of the Internet.
  • Packet-based communications have played a large role in the realization of digital multimedia communications, and in communications at varying Quality of Service (QoS) levels.
  • QoS levels specify different data performance, and can support different priority communications and, ultimately, can support different rates or tariffs that can be charged to the users.
  • QoS levels or classes include constant bit rate (CBR), unspecified bit rate (UBR, also referred to as best-effort), and variable bit rate (VBR). These well-known categories ensure the fair allocation of the available bandwidth over a communications channel.
  • lossless flow control in the Ethernet context involves some amount of buffering of the transmitted data at each node in the network.
  • This buffering is often necessary because of the variable nature of the architecture of a given network, and because of the possibility that a bottleneck may exist somewhere in the network downstream from a given network node.
  • sufficient buffer capacity must be provided to store one or more packets, at the receive and transmit sides of a node, in the event of a downstream bottleneck; the buffered packets can then be forwarded later, when network conditions permit.
  • This buffering is often accomplished by way of a dual-port memory, acting as a dual-port first-in first-out (FIFO) buffer.
  • FIFO first-in first-out
  • the dual-port buffer permits simultaneous, and asynchronous, reads and writes to the buffer, which is particularly beneficial considering the asynchronous nature of the communications on both side of a given network node. Given a FIFO buffer of sufficient capacity, loss-less flow control can be readily carried out.
  • the transmit side of the receiving node issues a pause request to the transmitting network node, requesting a pause in the transmission of data packets.
  • the transmitting node finishes transmitting the current packet, the remainder of which must be buffered at the receiving node for the communication to remain lossless.
  • the FIFO buffer at the receive node must have sufficient capaci ty to store a volume of data that is transmitted during the delay required for the receiving node to initiate the pause request, during the delay of the transmitting node in receiving and processing the pause request, and also during the remainder of the current packet.
  • a high data rate thus necessitates a rather large buffer for lossless operation. Long distance s between network nodes also contribute to the required FIFO capacity because the FIFO must also buffer the bits that are in transit over the facility.
  • MAN s should have cable lengths of on the order of 40 km, and should be capable of Gigabit Ethernet communications supporting jumbo packets according to 10GBASE-W.
  • this functionality will require FIFO capacities of on the order of several megabits, which of course are prohibitively expensive to realize via dual-port RAM, especially considering the recent trend to integrate the media access control (MAC) circuitry for Ethernet and other packet-based networking into a single integrated circuit. For these reasons, a disconnect exists between the available technology for FIFO memory and the functional need of Gigabit Ethernet in the MAN environment.
  • MAC media access control
  • dual-port memories are useful at any large data rate, or data quantity, interface between asynchronous system elements.
  • interfaces include data transfer interfaces between computer subsystems or input/output devices and a main computer bus, non-packet-based networking applications, interfaces between dissimilar microprocessors or CPUS in a multiprocessing environment, emulation systems, and the like.
  • MAN Metro Area Network
  • the present invention may be implemented into a memory architecture including a double width array of conventional single-port memory cells.
  • the memory array is of a double-word-width relative to the external data width.
  • a write buffer buffers two data words, with writes to the memory array being of double-word width.
  • external read requests are buffered so that reads from the memory array are of double width, effected upon two or more requests being received.
  • Sequential logic controls the memory so that asynchronous external reads and writes are internally performed as scheduled reads from and writes to the memory array.
  • the present invention will be described in connection with its preferred embodiment, namely as implemented into transmit and receive buffers of high data rate Ethernet network nodes.
  • This exemplary description is selected because of the particular benefits that this invention provides in that environment.
  • this invention may be used in connection with first-in-first-out (FIFO) buffers in general, and as implemented in a wide range of applications. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.
  • FIFO first-in-first-out
  • FIG. 1a An example of a high data rate communication system into which the preferred embodiment of the invention is implemented is shown in Figure 1a, in the form of a functional data flow diagram.
  • two network nodes 5A, 5B are communicating with one another over a medium, which in this example is fiber optic facility FO.
  • Either or both of network nodes 5 may be a Metro Area Network (MAN) node, a Local Area Network (LAN) switch, or the like, and as such are generically referred to as network nodes 5 in the system functional diagram of Figure 1a.
  • MAN Metro Area Network
  • LAN Local Area Network
  • Each of network nodes 5A, 5B include both a transmit side and a receive side, each of which includes FIFO buffering and media access control (MAC) functionality.
  • MAC media access control
  • transmit MAC FIFO 2A buffers data to be transmitted over facility FO via transmit MAC function 4A; on the receive side, receive MAC function 6A receives data from facility FO and forwards the received data to receive MAC FIFO 8A.
  • Network node 5B is similarly constructed.
  • network nodes 5A, 5B of Figure 1a may be implemented according to the available technology and according to specific system attributes, such as type of communications facility (e.g., fiber optic, coaxial cable, twisted pair, wireless).
  • network nodes 5 may be implemented in the form of a line card of another conventional network element or network line.
  • Figure 2 illustrates, in block form, a typical hardware realization of network node 5 according to the exemplary implementation of a Gigabit Ethernet line card for an optical network implementation.
  • network nodes 5A, 5B may be constructed in ways other than that illustrated in Figure 2, and indeed need not be constructed similarly as one another, so long as the appropriate communications protocols are obeyed by each.
  • network node 5 includes system 10, which generically refers to the function of node 5 in the overall communications network of Figure 1a.
  • system 10 will correspond to those switching and routing functions; alternatively, if network node 5 is a server, then system 10 will be realized by a server architecture.
  • System 10 may also be realized by a switching fabric, or simply a bus connected to other line cards, in some architectures.
  • Line card 20 performs various functions involved in transmitting data from downstream functions 10 over fiber optic facility FO, and in receiving signals from fiber optic facility FO for downstream functions 10.
  • the functions performed by line card 20 include those functions involved in the layer 2 protocol processing (e.g., media access control, or MAC) and physical (PHY) protocol layers.
  • line card 20 is connected on its system side to downstream functions 10, and on its line side to fiber optic facility FO via laser diodes and amplifiers 32 (for transmit) and photodiode and amplifiers 34 (for receive).
  • line card 20 is realized in a single integrated circuit device, for reduced cost and improved performance.
  • This implementation of line card 20 may be referred to as an application specific signal processor (ASSP), and may be realized by way of one or more digital signal processors (DSPs).
  • ASSP application specific signal processor
  • DSPs digital signal processors
  • line card 20 may be implemented in several devices as a chipset, or integrated with additional functions such as some or all of downstream functions 10.
  • line card 20 may be functionally considered as having transmit and receive "sides". Typically, some of the functionality of each of the transmit and receive sides of line card 20 may be performed by the same physical hardware, such as a DSP core or custom logic. For clarity in this description, however, the construction of line card 20 according to the preferred embodiment of the invention will refer to the construction of line card 20 according to its transmit and receive sides.
  • Management logic 25 is preferably provided within line card 20, to control the operation and coordination of the transmit and receive functions.
  • transmit system interface 22T interfaces with downstream functions 10, preferably according to a modern interface protocol such as the System Packet Interface (SPI) standard.
  • Interface 22 receives data from downstream functions 10, and forwards this data to transmit FIFO 24T for eventual transmission over fiber optic facility FO,.
  • Transmit FIFO 24T which equates to transmit MAC FIFO 2A or 2B in the functional diagram of Figure 1a, buffers the data received from downstream functions 10 until the data can be forwarded to transmit MAC processor 26T in line card 20.
  • transmit FIFO 24T will be described in further detail below, for the example of a Gigabit Ethernet implementation, in which case the layer 2 protocol processing layer equates to the media access control (MAC) layer.
  • MAC media access control
  • Transmit MAC processor 26T processes the buffered received data into the appropriate form for transmission over facility FO, according to the particular protocols in place. Typically, it is contemplated that such operations as flipping of bytes from LSB-first to MSB-first, stripping of Ethernet headers, byte counting, insertion of control bytes, character or symbol alignment, and formatting into packets, are performed by transmit MAC processor 26T.
  • the formatted and processed data in the appropriate format such as XGMII (10 Gbit Media Independent Interface), are then forwarded to transmit XAUI 28T.
  • Transmit XAUI (10 Gbit Attachment Unit Interface) 28T converts the data into the appropriate format, an example of which is a forty-bit four-channel datapath. This XAUI-formatted data are then forwarded to transmit serializer 30T, which converts the parallel channel data into serial streams that are compliant with the transmission standard. For example, where the output of transmit XAUI 28T is provided as four channels of ten-bits in parallel, transmit serializer 30T serializes these four channels into four single-bit serial channels, each operating at high speeds such as on the order of 3.125 Gbps for 10 Gbit communications. The serial data output by transmit serializer 30T are then applied to laser diode and amplifier block 32, which generates the appropriate optical signals applied to fiber optic facility FO.
  • transmit serializer 30T serializes these four channels into four single-bit serial channels, each operating at high speeds such as on the order of 3.125 Gbps for 10 Gbit communications.
  • the serial data output by transmit serializer 30T are then applied to laser diode and amplifier block 32, which generate
  • Incoming optical signals are converted by photodiode and amplifiers 34 into an electrical signal that is forwarded to deserializer 30R in line card 20.
  • MAC processor 26R performs such functions as MSB-first to LSB-first translation, adding Ethernet headers, byte counting, removal of control bytes, character or symbol alignment, and formatting into the desired packet structure.
  • transmit and receive XAUI 28T, 28R, serializer 30T, and deserializer 30R may be embodied within a single integrated circuit device, referred to in the art as a transceiver; of course, the particular boundaries of integrated circuits used in line card 20 may vary widely, depending upon the manufacturing technology and the available functionality.
  • Receive FIFO 24R equates to receive MAC FIFO 8A or 8B in the functional diagram of Figure 1a.
  • receive FIFO 24R buffers the formatted and processed data received over fiber optic facility FO, until the data is forwarded to downstream functions 10.
  • the construction of transmit FIFO 24R according to the preferred embodiments of the invention will also be described in further detail below.
  • Receive FIFO 24R outputs the buffered data to receive system interface 22R, which interfaces with downstream functions 10, preferably according to a modern interface protocol such as the System Packet Interface (SPI) standard.
  • SPI System Packet Interface
  • receive MAC FIFOs 8A, 8B may be implemented as receive FIFO 24R within line card 20, as shown in Figure 2 and described above.
  • receive MAC FIFO 8A issues a request for a pause frame (pause_fr_req) to its transmit MAC function 4A.
  • Transmit MAC function 4A then issues a request (pause_fr) for a pause frame of a specified duration (pause_time) to network node 5B.
  • the pause frames are ON and OFF messages, where the ON message is a frame with maximum pause quanta and the OFF message is a frame with zero pause quanta.
  • Receive MAC function 6B will receive this request, and cause its corresponding transmit MAC function 4B to pause the sending of data for a specified duration, measured by pause counter 9B in the conventional manner, following the completion of the packet that is currently being transmitted.
  • receive MAC FIFO 8A (e.g., receive FIFO 24 in line card 20) must have sufficient capacity, beyond the capacity threshold at which it issues a pause frame request, to store packet data that continues to be transmitted after its pause frame request but until the pause actually begins.
  • the size of receive MAC FIFO 8A, and also the threshold at which it issues a pause frame request, must contemplate this absorption of traffic.
  • delay time D t_int is the delay time, internal to network node 5A, between the clock cycle in which receive FIFO 8A reaches its "full” threshold and the clock cycle in which the pause frame request propagates to the edge of the external PHY media (facility FO).
  • Delay time D ext is the delay of the pause request as it is transmitted over the fiber optic facility FO to network node 5B, and also the delay of the leading edge of the stopped traffic propagating to the edge of fiber optic facility FO leading from network node 5B to network node 5A.
  • internal delay time D r_int is the internal delay time between transceiver 7A receiving the pause request, protocol function 6A handling the pause request, and receipt traffic actually stopping at receive FIFO 8A.
  • delay time D pkt the time required for the completion of a current packet.
  • this capacity C can be defined from: where the delay times D are measured in terms of "bit times" (i.e., number of clock cycles multiplied by the bits transmitted per cycle).
  • receive FIFO 8A will initially store an amount of data that fluctuates in a range well below its “full” threshold. Once this "full” threshold is reached, however, then the amount of data stored within receive FIFO 8A will tend to fluctuate around the "full” threshold, maintained by its issuing of pause frame requests to the transmitting node.
  • the actual physical size of the FIFO buffers can be calculated for specific communications protocols and systems. For example, in modem 10 Gigabit Ethernet wide area networks (WANs) that implement so-called “Metro Networks”, typical packet lengths can be as long as 1526 byte payloads, with 118 overhead bytes. If so-called "jumbo" packets are permitted, the packet lengths can be as long as 10000 bytes, with 780 overhead bytes.
  • the worst case delay time D pkt for jumbo WAN packets is therefore about 86,240 bit times (10780 * 8).
  • the internal delay component D int can vary from 14848 to 30720 bit times, depending upon the particular type of 10GE coding (i.e., 10GBASE-R, -W, or -X).
  • a more desirable installation for a conventional Metro Area Network is a cable length M of on the order of 40 km, supporting jumbo packets according to 10GBASE-W; for this functionality, which requires a FIFO capacity C of on the order of several megabits.
  • FIFO buffers are typically implemented by memories of conventional dual port architecture.
  • the dual port architecture enables efficient FIFO operation, as the two ports to each memory cell can operate in effectively an asynchronous manner, matching the asynchronous buffer function of the FIFO itself.
  • dual port memories of megabit capacity are prohibitively expensive, especially when considering the integration of such memories as on-chip functions within a VLSI integrated circuit.
  • conventional single port memories of this size can be realized within reasonable chip area, and are suitable for implementation into complex logic circuitry, such as that logic involved in a Gigabit Ethernet transceiver function such as line card 20 of Figure 2.
  • transmit and receive FIFOs 24T, 24R of line card 20 are constructed as memories having a single port memory array, for example of a capacity on the order of up to several megabits, but which appears to be a dual-port buffer to the external circuits and functions that write to and read from FIFOs 24T, 24R.
  • FIFOs 24T, 24R are thus capable of serving as transmit and receive MAC FIFOs 2, 8 in the network arrangement of Figure 1a, enabling the implementation of high speed communications over relatively long distances, for example in Gigabit Ethernet communications in a MAN context, with distances between nodes of on the order of kilometers.
  • this FIFO memory may be implemented into the network node of Figure 2 as either one of transmit and receive FIFOs 24T, 24R, for performing the MAC FIFO buffer functions 2A, 2B, 8A, 8B in the system that is functionally illustrated in Figure 1a. It is further contemplated that the construction of the FIFO memory according to the preferred embodiment of this invention will also be beneficial in other applications of FIFO buffering, beyond those involved in high-speed network communications.
  • Examples of such other uses include data transfer interfaces between computer subsystems or input/output devices and a main computer bus, non-packet-based networking applications, interfaces between dissimilar microprocessors or CPUS in a multiprocessing environment, emulation systems, and the like.
  • FIG. 3 illustrates a simplified example of the interfaces to FIFO memory 40, according to the preferred embodiment of the invention.
  • clock CLK is applied to FIFO memory 40, to serve as a system clock for FIFO memory 40 and its operation.
  • FIFO memory 40 receives write enable signal WREN, which indicates that a source of data to FIFO memory 40 is requesting a write operation of data presented on input data lines WRDATA. It is contemplated that the data width of input data lines WRDATA will be at least one byte (eight bits), and preferably one data word in width (sixteen or thirty-two bits).
  • WREN write enable signal
  • FIFO memory 40 receives read enable signal RDEN, indicating that a destination of data from FIFO memory 40 is requesting a read of data, which FIFO memory 40 will present on output data lines RDDATA, which will typically be of the same data width as input data lines WRDATA.
  • Figure 4a illustrates the operation of the write interface to FIFO memory 40 during a sequence of asynchronous write and read operations
  • Figure 4b illustrates the operation of the read interface to FIFO memory 40 over the same cycles as shown in Figure 4a.
  • write enable line WREN is taken to a high active level during such time as input data lines WRDATA are carrying data value WR1.
  • data value WR1 is written into FIFO memory 40.
  • Input data lines WRDATA next receive data value WR2, while write enable line WREN remains high.
  • This data value WR2 is written into FIFO memory 40 upon the next rising edge of clock CLK, in write cycle wcyc2.
  • write enable line WREN is taken inactive low for a cycle or so, and is again activated while input data lines WRDATA are carrying data value WR3.
  • This data value WR3 is written into FIFO memory 40 upon the next rising edge of clock CLK, in write cycle wcyc3.
  • Input data lines WRDATA receive the next data value WR4, which are written into FIFO memory 40 upon the next rising edge of clock CLK, because write enable line WREN remains high during that cycle.
  • FIG. 4a read operations from FIFO memory 40 are being carried out during the write operations. These reads are asynchronous with the write operations, as evident from the non-aligned nature of write and read enable signals WREN, RDEN, and also from the non-aligned activity on input and output data lines WRDATA, RDDATA.
  • Figure 4b illustrates the operation of the read operations that are carried out in these cycles, from FIFO memory 40 according to the preferred embodiment of the invention.
  • read enable line RDEN Prior to the first rising edge of clock CLK in Figure 4b, read enable line RDEN is taken active high. The rising edge of clock CLK then initiates a read from FIFO memory 40, with the data appearing on output data lines RDDATA after an access time (e.g., one cycle of clock CLK). In this first example, this data value from first rising edge of clock CLK is shown as data value RD1. In this example, read enable line RDEN remains high for the next rising edge of clock CLK, in response to which FIFO memory 40 presents the next data value RD2 on output data lines RDDATA. In this example, read enable line RDEN goes inactive for a cycle or so, precluding any reads responsive to the next rising edge of clock CLK.
  • FIFO memory 40 externally appears exactly like a dual port RAM, because reads and writes are requested and carried out effectively in an asynchronous manner relative to one another.
  • the data written to and read from FIFO memory 40 will relate to one another in FIFO fashion, in that the first data values written into FIFO memory 40 will be the first values read therefrom.
  • FIFO memory 40 appears to external functions as a dual port RAM, it is constructed from a single port RAM architecture, thus greatly saving the cost and silicon area required for its realization. Indeed, it is contemplated that the present invention permits the construction of sizable FIFO memories having dual port capabilities, at a cost that is not prohibitive.
  • Dual-port FIFO functions may be constructed according to this invention that may in fact be integrated into the same integrated circuit as the logic functions used in network communications, as described above.
  • FIFO memory 40 is based on SRAM array 45, which is constructed as an array of single-port memory cells arranged in rows and columns, together with the appropriate addressing circuits, sense amplifiers, and input/output circuitry, as conventional for a typical SRAM array as known in the art.
  • the memory cells in SRAM array 45 may be conventional 6-transistor, or 4-transistor, 2-resistor cells. According to this embodiment of the invention, however, the input and output data width into and out of SRAM array 45 is two words wide, relative to the word width of the read and write interfaces to FIFO memory 40.
  • FIFO memory 40 thus includes a "double word width domain", including SRAM array 45 and interface circuitry to it, as will now be described. As will become apparent from the following description, this double word width domain serves to resolve write and read conflicts to SRAM array 45, permitting FIFO memory 40 to externally appear as a dual port memory while using single port memory cells in SRAM array 45.
  • FIFO memory 40 also includes the appropriate power supply and clock control circuitry as conventional in the art.
  • Figure 5 also illustrates control logic and clock circuitry 47, which includes the appropriate logic for controlling the operation of FIFO memory 40, including according to the operation described below.
  • control logic and clock circuitry 47 also receives clock CLK, and includes circuitry for generating the appropriate internal clocks, including alternating internal read and write clock cycles according to this preferred embodiment of the invention, ultimately responsive to clock CLK.
  • clock CLK clock
  • separate clock circuitry may alternatively be provided within FIFO memory 40 to receive and buffer system clock CLK, and generate and forward internal clocks based on system clock CLK to the constituent functions of FIFO memory 40, as desired.
  • FIFO memory 40 is preferably realized by way of sequential logic, according to the state diagrams described below, which may be implemented in a central location as suggested by control logic and clock circuitry 47 of Figure 5, or distributed throughout FIFO memory 40 as desired. It is contemplated that the particular implementation of these control functions for a particular application can be readily accomplished by those skilled in the art having reference to this specification.
  • write buffer 42 receives write enable signal WREN, and also receives input data WRDATA.
  • write buffer 42 buffers each incoming data word of input data WRDATA when enabled by write enable signal WREN, and upon the rising edge of clock CLK.
  • each single-word write request to FIFO memory 40 and its corresponding data are buffered at write buffer 42.
  • the actual write to the appropriate location of SRAM array 45 is effected after two words have been received and upon an internal write cycle becoming available.
  • cycles of clock CLK are evenly distributed, and preferably alternate, between internal read cycles from, and internal write cycles to, SRAM array 45.
  • the converting of single-word-width internal input and output to and from double-word-width internal input and output enables the implementation of FIFO memory 40 using single port memory cells in SRAM array 45.
  • the double word width domain of FIFO memory 40 resolves conflicts between asynchronous reads and writes to SRAM array 45 by assigning either a read cycle or a write cycle to each clock cycle, and by including a two-stage, two-word-wide buffer, at both of the read and write interfaces.
  • write buffer 42 includes entries arranged as two rows (0, 1) and two columns (a, b), at the write and read interfaces, respectively. Each entry a0, a1, b0, b1 stores a single data word.
  • write and read data (depending upon the buffer) is registered into the buffer in a fixed order, for example, a1, a0, b1, b0, a1, a0, b1, b0, and so on.
  • a column of the buffer will be considered as "matured" if both of its entries are occupied.
  • alternating cycles of clock CLK are designated as read and write cycles between SRAM array 45 and write buffer 42 or output width converter 46, as the case may be (shown in Figure 6 as read cycle RCYC and write cycle WCYC).
  • the operation of the buffering involves (i) registering input and output data into the buffer in the fixed order (a1, a0, b1, b0, ... ) in each cycle, and (ii) executing a read or a write operation in the corresponding read or write clock cycles, if a column is matured in the read and write buffers, respectively.
  • the operation of write buffer 42 in this manner will now be described relative to the state diagram of Figure 7.
  • write buffer 42 After reset, or initialization, of FIFO memory 40, or upon a fault condition such as FIFO memory 40 becoming completely full, write buffer 42 enters "all empty" state 50. As shown in Figure 7, in this state 50, none of the four data word entries of write buffer 42 contain registered data, and as such write buffer 42 is effectively empty. For those cycles of clock CLK (read or write) in which write enable line WREN is inactive (indicated in Figure 7 by ⁇ WREN), write buffer 42 remains in empty state 50. Upon the write enable line becoming active (WREN), write buffer 42 will enter state 52 in the next cycle of clock CLK, in which an input data word is registered in its entry a1.
  • write enable line WREN is inactive
  • An active signal on write enable line WREN causes write buffer 42 to register a data word in entry a0, moving write buffer 42 to state 54, in which a full column (column a) contains registered data. Because this column has now matured, a double data word becomes writable from write buffer 42 to SRAM array 45 upon the next write cycle (WCYC).
  • next write cycle WCYC occurs in combination with an active level on write enable line WREN
  • the double data word is written from write buffer 42 from column a and a data word is also received by write buffer into entry b1, moving write buffer 42 to state 55 as shown in Figure 7.
  • write buffer 42 remains in state 55 for one or more successive cycles with inactive write enable -WREN.
  • write buffer registers a data word in entry b0 and moves into state 57.
  • write buffer 42 registers another data word into entry b1 and transfers to state 56 if write enable line WREN is active, or remains in state 54 with no additional data word if write enable line WREN is inactive.
  • state 56 column a of write buffer 42 has matured, and entry b1 is also registered with data. Because state 56 is entered only during a read cycle RCYC, the next cycle of clock CLK is necessarily a write cycle (WCYC) according to this embodiment of the invention.
  • the state change from state 56 thus depends upon whether an active level is received on write enable line WREN. If write enable line WREN is inactive ( ⁇ WREN) in this next write cycle (WCYC), no new data is received, but the double data word is written from matured column a to SRAM array 45; write buffer 42 enters state 55 as a result. On the other hand, if write enable line WREN is active, a data word is registered in entry b0, the double data word is written to SRAM array 45 from column a of write buffer 42, and write buffer 42 moves to state 57.
  • read interface of FIFO memory 40 involves read buffer 46 and output FIFO 48.
  • This particular construction is especially beneficial to the use of FIFO memory 40 in a network application, as described above relative to Figures 1 and 2, to ensure integrity of the packet stream, by enforcing the constraint that the read of a packet will not begin until all or a sufficient amount of data from the packet is stored in FIFO memory 40.
  • This function is effected in FIFO memory 40 by its asserting of an active signal on control line RD_RDY when the packet conditions (sufficient data, or complete packet) indicate that a read of the packet stream data in FIFO memory 40 may be made.
  • the asynchronous reads and writes from external to FIFO memory 40 must be converted to scheduled reads and writes internally, in order to avoid read and write conflicts; scheduled reads therefore cannot necessarily be synchronized with the external, asynchronous, read strobes or requests.
  • this synchronizing is effected by output FIFO buffer 48, preferably constructed of a small true dual-port memory, which effectively absorbs the response time difference of the data output from SRAM array 45.
  • output FIFO 48 when SRAM array 45 is ready to provide data and issues a signal on line SRAM_rd_rdy to that effect, output FIFO 48 in turn asserts a signal on line RD_RDY to the external downstream destination of the data when data may be read from FIFO memory 40.
  • FIFO memory 40 is ready to be read when an end-of-packet (EOP) indication has been stored in SRAM array 45 for a packet, or when a sufficient amount of data for a given packet has been stored.
  • EOP end-of-packet
  • Output FIFO 48 is then available to receive an externally generated read request, or read strobe, which is made by an active signal on line RDEN. These external requests are forwarded to read request buffer 44 via line FIFO_rden.
  • Read request buffer 44 stores the incoming requests and, upon two such requests being made in combination with a read clock cycle becoming available internal to FIFO memory 40, effects a scheduled read of two data words from SRAM array 45, to occur upon
  • output FIFO 48 is preferably constructed as a small amount of dual-port RAM in combination with various control logic for effecting and controlling the read requests, and for synchronizing the output data to be applied on lines RDDATA at a relatively constant time relationship relative to the request on line RDEN.
  • Output FIFO 48 thus effectively synchronizes the output data stream, despite the internal reads and writes within FIFO memory 40 being scheduled relative to one another.
  • Output FIFO 48 forwards the requested data words on data lines RDDATA, and asserts an active level on line D_VAL to indicate the presence of valid data.
  • the data stream being written into and read from FIFO memory 40 is packet-based, as mentioned above.
  • the end of a packet is indicated by a data word encoded as an end-of-packet (EOP) indicator.
  • EOP end-of-packet
  • write buffer 42 only writes matured columns into SRAM array 45, each EOP indicator should be followed by at least one idle data word, to keep the EOP indicator from remaining indefinitely in the first entry of a column of write buffer 42.
  • the combination of alternating read and write clock cycles (RCYC, WCYC), with write buffer having two double data word entries enables asynchronous writes to FIFO memory 40 from external sources, while permitting scheduled writes to the single port SRAM array 45 within FIFO memory 40.
  • FIFO memory 40 preferably includes additional control functionality to manage these packets.
  • This control functionality for packet management will now be described relative to the state diagram of Figure 8, and implemented as packet management logic within control logic and clock circuitry 47, either centrally or in a distributed fashion, in FIFO memory 40.
  • packet management logic is provided to ensure the coherence of packets that are read from FIFO memory 40.
  • control logic 47 it is important for control logic 47 to comprehend the number of packets that are stored within FIFO memory 40, and to comprehend the start and end of these stored packets.
  • FIFO memory 40 according to this embodiment of the invention has the capability of handling "cut through" packets, which are packets of a size greater than a configurable threshold. For packets of a size greater than this threshold, the reading out of the beginning of the packet from FIFO memory 40 is permitted prior to the writing in of the end of the packet. As such, the "cut through" packet will not have both a start and end within FIFO memory 40 at any given time.
  • the state diagram of Figure 8 refers to the state of sequential logic within control logic 47 of FIFO memory 40 that controls the packet management functions.
  • This state diagram operates in connection with a set of state variables, in which SOP refers to a start-of-packet indicator in the data stream, and in which EOP refers to an end-of-packet indicator:
  • initial no_pkt state 70 is entered upon reset of FIFO memory 40.
  • state 70 no part of any packet is stored within FIFO memory 40.
  • FIFO memory 40 makes a transition to first_sop state 72 upon receiving an indication that an SOP has been written into FIFO memory 40 (write_sop); the writing_pkt state variable is then set in response to this event.
  • a transition from first_sop state 72 occurs upon the end of this first packet being written (write_eop), in response to which the writing_pkt state variable is cleared, and the #pkt state variable is incremented to the value 1, indicating that one complete packet has been written into FIFO memory 40.
  • Control logic 47 then enters one_pkt_rdy state 74.
  • Control logic 47 remains in one_pkt_rdy state 74 after the start of a next packet is also being written into FIFO memory 40 (write_sop), during which time the writing_pkt state variable is set.
  • the pkts_rdy state 75 indicates that more than one packet is stored within FIFO memory 40.
  • control logic 47 makes a transition to tx_last_pkt state 76, setting the sending_pkt state variable.
  • tx_last_pkt state 76 refers to the state in which the only or last remaining packet is in the process of being read from FIFO memory 40.
  • control logic 47 remains in tx_last_pkt state 76 if the start of a new packet is being read (write_sop), setting state variable writing_pkt. If the end of this next packet is written before the last packet is read out (write_eop, in combination with the confirming condition of #pkt+1 is greater than or equal to 2), control logic 47 makes a transition to pkts_rdy state 75, incrementing state variable #pkt and clearing state variable writing_pkt.
  • control logic 47 manages the possibility of zero, one, or more than one packet being stored.
  • control logic 47 enters cut_thru state 78 from first_sop state 72, in response to state variable pass_cut_thru_Th indicating, in the true condition, that the size of the packet for which an SOP has been written (state 72) is greater than a preselected threshold size.
  • state variable sending_pkt is set to indicate that this packet is readable from FIFO memory 40. Both of the state variables writing_pkt and sending_pkt are set in this condition, indicating that the same large packet is both being written and being read simultaneously.
  • cut_thru state 78 receipt of the end of the jumbo packet (write_eop) by FIFO memory 40 causes control logic 47 to make a transition to tx_last_pkt state 76, incrementing state variable #pkt and clearing the writing_pkt state variable.
  • the last remaining packet in FIFO memory 40 at this point is the remainder of the jumbo packet.
  • FIFO memory 40 in the network communications context described above relative to Figures 1 and 2 preferably contemplates the operation of FIFO memory 40 in a context in which reads from FIFO memory 40 can stop synchronously with the read strobe RDEN.
  • this is made somewhat difficult because reads of SRAM array 45 internally to FIFO memory 40 are scheduled reads, rather than strobed or asynchronous reads.
  • the need to synchronously stop reading data from SRAM array 45 can arise in two situations.
  • reads from SRAM array 45 should preferably stop after the output of an EOP externally from FIFO memory 40 if the next frame of data is not ready (i.e., because it is neither fully stored within SRAM array 45 nor corresponds to a "cut through" frame), in order to avoid the underflow condition in which all available data is read out of FIFO memory 40 before SRAM array 45 receives the EOP for the next packet.
  • a second such situation arises when the external downstream destination deasserts the read enable signal, either at the end of a packet or in mid-packet.
  • output FIFO 48 is provided to effect a "read brake" function in these two situations, as will now be described relative to Figure 9.
  • output FIFO 48 includes dual port FIFO 92, output register 94, and strobe buffer 90 (which corresponds to read request buffer 44 of Figure 5).
  • Strobe buffer 90 receives the read strobe on external read enable line RDEN from the data destination, and buffers this read strobe into a signal applied to dual port FIFO 92.
  • Dual port FIFO 92 is a conventional small FIFO memory, preferably configured with dual port memory cells; typically, however, dual port FIFO 92 is much smaller than SRAM array 45, and need only be of sufficient size to retain a few data words.
  • Register 92 temporarily stores a data word after being output by dual port FIFO 92 and prior to being applied on output data lines RDDATA, to achieve synchronization.
  • the downstream external destination of data from FIFO memory 40 asserts and deasserts a read strobe signal on read enable line RDEN to request and stop data access, respectively.
  • one function of output FIFO 48 is to effect an immediate stop of output data upon read enable line RDEN going inactive. Referring to Figure 9, this is accomplished by strobe buffer 90 sensing the inactive state on read enable line RDEN, and immediately disabling output from register 94 in response; strobe buffer 90 also deasserts the valid data signal on line D_VAL, indicating that the data on lines RDDATA are no longer valid.
  • strobe buffer 90 forwards a signal to dual port FIFO 92 in response to the deasserted read strobe on read enable line RDEN. Dual port FIFO 92 then takes line FIFO_rden to an inactive state. To the extent that reads from SRAM array 45 remain scheduled at this time, those scheduled reads continue to be executed, with the results stored in dual-port FIFO 92. In this way, the cessation of external read requests, or read strobes, results in the immediate cessation of output data externally from FIFO memory 40, while permitting the remaining scheduled reads of SRAM array 45 to take place.
  • SRAM array 45 deasserts the control signal on line SRAM_rd_rdy upon its outputting of the EOP indicator for its last or only packet.
  • This signal is received by the downstream destination device, by way of the RD_RDY control line, in response to which this downstream external device stops sending read strobes on read enable line RDEN.
  • FIFO memory 40 includes the "read brake" function so that it can stop its operation at the desired point in time or state. If this were not the case, the start of the next packet could be undesirably read out, before the packet is ready for output, thus causing a loss of a packet.
  • control logic 47 makes a transition to read_brake state 80, and resets state variable sending_pkt. Control logic 47 remains in read_brake state 80, even if a read of the SOP for the next packet is later requested (in which case state variable sending_pkt is set).
  • control logic 47 Upon the write of the EOP for that next packet (write_eop), and if the packet has not been sent yet (sending_pkt is clear), control logic 47 transitions to one_pkt_rdy state 74, and increments the packet count state variable #pkt. If the new packet, for which the SOP has been written, is a jumbo packet such that its length exceeds the cut through threshold (pass_cut_thru_Th is set), control logic 47 passes to cut_thru state 78, for processing of the jumbo packet.
  • output FIFO 48 includes threshold logic for generating its ready signal RD_RDY to the downstream function, and also to control the flow of data from SRAM array 45 into output FIFO 48.
  • threshold logic for generating its ready signal RD_RDY to the downstream function, and also to control the flow of data from SRAM array 45 into output FIFO 48.
  • a preferred example of the thresholds according to which this threshold logic operates is schematically illustrated in Figure 10, in which output FIFO 48 is operated according to three thresholds. If output FIFO 48 is filled beyond threshold FIFO_ready, which is near the midpoint of the capacity of output FIFO 48, the downstream data destination receives a signal indicating that FIFO memory 40 can now be read. A second threshold stop_read is higher than threshold FIFO_ready. When the filled capacity of output FIFO 48 exceeds this threshold stop_read, reads of SRAM array 45 are stopped, to avoid overflow of output FIFO 48.
  • an extremely cost-efficient FIFO memory is provided.
  • the inventive FIFO memory appears, to its external functions, as a dual-port memory, capable of receiving asynchronous writes and reads.
  • the FIFO memory according to this invention can be realized by way of conventional single-port memory cells, thus enabling the fabrication of an extremely large FIFO memory with dual-port functionality, well beyond the size of such a dual-port FIFO that can be feasibly implemented and integrated according to modern technology.
  • the size of the dual-port FIFO constructed according to this invention is especially beneficial in the network communications context, particularly in high data rate networks such as 10 Gbit Ethernet.
  • the buffer function provided by the FIFO according to this invention permits the separation of network nodes by as much as on the order of kilometers, enabling the realization of extremely high data rate networks in the Metro context while providing an efficient and simple way to accomplish lossless flow control.
  • the dual-port FIFO includes packet management functionality, so that packet communications can be readily carried out at network nodes that implement this device.
  • the memory circuit as set forth, wherein the sequential logic also controls the write buffer to then store a third input data word in a buffer storage location of the second column responsive to the inputs receiving the third input data word prior to an internal write cycle.
  • the read buffer comprises:
  • the read buffer comprises:
EP04102921A 2003-06-23 2004-06-23 Dual-Port-Funktionalität für einen Single-Port-Speicher Expired - Fee Related EP1491995B1 (de)

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DE602004022614D1 (de) 2009-10-01
EP1491995B1 (de) 2009-08-19
US20110276731A1 (en) 2011-11-10
US20040257856A1 (en) 2004-12-23
EP1491995A3 (de) 2006-03-29

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