EP1488531A1 - Verfahren zur decodierung einer mit hilfe eines binären faltungscodes verschlüsselten datenfolge - Google Patents
Verfahren zur decodierung einer mit hilfe eines binären faltungscodes verschlüsselten datenfolgeInfo
- Publication number
- EP1488531A1 EP1488531A1 EP03744712A EP03744712A EP1488531A1 EP 1488531 A1 EP1488531 A1 EP 1488531A1 EP 03744712 A EP03744712 A EP 03744712A EP 03744712 A EP03744712 A EP 03744712A EP 1488531 A1 EP1488531 A1 EP 1488531A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- trellis
- metric values
- decoding
- values
- metric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
- H04L1/006—Trellis-coded modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3972—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using sliding window techniques or parallel windows
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0055—MAP-decoding
Definitions
- the present invention relates to a process for Decodie ⁇ tion of an encrypted using a binary convolutional code data sequence from K information bits using a Max LogMAP algorithm.
- the basic MAP algorithm is described, for example, in the publication "Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate, L.R. Bahl et al. , IEEE Transactions on Information Theory, pp. 284-287, March 1974, the MaxLogMAP algorithm can be described in the document “Iterative Decoding of Binary Block and Convolutional Codes *, J. Hagenauer et al. , IEEE Transactions on Information Theory, vol. 42, no. 2, pp. 429-445, March 1996.
- the binary trellis diagram serves as the basis for decoding a data sequence encrypted with the aid of a binary convolutional code.
- a segment of the trellis diagram belonging to an information bit of the data sequence captures all possible combinations of m (memory length of the convolutional code) preceding information bits as 2 m initial states.
- all resulting “conversions * (encodings) of the information bit are recorded as 2 lm + 1) state transitions and resulting 2 m target states as initial states for the next subsequent information bit.
- An information bit sequence corresponds to a specific path within the trellis diagram, with the MaxLogMAP algorithm being used to determine a sequence of the most likely information bits in the trellis diagram.
- the Window MaxLogMAP algorithm is generally used for decoding.
- Decoding results (soft output values), which are obtained in comparison with a MaxLogMAP algorithm without a decoding window, are more accurate, but this requires a great deal of hardware and memory.
- MaxLogMAP An alternative to the MaxLogMAP algorithm is based on a block error rate for a given signal-to-noise
- the object of the present invention is to carry out a decoding of a data sequence encrypted with the aid of a binary convolutional code by means of the MaxLogMAP algorithm in such a way that with low hardware expenditure, precise
- Soft output values are formed as decoding results.
- the method according to the invention is one of the processor-oriented implementations of the MaxLogMAP algorithm.
- ASIC user-specific module
- the metric values are calculated productively in a first calculation run and reproductively in further calculation runs based on the stored reference points.
- the method according to the invention saves storage space and thus area on an ASIC module.
- the space saved is thus available for further signal processing algorithms, which means that additional algorithms can be implemented in the ASIC module.
- the MaxLogMAP algorithm is used to decode a data sequence encoded using a binary convolutional code from K information bits.
- alfa metric values M ⁇ -calc-store for each individual trellis segment TSN starting with a trellis segment T1 are calculated and stored as logarithmic transition probabilities.
- beta metric values Mß-calc-store for each individual trellis segment TSN are calculated and stored starting at a trellis segment T2.
- the two calculations take place on a trellis segment TSM, from which point on a decision process for calculating a soft output value is carried out, ie the decoding of an information bit of the data sequence takes place.
- a “forward decision process * FDP carried out in the forward direction after passing the trellis segment TSM, currently calculated alfa metric values are obtained M ⁇ -calc with the previously calculated and stored beta metric values Mß-calc-store used to calculate the soft output value.
- This process takes place at the same time in a backward decision process * BDP, in which the currently calculated beta metric values Mß-calc are used with the previously calculated and stored Alfa metric values M ⁇ -calc-store to calculate the soft output value.
- K information bit number, s state of a convolutional code decoding, code memory length, T required number of trellis segments, with T K + m, and ⁇ length of a transient phase, with ⁇ > 5 * m
- Metric processors and a total of 2 -K / 2 - w - 2 m memory spaces required.
- the above-mentioned parameter t segmen t is dependent on the module technology (ASIC) used to implement the algorithm, on the memory architecture and on the clock rate used in the ASIC module.
- ASIC module technology
- the respective calculation of the metric values begins with the assumption of an uneven probability distribution in a trellis segment with a start state value (“initial state”), which has a probability of 100%, while all further “states * have a probability of Have 0%.
- FIG. 2 shows a basic illustration of a window MaxLogMAP algorithm for calculating soft output values according to the prior art.
- the Window-MaxLogMAP algorithm which is implemented with the help of a sliding decoding window, is used for long data sequences.
- a particular advantage of the Window MaxLogMAP algorithm is its efficient implementation.
- alpha metric values M ⁇ -calc are calculated exactly starting in the forward direction with a trellis segment Tl.
- beta metric values Mß-calc-1 of a first decoding window DPI or beta metric values Mß-calc-2 of a second decoding window DP2 are estimated.
- Metric values M ⁇ -pre, Mß-pre-1 and Mß-pre-2 are in turn assigned to a settling phase.
- Metrics are stored, w the size of the decoding window in trellis segments, and ⁇ e ⁇ , l ⁇ a parameter that depends on the chip technology (ASIC) used to implement the algorithm, on the memory architecture and on the ASIC Block rate used is.
- ASIC chip technology
- the storage takes place within a memory cascaded in levels.
- the calculated metric values M ⁇ -calc (l) or Mß-calc (l) of the first pass for a selection of K / ⁇ (l) trellis segments which serve as support points are now metric values M ⁇ -calc -sel (1) or Mß-calc- sel (l) of the first pass are each stored in a first storage level SP (1) with a storage depth of ⁇ (l).
- metric values M ⁇ -calc (2) or Mß-calc (2) of those trellis segments TSN which are arranged between the respective support points of the first run are again calculated.
- M ⁇ -calc-sel (2) or Mß-calc-sel (2) of the second pass are stored in a second storage level SP (2) with a storage depth of ⁇ (2).
- This metric value calculation based on the support points of a previous run is accordingly both continued in the forward and backward directions.
- Corresponding soft output values are formed after passing through the TSM trellis segment, with memory levels that are freed up being used accordingly.
- the decision process for determining the soft output values takes place as described in FIG. 1.
- the individual storage levels are cascaded.
- n After n passes, all soft output values are determined, the nth memory level having a memory depth of ⁇ (n) with stored metric values of K / ⁇ (1) / ⁇ (2) / .... / ⁇ (n) trellis segments or Has support points.
- the hardware outlay in the memory-cascaded implementation according to the invention is reduced by more than 80% compared to the conventional implementation described in FIG.
- a metric processor including scaling of the register bits: t rH M '/ parallel + ⁇ ⁇ ⁇ W ⁇ ü fll ⁇ op
- a V iterbi represent the Viterbi arithmetic for a given word width w and a flip-flop the register area unit per bit
- the units correspond to a gate equivalent of 0.18 ⁇ m ASIC technology at a clock frequency of around 150 MHz.
- MaxLogMAP decoder With UMTS (W-CDMA) and UTRAN TDD Turbo Codes, a MaxLogMAP decoder with minor extensions can be considered as part of the turbo decoding.
- the memory cascaded implementation can be compared with the direct and the window implementation:
- these metric values are read out from the memory levels SP ( ⁇ l) or SP ( ⁇ 1) and the associated alpha metric values or beta metric values are calculated exactly from the trellis segments arranged between the support points. Again, a corresponding selection of trellis segments is made as support points and the associated metric values are stored.
- Two memory levels SP ( ⁇ 2) and SP ( ⁇ 2 ') or SP (ß2) and SP (ß2') are given here as examples.
- a third pass D3 the trellis segment TSM is reached from both sides and 2 m beta metric values currently calculated for the “backward decision process *” with stored 2 m Alfa metric values are stored in the memory SP ( ⁇ 2). are used to determine soft output values. Likewise, 2 m alpha metric values currently calculated for the “forward decision process *” with stored 2 m beta metric values, which are stored in the memory SP ( ⁇ 2), are used to determine soft output values.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03744712A EP1488531A1 (de) | 2002-03-27 | 2003-03-20 | Verfahren zur decodierung einer mit hilfe eines binären faltungscodes verschlüsselten datenfolge |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02007030 | 2002-03-27 | ||
EP02007030A EP1349286A1 (de) | 2002-03-27 | 2002-03-27 | Verfahren zur Decodierung einer mit Hilfe eines binären Faltungscodes verschlüsselten Datenfolge |
DE10213882 | 2002-03-27 | ||
DE2002113882 DE10213882B4 (de) | 2002-03-27 | 2002-03-27 | Verfahren zur Decodierung einer mit Hilfe eines binären Faltungscodes verschlüsselten Datenfolge |
PCT/EP2003/002942 WO2003081786A1 (de) | 2002-03-27 | 2003-03-20 | Verfahren zur decodierung einer mit hilfe eines binären faltungscodes verschlüsselten datenfolge |
EP03744712A EP1488531A1 (de) | 2002-03-27 | 2003-03-20 | Verfahren zur decodierung einer mit hilfe eines binären faltungscodes verschlüsselten datenfolge |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1488531A1 true EP1488531A1 (de) | 2004-12-22 |
Family
ID=28455549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03744712A Withdrawn EP1488531A1 (de) | 2002-03-27 | 2003-03-20 | Verfahren zur decodierung einer mit hilfe eines binären faltungscodes verschlüsselten datenfolge |
Country Status (6)
Country | Link |
---|---|
US (1) | US7143334B2 (de) |
EP (1) | EP1488531A1 (de) |
KR (1) | KR100973097B1 (de) |
CN (1) | CN1643798A (de) |
AU (1) | AU2003215670A1 (de) |
WO (1) | WO2003081786A1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100706608B1 (ko) * | 2005-07-19 | 2007-04-13 | 한국전자통신연구원 | 이중 스트림 전송에 적합한 부호기 추정 방법 및 이를이용한 부호화 장치 |
US7895497B2 (en) * | 2006-06-26 | 2011-02-22 | Samsung Electronics Co., Ltd. | Apparatus and method using reduced memory for channel decoding in a software-defined radio system |
CN110110283A (zh) * | 2018-02-01 | 2019-08-09 | 北京中科晶上科技股份有限公司 | 一种卷积计算方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3910739C3 (de) * | 1989-04-03 | 1996-11-21 | Deutsche Forsch Luft Raumfahrt | Verfahren zum Verallgemeinern des Viterbi-Algorithmus und Einrichtungen zur Durchführung des Verfahrens |
DE4224214C2 (de) * | 1992-07-22 | 1995-02-09 | Deutsche Forsch Luft Raumfahrt | Verfahren zur quellengesteuerten Kanaldecodierung durch Erweiterung des Viterbi-Algorithmus |
DE4437984A1 (de) | 1994-10-25 | 1996-08-14 | Philips Patentverwaltung | Übertragungssystem mit Soft-Output-Dekodierung |
US6028899A (en) | 1995-10-24 | 2000-02-22 | U.S. Philips Corporation | Soft-output decoding transmission system with reduced memory requirement |
US6226773B1 (en) * | 1999-10-20 | 2001-05-01 | At&T Corp. | Memory-minimized architecture for implementing map decoding |
FR2802371B1 (fr) * | 1999-12-10 | 2003-09-26 | Matra Nortel Communications | Procede de signalisation dans un systeme de radiocommunication, emetteurs, recepteurs et repeteurs pour la mise en oeuvre du procede |
US6654927B1 (en) * | 2000-01-10 | 2003-11-25 | Lg Electronics Inc. | Iterative error-correction for turbo code decoding |
US6901117B1 (en) * | 2000-02-10 | 2005-05-31 | Motorola, Inc. | Soft output decoder for convolutional codes |
EP1128560B1 (de) * | 2000-02-21 | 2004-01-28 | Motorola, Inc. | Vorrichtung und Verfahren zur SISO Dekodierung |
US20020034261A1 (en) * | 2000-06-23 | 2002-03-21 | Eidson Donald Brian | Rate n/n systematic, recursive convolutional encoder and corresponding decoder |
FI109162B (fi) * | 2000-06-30 | 2002-05-31 | Nokia Corp | Menetelmä ja järjestely konvoluutiokoodatun koodisanan dekoodaamiseksi |
US6829313B1 (en) * | 2000-07-17 | 2004-12-07 | Motorola, Inc. | Sliding window turbo decoder |
US6813743B1 (en) * | 2000-07-31 | 2004-11-02 | Conexant Systems, Inc. | Sliding window technique for map decoders |
US6452979B1 (en) * | 2000-09-06 | 2002-09-17 | Motorola, Inc. | Soft output decoder for convolutional codes |
FI20010147A (fi) * | 2001-01-24 | 2002-07-25 | Nokia Corp | Menetelmä ja järjestely konvoluutiokoodatun koodisanan dekoodaamiseksi |
JP4198904B2 (ja) * | 2001-06-11 | 2008-12-17 | 富士通株式会社 | 記録再生装置、信号復号回路、エラー訂正方法、及び反復型復号器 |
KR100436434B1 (ko) * | 2001-11-19 | 2004-06-16 | 한국전자통신연구원 | 상태 메트릭을 갖는 터보 복호기 및 그를 이용한 계산 방법 |
-
2003
- 2003-03-20 KR KR1020047015128A patent/KR100973097B1/ko not_active IP Right Cessation
- 2003-03-20 WO PCT/EP2003/002942 patent/WO2003081786A1/de not_active Application Discontinuation
- 2003-03-20 CN CNA03806880XA patent/CN1643798A/zh active Pending
- 2003-03-20 AU AU2003215670A patent/AU2003215670A1/en not_active Abandoned
- 2003-03-20 EP EP03744712A patent/EP1488531A1/de not_active Withdrawn
- 2003-03-20 US US10/509,038 patent/US7143334B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
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See references of WO03081786A1 * |
Also Published As
Publication number | Publication date |
---|---|
KR20040099360A (ko) | 2004-11-26 |
US20050166128A1 (en) | 2005-07-28 |
US7143334B2 (en) | 2006-11-28 |
AU2003215670A1 (en) | 2003-10-08 |
WO2003081786A1 (de) | 2003-10-02 |
CN1643798A (zh) | 2005-07-20 |
KR100973097B1 (ko) | 2010-07-29 |
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