EP1484740A2 - Dispositif et méthode de commande d'une source de lumière dans des appareils d'affichage avec génération améliorée de signal de référence - Google Patents

Dispositif et méthode de commande d'une source de lumière dans des appareils d'affichage avec génération améliorée de signal de référence Download PDF

Info

Publication number
EP1484740A2
EP1484740A2 EP04005862A EP04005862A EP1484740A2 EP 1484740 A2 EP1484740 A2 EP 1484740A2 EP 04005862 A EP04005862 A EP 04005862A EP 04005862 A EP04005862 A EP 04005862A EP 1484740 A2 EP1484740 A2 EP 1484740A2
Authority
EP
European Patent Office
Prior art keywords
signal
frequency
generate
horizontal synchronization
reference signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP04005862A
Other languages
German (de)
English (en)
Other versions
EP1484740B1 (fr
EP1484740A3 (fr
Inventor
Hyeon-Yong Jang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of EP1484740A2 publication Critical patent/EP1484740A2/fr
Publication of EP1484740A3 publication Critical patent/EP1484740A3/fr
Application granted granted Critical
Publication of EP1484740B1 publication Critical patent/EP1484740B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0606—Manual adjustment
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to devices for displaying images, and more particularly, to a device and a method of driving a light source for image display devices.
  • Display devices such as computer monitors, television sets, etc., generally include self-emitting display devices employing light emitting diodes (LEDs), electroluminescences (ELs), vacuum fluorescent display (VFD), field emission display (FED) and plasma panel display (PDP), and non-emitting display devices employing liquid crystal display (LCD) which necessitates a light source.
  • LEDs light emitting diodes
  • ELs electroluminescences
  • VFD vacuum fluorescent display
  • FED field emission display
  • PDP plasma panel display
  • LCD liquid crystal display
  • LCD devices are generally equipped with two panels each having a field-generating electrode and a liquid crystal (LC) layer with dielectric anisotropy.
  • the LC layer is interposed between the two panels.
  • the field-generating electrodes are each supplied with an electric voltage to generate electric fields across the liquid crystal layer.
  • the light transmittance of the LC layer varies in association with the strength of the electric fields which is controlled by the applied voltage. Accordingly, desired images are displayed by adjusting the applied voltage.
  • the light for an LCD device is provided by a light source equipped within the LCD device or may be the natural light.
  • the brightness on a screen of the LCD device is usually adjusted by regulating the ratio of on- and off-time of the light source or regulating the current flowing the light source.
  • fluorescent lamps are usually used as a light source for the LCD devices.
  • the fluorescent lamps generally require a high AC voltage of which magnitude is typically in the range of several kilovolts and frequency in the range of dozens of kilohertz.
  • the current flowing such fluorescent lamps has a magnitude of several milli-amperes. Since the lamps are disposed at the rear side of an LCD panel and close to the panel at a distance of several millimeters, electric fields and magnetic fields from the lamps make noise to signals in wires and thin film transistors (TFTs) of the LCD panel. In particular, since the frequency of a driving signal for the lamps and the frequency of a horizontal synchronization signal for the LCD panel are similar to each other but a slight difference, a beating occurs to cause interference which makes horizontal stripes, called waterfall, on the LCD screen.
  • TFTs thin film transistors
  • a triangular pulse width modulation (PWM) reference signal having a frequency lower than the frequency of the horizontal synchronization signal is generated and the reference signal is dropped to a bottom level at the time of synchronization by using short pulses to be initiated.
  • PWM pulse width modulation
  • the triangular reference wave is generated to have rising portions and falling portions which are asymmetric to each other. As a result, are caused several problems such as reduced lifetime and unstable ignition of the lamps.
  • a device for driving a light source of an image display device comprises input terminals to receive a horizontal synchronization signal and a control signal externally provided, an oscillator to generate a reference signal having a frequency, a controller to modulate the reference signal in response to the control signal and output a modulated signal, and a phase difference detecting unit to receive the horizontal synchronization signal and the modulated signal and detect a phase difference between the horizontal synchronization signal and the modulated signal to generate an output signal indicating the phase difference, wherein the oscillator adjusts the frequency of the reference signal in response to the output signal of the phase difference detecting unit so that the horizontal synchronization signal and the reference signal are synchronized with each other.
  • the control signal externally provided includes a signal to control luminance on a screen of the image display device.
  • the phase difference detecting unit may include a phase comparator to compare phases of the horizontal synchronization signal and the modulated signal and generate an output signal of which value is determined based on the comparison, and an integrator to generate a voltage signal having a magnitude proportional to an integration of the output signal of the phase comparator.
  • the integrator may include a voltage divider having resistors connected between a supply voltage and ground, an operational amplifier having an inverting terminal to receive the output signal of the phase comparator and a non-inverting terminal connected to the voltage divider, a capacitor connected between the inverting terminal and an output terminal of the operational amplifier, and a reset unit to initiate the integrator in response to an externally provided instruction signal by discharging the capacitor in the integrator.
  • the light source drive device may also include a frequency divider to divide a frequency of the modulated signal provided from the controller to generate a frequency-divided signal.
  • the light source drive device may further include a low pass filter connected between the phase comparator and the integrator, in which the low pass filter filters out high frequency components of the output signal of the phase comparator.
  • the light source drive device may also include a switch circuit to receive the modulated signal from the controller and generate a switch signal having on and off levels by switching a supply voltage in accordance with the modulated signal, and a transformer to receive the switch signal from the switch circuit and generate a sinusoidal signal which is applied to the light source.
  • a method of driving a light source in an image display device comprising the steps of generating a reference signal having a frequency, detecting a phase difference between a horizontal synchronization signal for the image display device and the reference signal to generate a detect signal, adjusting the frequency of the reference signal in response to the detect signal, and providing a driving signal to the light source in response to the adjusted reference signal.
  • the detecting step may include comparing the horizontal synchronization signal and the reference signal, integrating a result signal obtained from the comparing step to generate an integrated voltage signal as the detect signal, and resetting the integrating step such that the integrated voltage signal returns to an initial status.
  • the method may further include performing pulse width modulation with respect to the reference signal to generate a modulated signal, and dividing a frequency of the modulated signal to generate a frequency-divided signal, in which the detect signal is obtained by detecting the phase difference between the horizontal synchronization signal and the frequency-divided signal.
  • Fig. 1 is an exploded perspective view of an image display device according to an embodiment of the present invention
  • Fig. 2 is a block diagram illustrating a part of the image display device of the present invention
  • Fig. 3 is an equivalent circuit diagram of a pixel of the image display device according to an embodiment of the present invention.
  • the image display device such as a liquid crystal display (LCD) device
  • the image display device includes a display module 350 including a display unit 330, a backlight unit 340, a pair of front and rear cases 361 and 362, a chassis 363, and a mold frame 364 containing and fixing the display module 350.
  • LCD liquid crystal display
  • the display unit 330 includes a display panel assembly 300, gate tape carrier packages (TCPs) or chip-on-film (COF) type packages 510 mounting gate driving ICs and data TCPs 410 attached to the display panel assembly 300, and a gate printed circuit board (PCB) 550 and a data PCB 450 attached to the gate and data TCPs 510 and 410, respectively.
  • TCPs gate tape carrier packages
  • COF chip-on-film
  • the backlight unit 340 includes lamps 341 disposed behind the display panel assembly 300, a spread plate 342 and optical sheets 343 disposed between the panel assembly 300 and the lamps 341.
  • the spread plate 342 guides and diffuses light from the lamps 341 to the panel assembly 300.
  • the backlight unit also includes a reflector 344 disposed under the lamps 341 and reflecting the light from the lamps 341 toward the panel assembly 300.
  • the lamps 341 are, for example, fluorescent lamps such as CCFL (cold cathode fluorescent lamp) and EEFL (external electrode fluorescent lamp) or LED lamps.
  • the display device of the present invention also includes a gate driver 400 and a data driver 500 which are connected to the display panel assembly 300, a gray voltage generator 800 connected to the data driver 500, a lighting unit 900 for illuminating the panel assembly 300, and a signal controller 600 controlling the above elements.
  • the display panel assembly 300 includes a lower panel 100, an upper panel 200 and a liquid crystal (LC) layer 3 interposed therebetween (referring to Fig. 3).
  • the display panel assembly 300 includes display signal lines G 1 -G n and D 1 -D m and pixels which are connected to the display signal lines G 1 -G n and D 1 -D m and arranged in a matrix form.
  • the display signal lines G 1 -G n and D 1 -D m are disposed on the lower panel 100 and include gate lines G 1 -G n transmitting gate signals (called scanning signals) and data lines D 1 -D m transmitting data signals.
  • the gate lines G 1 -G n are arranged in a row direction and substantially parallel to each other, and the data lines D 1 -D m are arranged in a column direction and substantially parallel to each other.
  • Each pixel of the display device includes a switching element Q connected to the display signal lines G 1 -G n and D 1 -D m , and capacitors C LC and C ST that are connected to the switching element Q.
  • Capacitor C LC is, for example, a liquid crystal (LC) capacitor formed between the lower and upper panels 100 and 200.
  • the storage capacitor C ST may be omitted.
  • the switching element Q is implemented with, for example, a thin film transistor and disposed on the lower panel 100.
  • the switching element Q has three terminals: a control terminal connected to one of the gate lines G 1 -G n , an input terminal connected to one of the data lines D 1 -D m , and an output terminal connected to the LC capacitor C LC and the storage capacitor C ST .
  • the LC capacitor C LC includes a pixel electrode 190 on the lower panel 100, a common electrode 270 on the upper panel 200, and the LC layer 3 as a dielectric between the electrodes 190 and 270.
  • the pixel electrode 190 is connected to the switching element Q, and the common electrode 270 covers the entire surface of the upper panel 100 and is supplied with a common voltage Vcom.
  • both the pixel electrode 190 and the common electrode 270 which have shapes of bars or stripes, are disposed on the lower panel 100.
  • the storage capacitor C ST is an auxiliary capacitor for the LC capacitor C LC .
  • the storage capacitor C ST includes the pixel electrode 190 and a separate signal line (not shown) disposed on the lower panel 100.
  • An insulator (not shown) is disposed between the separate signal line and the pixel electrode 190, and the separate signal line is supplied with a predetermined voltage such as the common voltage Vcom.
  • the storage capacitor C ST may include in another embodiment the pixel electrode 190 and an adjacent gate line (or a previous gate line), in which an insulator is disposed between the adjacent gate line and the pixel electrode 190.
  • each pixel uniquely represents one of three primary colors (i.e., spatial division) or each pixel represents three primary colors in turn (i.e., time division) such that spatial or temporal sum of the three primary colors are recognized as a desired color.
  • Fig. 3 shows an example of the spatial division that each pixel is provided with a color filter 230, one of red, green and blue color filters, in an area of the upper panel 200 facing the pixel electrode 190.
  • the color filter 230 is provided on or under the pixel electrode 190 on the lower panel 100.
  • the lighting unit 900 includes a lamp unit 910 having the lamps 341 shown in Fig. 1 and an inverter 920 connected to the lamp unit 910.
  • the inverter 920 turns on and off the lamp unit 910 and controls the timing of on-time and off-time of the lamp unit to adjust luminance of a display screen.
  • the inverter 920 may be mounted on a stand-alone inverter PCB (not shown) or mounted on the gate PCB 550 or the data PCB 450. A detailed configuration of the inverter 920 will be described.
  • a pair of polarizers (not shown) polarizing the light from the lamps 341 are attached on the outer surfaces of the panels 100 and 200 of the panel assembly 300.
  • the gray voltage generator 800 is disposed on the data PCB 450.
  • the gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixels.
  • the gray voltages in one set have a positive polarity with respect to the common voltage Vcom, and those in the other set have a negative polarity with respect to the common voltage Vcom.
  • the gate driver 400 includes integrated circuit (IC) chips mounted on the respective gate TCPs 510.
  • the gate driver 400 is connected to the gate lines G 1 -G n of the panel assembly 300 and synthesizes the gate-on voltage Von and the gate-off voltage Voff from an external device to generate gate signals for application to the gate lines G 1 -G n .
  • the data driver 500 includes IC chips mounted on the respective data TCPs 410.
  • the data driver 500 is connected to the data lines D 1 -D m of the panel assembly 300 and applies data voltages selected from the gray voltages supplied from the gray voltage generator 800 to the data lines D 1 -D m .
  • the IC chips of the gate driver 400 and/or the data driver 500 are mounted on the lower panel 100.
  • one or both of the drivers 400 and 500 are incorporated along with other elements into the lower panel 100.
  • the gate PCB 550 and/or the gate TCPs 510 may be omitted in such embodiments.
  • the signal controller 600 controlling the drivers 400 and 500, etc. is disposed on the data PCB 450 or the gate PCB 550.
  • the signal controller 600 is supplied with RGB image signals R, G and B and input control signals controlling the display thereof such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, and a data enable signal DE, from an external graphics controller (not shown).
  • the signal controller 600 After generating gate control signals CONT1 and data control signals CONT2 and processing the image signals R, G and B suitable for the operation of the panel assembly 300 on the basis of the input control signals and the input image signals R, G and B, the signal controller 600 provides the gate control signals CONT1 for the gate driver 400, and the processed image signals R', G' and B' and the data control signals CONT2 for the data driver 500.
  • the gate control signals CONT1 include a vertical synchronization start signal STV for informing of start of a frame, a gate clock signal CPV for controlling the output time of the gate-on voltage Von, and an output enable signal OE for defining the duration of the gate-on voltage Von.
  • the data control signals CONT2 include a horizontal synchronization start signal STH for informing of start of a horizontal period, a load signal LOAD or TP for instructing to apply the appropriate data voltages to the data lines D 1 -D m , an inversion control signal RVS for reversing the polarity of the data voltages (with respect to the common voltage Vcom), and a data clock signal HCLK.
  • the data driver 500 receives a packet of the image data R', G' and B' for a pixel row from the signal controller 600 and converts the image data R', G' and B' into the analog data voltages selected from the gray voltages supplied from the gray voltage generator 800 in response to the data control signals CONT2 from the signal controller 600.
  • the gate driver 400 applies the gate-on voltage Von to selected one(s) of the gate lines G 1 -G n , thereby turning on the switching elements Q connected thereto.
  • the data driver 500 applies the data voltages to the corresponding data lines D 1 -D m for an on-time of the switching elements Q (which is called “one horizontal period” or “1H” and equals to one period of the horizontal synchronization signal Hsync, the data enable signal DE, and the gate clock signal CPV). Then, the data voltages in turn are supplied to the corresponding pixels via the turned-on switching elements Q.
  • the difference between the data voltage and the common voltage Vcom applied to a pixel is expressed as a charged voltage of the LC capacitor C LC , i.e., a pixel voltage.
  • the liquid crystal molecules have orientations depending on the magnitude of the pixel voltage and the orientations determine the polarization of light passing through the LC capacitor C LC .
  • the polarizers convert the light polarization into the light transmittance.
  • the inversion control signal RVS applied to the data driver 500 is controlled such that the polarity of the data voltages is reversed (which is called “frame inversion”).
  • the inversion control signal RVS may be also controlled such that the polarity of the data voltages flowing in a data line in one frame are reversed (which is called “line inversion”), or the polarity of the data voltages in one packet are reversed (which is called “dot inversion").
  • the inverter 920 drives the lamp unit 910 based on a luminance control signal Vdim, the horizontal synchronization signal Hsync, and an instruction signal EN for turning on and off the lamp unit 910.
  • the inverter 920 includes a transformer (TRANS) 921, a switch circuit (SW) 922, a controller (CTN) 930, an oscillator (OSC) 940, and a phase difference detecting circuit 950, which are connected in series from the lamp unit 910.
  • TRANS transformer
  • SW switch circuit
  • CTN controller
  • OSC oscillator
  • phase difference detecting circuit 950 phase difference detecting circuit 950
  • the phase difference detecting circuit 950 includes a phase comparator 951, a low pass filter (LPF) 952, a proportional integrator 953, a reset unit 954, and a frequency divider 955.
  • the phase comparator 951 receives the horizontal synchronization signal Hsync and an output from the frequency divider 955 and outputs logic '0' when the inputs have different logic values and outputs logic '1' the inputs have a same logic value.
  • the phase comparator 951 is implemented with an XNOR gate.
  • the XNOR gate can be substituted with an XOR gate.
  • the low pass filter 952 includes two resistors R1 and a capacitor C 1 connected in series between the phase comparator 951 and the ground, and passes low frequency components of an input signal by filtering out high frequency components of the input signal.
  • the proportional integrator 953 includes an operational amplifier OP having a negative feedback through an integration capacitor C2 and a resistor R5 connected in series and receiving an output of the low pass filter 952 at its inverting terminal (-).
  • the operational amplifier OP has a non-inverting terminal (+) connected to a voltage divider including a pair of resistors R3 and R4 connected in series between a supply voltage VDDA and the ground.
  • the operational amplifier OP is biased with the supply voltage VDDA and the ground.
  • the proportional integrator 953 outputs a voltage having a magnitude proportional to a temporal integration of the output of the low pass filter 952.
  • the reset unit 954 includes a switching element Q 1 connected with the proportional integrator 953 and a differentiation circuit including a resistor R6 and a capacitor C3 connected in series between a control terminal of the switching element Q 1 and an input terminal receiving the instruction signal EN.
  • the reset unit 954 initiates the proportional integrator 953 by discharging the charges stored in the integration capacitor C2.
  • the switching element Q 1 is implemented with an NPN bipolar transistor in this embodiment, a PNP bipolar transistor or a MOS transistor is also used as the switching element Q1. It is apparent to those skill in the art that some design modifications such as inversion of the value of the instruction signal EN are required when using the PNP transistor or a P-channel MOS transistor.
  • the frequency divider 955 divides the frequency of the output signal of the controller 930 and outputs the frequency-divided signal to the phase comparator 951.
  • the frequency divider 955 employs a T-flipflop that makes the frequency of a signal inputted into a clock terminal become half.
  • the frequency divider may be omitted when the frequency is maintained same.
  • Fig. 5 shows waveforms of output voltages of the parts in Fig. 4 and a lamp current provided to the lamp unit.
  • the oscillator 940 When the dimming control signal Vdim and the instruction signal EN are received, the oscillator 940 generates a reference signal OSC having a triangular waveform or a saw-toothed waveform for pulse width modulation (PWM).
  • the controller 930 pulse-width-modulates the reference signal OSC by using a predetermined reference voltage and supplies a PWM signal to the switch circuit 922.
  • An exemplary frequency of the reference signal OSC is twice the frequency of the horizontal synchronization signal Hsync.
  • the switch circuit 922 generates a signal SW having on and off levels by switching the DC supply voltage according to the PWM signal as shown in Fig. 5.
  • the transformer 921 generates a sinusoidal signal based on the on/off signal SW and transforms the sinusoidal signal to have a high voltage.
  • the sinusoidal signal generated from the transformer 921 is provided to the lamp unit 910 as the lamp current LDS which turns on the lamps of the lamp unit 910.
  • the sinusoidal signal output from the transformer 921 has amplitudes 'a' and 'b' in positive and negative polarities, respectively, which have a substantially same value.
  • the differentiator C3 and R6 of the reset unit 954 flows a temporary current upon the input of the instruction signal EN to turn on the switching element Q 1 for a few microseconds. Then, the charge stored in the integration capacitor C2 of the proportional integrator 953 is discharged and the proportional integrator 953 is initiated.
  • the PWM signal of the controller 930 is input to the frequency divider 955, where the frequency of the PWM signal is divided.
  • the frequency-divided signal is then input to the phase comparator 951.
  • the phase comparator 951 outputs logic '1' when the value of the horizontal synchronization signal Hsync is equal to the output signal of the frequency divider 955.
  • the phase comparator 951 also outputs logic '0' when the input signals have different values. Therefore, the output of the phase comparator 951 has a longer duration of logic '1' as the phases of the two input signals coincide, and, on the contrary, it has a longer duration of logic '0' as the phases of the two signals are in discord.
  • the output of the phase comparator 951 indicates the identity and/or the difference between the phases of the two input signals as function of time.
  • the output signal of the phase comparator 951 passes through the low pass filter 952 where the high frequency components of the signal are removed, and is converted into an analog voltage which is charged into the integration capacitor C2 of the proportional integrator 953. Since the output voltage of the proportional integrator 953 is proportional to a temporal integration of the output of the phase comparator 951, it indicates the degree of the phase difference between the two input signals of the phase comparator 951. Since appropriate resistance ratio of the voltage divider R3 and R4 enables to integrate the difference from a desired value, the output voltage of the proportional integrator 953 indicates the difference between the phase difference of the two input signals and the desired value.
  • the oscillator 940 changes an oscillating frequency of the reference signal OSC based on the output voltage of the proportional integrator 953. That is, the oscillator 940 increases a low frequency of the reference signal OSC, while it reduces a high frequency of the reference signal OSC.
  • the controller 930 pulse-width-modulates and outputs the PWM signal having the changed frequency, and the output signal of the controller 930 is double frequency-divided and is returned to the phase comparator 951.
  • the horizontal synchronization signal Hsync and the output signal of the frequency divider 955 becomes synchronized by performing the above operation through the feedback loop. In other words, the phases of the horizontal synchronization signal Hsync and the output signal of the frequency divider 955 become coincident. As a result, the frequency of the reference signal OSC of the oscillator 940 becomes twice the frequency of the horizontal synchronization signal Hsync in case of employing the divider 955.
  • the reference signal OSC of the oscillator 940 has a frequency twice that of the horizontal synchronization signal Hsync, and thus the lamp current LDS to be provided to the lamp unit 910 has a symmetrical waveform. Accordingly, the lifetime reduction or unstable ignition of the lamp unit 910 due to asymmetrical current therein can be prevented.
  • the luminance of an LCD screen can be controlled by adjusting the ratio of the on-time and the off-time of the lamp unit 910 based on the dimming control signal Vdim, which is inputted from a separate input device adjustable by a user or from the signal controller 600.
  • the controller 930 turns on or off the lamp unit 910 in response to the instruction signal EN.
  • the controller 930 receives a voltage having a magnitude in proportion to the current in the lamp unit 910 and performs feedback control for the lamp unit 910.
  • the life time of the lamps is elongated and stable ignition of the lamps is obtained since the positive portions and the negative portions of current waves in the lamps are substantially equal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Circuit Arrangements For Discharge Lamps (AREA)
EP20040005862 2003-03-14 2004-03-12 Dispositif et méthode de commande d'une source de lumière dans des appareils d'affichage avec génération améliorée de signal de référence Expired - Fee Related EP1484740B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030016041A KR100920353B1 (ko) 2003-03-14 2003-03-14 표시 장치용 광원의 구동 장치
KR2003016041 2003-03-14

Publications (3)

Publication Number Publication Date
EP1484740A2 true EP1484740A2 (fr) 2004-12-08
EP1484740A3 EP1484740A3 (fr) 2006-05-03
EP1484740B1 EP1484740B1 (fr) 2015-05-06

Family

ID=32960229

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20040005862 Expired - Fee Related EP1484740B1 (fr) 2003-03-14 2004-03-12 Dispositif et méthode de commande d'une source de lumière dans des appareils d'affichage avec génération améliorée de signal de référence

Country Status (6)

Country Link
US (2) US7362303B2 (fr)
EP (1) EP1484740B1 (fr)
JP (1) JP4473013B2 (fr)
KR (1) KR100920353B1 (fr)
CN (1) CN1540608A (fr)
TW (1) TWI408667B (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007035861A3 (fr) * 2005-09-21 2007-07-19 Sorin Davidovici Systeme et procede permettant d'obtenir un element capteur ou une matrice de capteurs a gamme dynamique elevee
US7872681B2 (en) 2005-10-13 2011-01-18 Rjs Technology, Inc. System and method for a high performance color filter mosaic array
US20110140615A1 (en) * 2009-12-11 2011-06-16 Byung-Sam Min Apparatus and method of driving light source

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4206693B2 (ja) * 2002-05-17 2009-01-14 株式会社日立製作所 画像表示装置
KR100920353B1 (ko) * 2003-03-14 2009-10-07 삼성전자주식회사 표시 장치용 광원의 구동 장치
TWI291311B (en) * 2003-12-08 2007-12-11 Beyond Innovation Tech Co Ltd PWM illumination control circuit with low visual noise for LED
JP3968587B2 (ja) * 2004-03-30 2007-08-29 船井電機株式会社 液晶テレビジョン、バックライト制御装置およびバックライト制御方法
JP2005316298A (ja) * 2004-04-30 2005-11-10 Nec Lcd Technologies Ltd 液晶表示装置、該液晶表示装置に用いられる光源駆動回路及び光源駆動方法
US7262560B2 (en) * 2004-05-25 2007-08-28 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Regulating a light source using a light-to-frequency converter
US7477246B2 (en) * 2004-12-20 2009-01-13 Intel Corporation Synchronization of lamp stabilizing pulses with frame rates of PWM LCOS devices
KR100613088B1 (ko) * 2004-12-24 2006-08-16 삼성에스디아이 주식회사 데이터 집적회로 및 이를 이용한 발광 표시장치
KR100700846B1 (ko) * 2004-12-24 2007-03-27 삼성에스디아이 주식회사 데이터 집적회로 및 이를 이용한 발광 표시장치
KR101127848B1 (ko) * 2005-06-17 2012-03-21 엘지디스플레이 주식회사 백 라이트 유닛과 이를 이용한 액정 표시장치
KR100810516B1 (ko) * 2005-07-01 2008-03-10 삼성전자주식회사 부하 구동장치 및 그 부하 구동방법
US7746330B2 (en) * 2005-12-22 2010-06-29 Au Optronics Corporation Circuit and method for improving image quality of a liquid crystal display
EP1826741A3 (fr) * 2006-02-23 2012-02-15 Semiconductor Energy Laboratory Co., Ltd. Dispositif d'affichage et dispositif électronique doté de celui-ci
TWI355629B (en) * 2006-03-08 2012-01-01 Novatek Microelectronics Corp Liquid crystal display device capable of wsitching
KR20080003587A (ko) * 2006-07-03 2008-01-08 왕종민 발광다이오드 매트릭스 구동 장치
TWI346925B (en) * 2006-08-28 2011-08-11 Au Optronics Corp Display and apparatus and method for power saving thereof
TW200839677A (en) * 2007-03-21 2008-10-01 Hannstar Display Corp Preventing image being interfered method and apparatus thereof
DE102007033471B4 (de) * 2007-07-18 2011-09-22 Austriamicrosystems Ag Schaltungsanordnung und Verfahren zur Ansteuerung segmentierter LED-Hintergrundbeleuchtungen
US9390659B2 (en) 2007-07-18 2016-07-12 Ams Ag Circuit configuration and method for controlling particularly segmented LED background illumination
KR100910450B1 (ko) * 2007-08-27 2009-08-04 삼성전기주식회사 영상 신호와 동기화된 액정 표시 장치용 백라이트 유닛
JP5577570B2 (ja) * 2008-03-17 2014-08-27 セイコーエプソン株式会社 電気光学装置
US8022635B2 (en) * 2008-05-25 2011-09-20 Microsemi Corporation CCFL controller with multi-function terminal
KR100978668B1 (ko) * 2008-11-28 2010-08-30 삼성전기주식회사 디스플레이 구동 장치
CN101958109B (zh) * 2010-09-03 2012-09-26 华映视讯（吴江）有限公司 降低显示器画面波纹现象的方法
JP5796944B2 (ja) * 2010-10-04 2015-10-21 ラピスセミコンダクタ株式会社 表示パネル駆動装置
CN102034438B (zh) * 2010-10-15 2013-04-24 深圳市华星光电技术有限公司 显示装置的背光模块的驱动电路及驱动方法
DE102017122014A1 (de) * 2017-09-22 2019-03-28 Osram Opto Semiconductors Gmbh Anordnung zum Betreiben optoelektronischer Halbleiterchips und Anzeigevorrichtung

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4365204A (en) * 1980-09-08 1982-12-21 American Microsystems, Inc. Offset compensation for switched capacitor integrators
US5331253A (en) * 1992-08-24 1994-07-19 Usi Lighting, Inc. Electronic ballast for gaseous discharge lamp operation
US5844540A (en) * 1994-05-31 1998-12-01 Sharp Kabushiki Kaisha Liquid crystal display with back-light control function
US6127865A (en) * 1997-05-23 2000-10-03 Altera Corporation Programmable logic device with logic signal delay compensated clock network
US6246183B1 (en) * 2000-02-28 2001-06-12 Litton Systems, Inc. Dimmable electrodeless light source
EP1119223A1 (fr) * 1999-05-14 2001-07-25 Ushio Denki Kabushiki Kaisya Source lumineuse
US20020050973A1 (en) * 2000-10-26 2002-05-02 Advanced Display Inc. Liquid crystal display
GB2378062A (en) * 2001-07-27 2003-01-29 Visteon Global Tech Inc Flicker reduction for fluorescent lamp

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07199891A (ja) * 1993-12-28 1995-08-04 Canon Inc 表示制御装置
JPH09101763A (ja) * 1995-10-05 1997-04-15 Sharp Corp 画像表示装置の駆動回路
JPH09237684A (ja) * 1995-12-26 1997-09-09 Tokin Corp インバータ回路
EP0782374B1 (fr) 1995-12-26 1999-10-27 Tokin Corporation Onduleur pour alimenter un tube à cathodes froides à l'aide d'un transformateur piézoélectrique
TW334549B (en) * 1996-07-24 1998-06-21 Motorola Inc Method and apparatus for controlling the display of a video image
WO1998007272A1 (fr) * 1996-08-13 1998-02-19 Fujitsu General Limited Circuit avec boucle a phase asservie pour dispositif d'affichage numerique
JPH10247593A (ja) * 1997-03-05 1998-09-14 Nec Corp インバータおよびその駆動方法
JP3418712B2 (ja) * 2000-09-29 2003-06-23 富士通カンタムデバイス株式会社 位相比較回路
KR100548434B1 (ko) * 2000-10-10 2006-02-02 엘지전자 주식회사 휴대형 컴퓨터의 절전 방법
JP2002123226A (ja) * 2000-10-12 2002-04-26 Hitachi Ltd 液晶表示装置
KR100870007B1 (ko) * 2002-06-25 2008-11-21 삼성전자주식회사 백라이트 구동 장치
KR100920353B1 (ko) * 2003-03-14 2009-10-07 삼성전자주식회사 표시 장치용 광원의 구동 장치

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4365204A (en) * 1980-09-08 1982-12-21 American Microsystems, Inc. Offset compensation for switched capacitor integrators
US5331253A (en) * 1992-08-24 1994-07-19 Usi Lighting, Inc. Electronic ballast for gaseous discharge lamp operation
US5844540A (en) * 1994-05-31 1998-12-01 Sharp Kabushiki Kaisha Liquid crystal display with back-light control function
US6127865A (en) * 1997-05-23 2000-10-03 Altera Corporation Programmable logic device with logic signal delay compensated clock network
EP1119223A1 (fr) * 1999-05-14 2001-07-25 Ushio Denki Kabushiki Kaisya Source lumineuse
US6246183B1 (en) * 2000-02-28 2001-06-12 Litton Systems, Inc. Dimmable electrodeless light source
US20020050973A1 (en) * 2000-10-26 2002-05-02 Advanced Display Inc. Liquid crystal display
GB2378062A (en) * 2001-07-27 2003-01-29 Visteon Global Tech Inc Flicker reduction for fluorescent lamp

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ABRAMOVITCH D ED - AMERICAN AUTOMATIC CONTROL COUNCIL INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "Phase-locked loops: a control centric tutorial" PROCEEDINGS OF THE 2002 AMERICAN CONTROL CONFERENCE. ACC. ANCHORAGE, AL, MAY 8 - 10, 2002, AMERICAN CONTROL CONFERENCE, NEW YORK, NY : IEEE, US, vol. VOL. 1 OF 6, 8 May 2002 (2002-05-08), pages 1-15, XP010597074 ISBN: 0-7803-7298-0 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007035861A3 (fr) * 2005-09-21 2007-07-19 Sorin Davidovici Systeme et procede permettant d'obtenir un element capteur ou une matrice de capteurs a gamme dynamique elevee
US7532145B2 (en) 2005-09-21 2009-05-12 Rjs Technologies Inc. High resolution and wide dynamic range integrator
US7782369B2 (en) 2005-09-21 2010-08-24 Rjs Technology, Inc. System and method for a high dynamic range sensitive sensor element or array with gain control
US7786422B2 (en) 2005-09-21 2010-08-31 Rjs Technology, Inc. System and method for a high dynamic range sensitive sensor element or array
US7800669B2 (en) 2005-09-21 2010-09-21 R.J.S. Technology, Inc. System and method for image sensor element or array with photometric and realtime reporting capabilities
US7872681B2 (en) 2005-10-13 2011-01-18 Rjs Technology, Inc. System and method for a high performance color filter mosaic array
US20110140615A1 (en) * 2009-12-11 2011-06-16 Byung-Sam Min Apparatus and method of driving light source
US8531116B2 (en) * 2009-12-11 2013-09-10 Lg Display Co., Ltd. Apparatus and method of driving light source

Also Published As

Publication number Publication date
US20080211834A1 (en) 2008-09-04
TWI408667B (zh) 2013-09-11
EP1484740B1 (fr) 2015-05-06
KR20040081279A (ko) 2004-09-21
US7362303B2 (en) 2008-04-22
KR100920353B1 (ko) 2009-10-07
JP4473013B2 (ja) 2010-06-02
EP1484740A3 (fr) 2006-05-03
US20040179003A1 (en) 2004-09-16
TW200501044A (en) 2005-01-01
US8054307B2 (en) 2011-11-08
JP2004281403A (ja) 2004-10-07
CN1540608A (zh) 2004-10-27

Similar Documents

Publication Publication Date Title
US8054307B2 (en) Device and method of driving light source in display device
US7417616B2 (en) Inverter for liquid crystal display
US7446750B2 (en) Inverter and liquid crystal display including inverter
US7288903B2 (en) Driving device of light source for display device
US20050190171A1 (en) Display device and device of driving light source therefor
US7612756B2 (en) Apparatus and method of driving light source for image display device and image display device having the same
US20030038770A1 (en) Liquid crystal display and method for driving the same
US20050269970A1 (en) Display device and driving device of light source for display device
US7411357B2 (en) Liquid crystal and device of driving light source therefor
US7391163B2 (en) Apparatus of driving light source for display device
KR100925470B1 (ko) 액정 표시 장치 및 액정 표시 장치용 광원의 구동 장치

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK

17P Request for examination filed

Effective date: 20061102

AKX Designation fees paid

Designated state(s): DE FR

17Q First examination report despatched

Effective date: 20080627

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SAMSUNG ELECTRONICS CO., LTD.

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SAMSUNG DISPLAY CO., LTD.

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

INTG Intention to grant announced

Effective date: 20141119

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602004047117

Country of ref document: DE

Effective date: 20150618

RAP2 Party data changed (patent owner data changed or rights of a patent transferred)

Owner name: SAMSUNG DISPLAY CO., LTD.

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602004047117

Country of ref document: DE

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 13

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20160209

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20170221

Year of fee payment: 14

Ref country code: FR

Payment date: 20170223

Year of fee payment: 14

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602004047117

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20181002

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180331