EP1421492A2 - Transmission de gros volumes de donnees par l'intermediaire d'interfaces asynchrones dans des circuits a concept de redondance de type controleur-maitre - Google Patents

Transmission de gros volumes de donnees par l'intermediaire d'interfaces asynchrones dans des circuits a concept de redondance de type controleur-maitre

Info

Publication number
EP1421492A2
EP1421492A2 EP02776659A EP02776659A EP1421492A2 EP 1421492 A2 EP1421492 A2 EP 1421492A2 EP 02776659 A EP02776659 A EP 02776659A EP 02776659 A EP02776659 A EP 02776659A EP 1421492 A2 EP1421492 A2 EP 1421492A2
Authority
EP
European Patent Office
Prior art keywords
data
checker
transmission
master
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02776659A
Other languages
German (de)
English (en)
Inventor
Franz Hechfellner
Rainer Vetter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1421492A2 publication Critical patent/EP1421492A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level

Definitions

  • the subject of the application relates to a method for transmitting data via an asynchronous interface in a circuit arrangement with master-checker redundancy.
  • High availability is an essential feature of technical systems such as B. Telecommunications switching systems. To ensure this, faults in parts of these systems must be recognized and localized as quickly as possible so that the faulty units can be switched off.
  • a concept for fault localization in the hardware relies on the duplication according to the master / checker principle. The complete circuit unit is duplicated and processes all input information in parallel at the exact same time. All data that leave this unit are compared between the master and the checker. If there are any inequalities, the unit is decommissioned and subjected to an error diagnosis.
  • Interfaces can be passed on, intermediate storage is necessary and the data flow may even have to be slowed down.
  • the transmission of wide data buses via asynchronous interfaces can e.g. controlled by a qualifier signal.
  • the data is transferred from the data bus into a register, where it is kept stable for several (3 - 4) cycles, so that it can be safely transferred to the other clock domain.
  • the qualifier signal becomes active. After clocking twice, this signal in the receiver clock domain indicates that the data can now be transferred in full width to the other clock domain. This procedure assumes that the data rate on the bus is not greater than the transmission capacity of the interface.
  • Data and qualifier signal are only taken from the master, the qualifier signal is clocked and distributed to the master and checker. This controls the transfer of the master data into the master and checker. Part of the redundancy is of course lost in this way, since the duplication principle is temporarily abandoned. This can be partially offset by additional measures: at the transition to the non-duplicated transmission path, errors that have occurred up to that point can be detected by comparing the master and checker data; on the non-duplicated transmission path, the data can be backed up, for example, using parity.
  • the object of the registration is based on the problem of specifying a transmission of large amounts of data via an asynchronous interface while largely maintaining the master / checker redundancy.
  • the subject of registration enables high-performance transfer of large amounts of data via asynchronous interfaces while largely maintaining the master / checker redundancy.
  • FIG. 1 shows a parallel data transmission 1 via an asynchronous interface in a circuit based on the master / checker redundancy principle
  • FIG. 2 shows a timing diagram of the cycle-oriented transmission via an asynchronous interface.
  • cycle-oriented transmission The concept on which the subject of the application is based may be referred to as cycle-oriented transmission.
  • the data to be transmitted arrive at the interface as discrete portions, not as a continuous data stream.
  • the start and end of a portion of data to be transferred are clearly defined.
  • the data portions to be transmitted can be classified, ie assigned to specific cycle types and / or formats (cells, packets). Each of these cycles runs in a fixed clock pattern.
  • the number of cycle types / formats is finite. In principle, different types of transmission cycles run independently of one another in parallel. Examples of this are processor write or read cycles with address, control signals and possibly write data in a fixed clock pattern; Packet formats such as ATM cells, IP packets; or a format of your choice for the parallel transmission of status information etc. in one or more successive cycles.
  • the data is transferred from one clock domain to the other via one or more data buses of any width, each separately from master to master and from checker to checker. There is no restriction of redundancy.
  • the start and end of the transmission of a data portion are fixed and the process takes place in a fixed clock pattern.
  • the FSM in the issuing clock domain signals the start and type of the transmission cycle, the further sequence follows a predetermined scheme in both FSMs.
  • Master and Checker provide the first data to be transmitted in the same cycle (clock domain A) on the asynchronous interface.
  • the Sync control FSML in the master and checker indicate the start of the transmission cycle with the same cycle (signal cycle_start).
  • the data is' kept stable for so long, could be transferred to the receiving clock domain (Sync control FSM2, clock domain B) to lock it.
  • the asynchronous interface is located within a block, 3 to 4 cycles are sufficient, otherwise longer times are required depending on the cable lengths.
  • the signal cycle_start is the only point at which the master / checker redundancy concept must be left. Only the master signal is synchronized by multiple clocking in the receiving clock domain (Synchronization B - clock domain B) and starts as sync_cycle_start, then again clock-synchronously in the master and checker, the Sync control FSM2 for data transfer in clock domain B. Before the synchronization of the master Signal, the duplicate cycle_start signals from master and checker are compared. The timing is shown schematically in FIG. 2 as a timing diagram.
  • the FSM can also control the parallel transfer of data on several data buses.
  • FIG. 1 shows the processing of write cycles in a system with 2 microprocessors in master / checker redundancy in clock domain A on a storage unit in clock domain B.
  • the latter is supplied with its own clock, since it is shared by several processors.
  • There are differences in the assignment of the 32-bit data bus: with write cycles, write data can be placed on the data bus in several successive cycles (e.g. 4 cycles with write burst, cycles 2 - 5). Since this data cannot be transmitted via the asynchronous interface as it appears on the data bus, it is stored in the
  • Data buffer & sync control FSM1 temporarily stored and, depending on the cycle type, transferred in parallel and / or sequentially to Sync control FSM2 via the various buses.
  • the circuit can be designed so that when a burst write cycle is transmitted, even the last data word does not experience a greater overall delay than the 3-4 clock initial delay by which all data at the interface must be kept stable.
  • Both FSM1 then generate the cycle_start signal isochronously, but independently of each other; the master signal is synchronized and starts the two FSM2 centrally.
  • the FSM2 is informed of the cycle type decentrally in the first transmission cycle in the control bus. Now that the FSM2 mane started synchronously, they continue to work autonomously and take over data from their Partener FSMl in every cycle until the cycle is complete.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Information Transfer Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Communication Control (AREA)

Abstract

L'invention concerne un procédé pour transmettre de gros volumes de données par l'intermédiaire d'une interface asynchrone dans un circuit à redondance de type contrôleur-maître. Selon l'invention, la transmission des données s'effectue en fonction du type et du volume de données à transmettre, selon différents cycles de transmission, dont le déroulement est fixé et réalisé au moyen d'automates d'états finis (FSM) des deux côtés de l'interface. Ces FSM peuvent commander la prise en charge des données sur des bus de données dont le nombre et la largeur sont aléatoires. Sur chacun de ces bus, les données sont maintenues de façon stable du côté sortie jusqu'à ce qu'elles puissent être prises en charge de manière sûre du côté entrée. Ce concept permet de transmettre un nombre aléatoire de données à chaque cadence suivante jusqu'à ce que le cycle soit achevé.
EP02776659A 2001-08-31 2002-08-28 Transmission de gros volumes de donnees par l'intermediaire d'interfaces asynchrones dans des circuits a concept de redondance de type controleur-maitre Withdrawn EP1421492A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10142611 2001-08-31
DE10142611 2001-08-31
PCT/DE2002/003155 WO2003026175A2 (fr) 2001-08-31 2002-08-28 Transmission de gros volumes de donnees par l'intermediaire d'interfaces asynchrones dans des circuits a concept de redondance de type controleur-maitre

Publications (1)

Publication Number Publication Date
EP1421492A2 true EP1421492A2 (fr) 2004-05-26

Family

ID=7697193

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02776659A Withdrawn EP1421492A2 (fr) 2001-08-31 2002-08-28 Transmission de gros volumes de donnees par l'intermediaire d'interfaces asynchrones dans des circuits a concept de redondance de type controleur-maitre

Country Status (4)

Country Link
US (1) US20040208202A1 (fr)
EP (1) EP1421492A2 (fr)
CN (1) CN1549970A (fr)
WO (1) WO2003026175A2 (fr)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117442A (en) * 1988-12-14 1992-05-26 National Semiconductor Corporation Methods and circuits for synchronizing signals in a modular redundant fault tolerant computer system
US5434996A (en) * 1993-12-28 1995-07-18 Intel Corporation Synchronous/asynchronous clock net with autosense
US6327667B1 (en) * 1995-05-12 2001-12-04 Compaq Computer Corporation Apparatus and method for operating clock sensitive devices in multiple timing domains
DE19536518C2 (de) * 1995-09-29 1998-07-09 Siemens Ag Verfahren zur Aufrechterhaltung des mikrosynchronen Betriebs von gedoppelten informationsverarbeitenden Einheiten
US6687255B1 (en) * 2000-03-21 2004-02-03 Lsi Logic Corporation Data communication circuit having FIFO buffer with frame-in-FIFO generator
US6725388B1 (en) * 2000-06-13 2004-04-20 Intel Corporation Method and system for performing link synchronization between two clock domains by inserting command signals into a data stream transmitted between the two clock domains
US20020069375A1 (en) * 2000-10-12 2002-06-06 Matt Bowen System, method, and article of manufacture for data transfer across clock domains
US6738917B2 (en) * 2001-01-03 2004-05-18 Alliance Semiconductor Corporation Low latency synchronization of asynchronous data
US6842728B2 (en) * 2001-03-12 2005-01-11 International Business Machines Corporation Time-multiplexing data between asynchronous clock domains within cycle simulation and emulation environments

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03026175A3 *

Also Published As

Publication number Publication date
WO2003026175A3 (fr) 2003-07-03
CN1549970A (zh) 2004-11-24
US20040208202A1 (en) 2004-10-21
WO2003026175A2 (fr) 2003-03-27

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