EP1421456B1 - Voltage regulator with frequency response correction - Google Patents

Abstract

The invention relates to a voltage regulator (10, 11) comprising a voltage regulator output (6) that provides a regulated output voltage (Uout) and an internal ohmic resistance (RZ) arranged in series to an external load (RL) to be connected to the voltage regulator output (6). An internal electrical regulation-feedback path of the voltage regulator (10, 11) is tapped both in a first position (A) upstream of the internal ohmic resistance (RZ) and in a second position (B) downstream of the internal ohmic resistance (RZ), said second position (B) being disposed between the internal ohmic resistance (RZ) and the voltage regulator output (6). For frequencies above a predetermined frequency (fw) the regulation is substantially effective directly via the first position (A) and not via the second position (B), while for frequencies below the predetermined frequency (fw) the regulation is substantially carried out via the path: first position (A) internal ohmic resistance (RZ) second position (B).

Description

The invention relates to a voltage regulator according to the preamble of the preamble of claim 1.

Electronic systems on silicon often require the provision of different operating voltages (IO range, digital core and analog circuits).

If an operating voltage of a lower level is to be generated from a given supply voltage, discrete voltage regulators are used as additional components. These are not always desirable because of high cost and additional control lines, but can be cost-effectively integrated with silicon in addition to the system.

Voltage regulators as such are known in the art and described, for example in Funke, R .; Liebscher, S .: "Basic circuits of electronics", Verlag Technik, Berlin 1983, pp. 24 to 34 or in Lindner, H .; Brauer, H .; Lehmann, C .: "Electrical Engineering - Electronics", book publisher Leipzig 1983, p 591 to 605 , Further, in particular on questions of mathematical-physical details of the voltage regulation technique, reference is expressly made to the article " Optimized Frequency-Shaping Circuit Topologies for LDOs "by GA Rincon-Mora and PE Allen in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS - II: ANALOG AND DIGITAL SIGNAL PROCESSING, Vol. 45 (1998), No. 6, pp. 703-708 ,

However, due to stability issues, the realization of integrated voltage regulators is not trivial. The same technical stability problem also occurs in discrete voltage regulator modules.

The above-mentioned stability problems will be briefly explained below. It is referred to Fig. 2 , which generally shows a schematic of a voltage regulator 12 known from the prior art. In general, the following components are found in voltage control circuits: a reference voltage Uref, a control amplifier 1, z. B. formed as an operational amplifier, a control transistor Q, the z. B. may be a FET or a bipolar transistor, the der.Regeltransistor Q in Fig. 2 outlined as a controlled current source. Further, a general voltage control loop includes a load according to Fig. 2 a load resistor RL, an external buffer capacitance CL and, at least in certain cases, an internal voltage divider R1, R2. The buffering capacity CL may also be a purely parasitic capacity.

The DC gain of an open loop in the small signal range is composed of several factors. The DC voltage gain of the control amplifier 1 is in the range between 40 and 60 dB. This amount results from the requirements for the static control deviation. The control transistor Q in conjunction with the load resistor RL and the voltage divider R1, R2 provides a contribution in the range between 0 and 30 dB for amplification, depending on the transistor Q used, the ohmic load resistor RL and the supply voltage.

Fig. 3 shows both a block diagram of a closed loop and a block diagram of an open loop. The open loop transfer function, sometimes referred to as the "open loop transfer function", has poles. The pole frequency fp generally defines the cut-off frequency of a low-pass transfer function of the type 1 / (1 + s / p) in control technology, at which an attenuation of 3 dB and a phase post-rotation of 45 ° occur. Another important term in this context is the term "transit frequency". In the voltage regulation technique, the transit frequency ft is the 0 dB cutoff frequency of a transfer function. At the transit frequency ft, signals are not amplified or attenuated in magnitude. The transit frequency is referred to in the English literature as "unity gain frequency (UGF)". For further mathematical-physical details of the voltage regulation technique, reference is expressly made to the above-mentioned article " Optimized Frequency-Shaping Circuit Topologies for LDOs "by GA Rincon-Mora and PE Allen in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS - II: ANALOG AND DIGITAL SIGNAL PROCESSING, Vol. 45 (1998), No. 6, pp. 703-708 ,

Poles in the open loop transfer function are as follows:

The control amplifier 1 has a dominant pole fp0 whose frequency can be placed within certain limits, wherein a dependence on the input capacitance of the control transistor Q and the allowable power consumption of the control amplifier 1 consists.

The control transistor Q in conjunction with the load resistor RL and the load capacitance (buffer capacity) CL provides a variable pole fp1, the position of which can vary by several decades depending on the load. In the frequency range >> 1 MHz are parasitic poles of the control amplifier 1 (fp2 and others).

The transfer function of the open loop in the s range is $$\mathrm{L}\left(\mathrm{s}\right)\mathrm{=}\frac{\mathrm{A}\mathrm{0}}{\left(\mathrm{1}\mathrm{+}\mathrm{s}\mathrm{/}\mathrm{sp}\mathrm{0}\right)\left(\mathrm{1}\mathrm{+}\mathrm{s}\mathrm{/}\mathrm{sp}\mathrm{1}\right)\left(\mathrm{1}\mathrm{+}\mathrm{s}\mathrm{/}\mathrm{sp}\mathrm{2}\right)}\mathrm{,}$$

wobei unter Vernachlässigung des Ausgangswiderstands des Regeltransistors Q $$\mathrm{RLges}\mathrm{\sim }\left(\mathrm{RL}\mathrm{\parallel }\left(\mathrm{R}\mathrm{1}\mathrm{+}\mathrm{R}\mathrm{2}\right)\right)\mathrm{ist}\mathrm{.}$$

The pole of the control amplifier 1 is sp0. For the load pole sp1 applies $$\mathrm{sp}1~\frac{1}{\mathrm{CL}\cdot \mathrm{RLges}}$$

neglecting the output resistance of the control transistor Q $$\mathrm{RLges}\mathrm{~}\left(\mathrm{RL}\mathrm{\parallel }\left(\mathrm{R}\mathrm{1}\mathrm{+}\mathrm{R}\mathrm{2}\right)\right)\mathrm{is}\mathrm{,}$$

In this case, sp2 denotes the parasitic pole and the expression (· ∥ ·) denotes the resistance which is brought about by a parallel connection of the resistors indicated on both sides of the symbol ∥.

$$\mathrm{sz}\mathrm{=}\mathrm{2}\mathrm{\cdot }\mathrm{\pi }\mathrm{\cdot }\mathrm{fz}$$

(fp - Polfrequenz, fz - Frequenz, bei der die Übertragungsfunktion eine Nullstelle hat)Furthermore applies $$\mathrm{sp}\mathrm{=}\mathrm{2}\mathrm{\cdot }\mathrm{\pi }\mathrm{\cdot }\mathrm{fp}$$

$$\mathrm{sz}\mathrm{=}\mathrm{2}\mathrm{\cdot }\mathrm{\pi }\mathrm{\cdot }\mathrm{fz}$$

(fp - pole frequency, fz - frequency at which the transfer function has a zero)

The high DC gain A0 associated with multiple poles causes the phase of the open loop transfer function to be shifted 180 ° and more upon reaching the transit frequency ft. This is in Fig. 4 represented with the curve for the uncorrected frequency response.

In summary, there is thus a stability problem in that, due to the influence of several poles fp0, fp1 and fp2 in combination with the high gain A0, the phase margin of the open control loop can reach impermissible values of around 0 °.

From the prior art, various approaches to overcome this stability problem by frequency response correction are known, all known approaches have specific disadvantages.

In general, the goal of the frequency response correction is to achieve a phase margin of the open control loop of> 45 °.

One prior art approach is to use an integral variable gain amplifier. The transit frequency ft of the system is placed far below the effective range of the poles fp1 and fp2 by realization of very low fp0. The disadvantage here, however, is a slow control. Large integrated capacities are needed to achieve the low fp0.

Another prior art approach uses a wide bandwidth variable gain amplifier. Here, fp0 is realized much larger than ft. The disadvantage here, however, is the high power consumption of the control amplifier. At high system transit frequencies, parasitic poles such as fp2 can further degrade the phase margin.

Another solution approach, which is already known from the prior art, is the realization of zeros in the open loop transmission function. As in Fig. 4 1, a zero at the frequency fz1 in the open loop transfer function L (s) will cancel the phase rotation of one pole. fz1 is usefully chosen smaller than ft.

Various realization possibilities of a zero point in the open loop transmission function are known from the prior art. Thus, a zero point can be generated by external wiring of the voltage regulator with passive components. The disadvantage here, however, is the high cost of the external components.

Furthermore, a zero in the open loop transfer function can be generated by integrated active filters. However, this disadvantageously requires an additional power consumption.

The possibility of generating a zero known from the prior art by so-called "feed forward" techniques has the disadvantage of difficult to estimate side effects of the circuit.

According to another already known variant, which forms the generic prior art with respect to the invention, the zero point in the open loop transfer function is realized by introducing an internal series resistor into the load circuit of the voltage regulator. A circuit which falls under the generic art for the invention, is in Fig. 5 shown.

The voltage regulator 13 according to Fig. 5 has a variable gain amplifier 1. This has two inputs 3, 4 and an output 5. Furthermore, the voltage regulator 13 after Fig. 5 a controlled current source Q and a voltage regulator output 6 for providing a regulated output voltage Uout. The controlled current source Q can z. B. be a transistor (FET or bipolar transistor).

The first input 3 of the control amplifier 1 is connected to a reference voltage source Uref. The second input 4 of the control amplifier 1 is connected to an electrical feedback path which leads outside of the control amplifier 1 from the output 5 of the control amplifier 1 via the controlled current source Q to the second input 4 of the control amplifier 1. Between the controlled current source Q and the second input 4 of the control amplifier 1 branches on in Fig. 5 with the "A" node from the electrical feedback path an electrical output path to the voltage regulator output 6 from. In the electrical output path, an internal ohmic resistor RZ is serially arranged between the branch A and the voltage regulator output 6. This internal ohmic resistance RZ is also sometimes referred to as "series resistance in the load circuit".

The in Fig. 5 Voltage regulator 13 shown further includes a voltage divider circuit R1, R2, which is optional and, as all are related to FIG Fig. 5 described circuit details with the exception of the internal ohmic resistance RZ, in relation to the present invention is not one of the mandatory generic features.

The introduction of the series resistor RZ in the load circuit causes in connection with the external buffer capacity CL, which may also be a purely parasitic capacitance, a zero point in the open loop. $$\mathrm{fz}=\mathrm{CL}\cdot \mathrm{RZ}/\left(2\cdot \mathrm{\pi }\right)$$

This will be $$\mathrm{L}\left(\mathrm{s}\right)\mathrm{=}\frac{\mathrm{A}\mathrm{0}\cdot \left(1+\mathrm{s}/\mathrm{sz}0\right)}{\left(\mathrm{1}\mathrm{+}\mathrm{s}\mathrm{/}\mathrm{sp}\mathrm{0}\right)\left(\mathrm{1}\mathrm{+}\mathrm{s}\mathrm{/}\mathrm{sp}\mathrm{1}\right)\left(\mathrm{1}\mathrm{+}\mathrm{s}\mathrm{/}\mathrm{sp}\mathrm{2}\right)}\mathrm{,}$$

By a suitable choice of fz, a sufficient phase margin can be achieved for a large load resistance range.

The advantages of the above-described type of frequency compensation are that parasitic impedances ESR (ESR = equivalent series resistance / serial equivalent resistance) in the external load circuit (see Fig. 6 ) can only slightly influence the controlled system, since the internal ohmic resistance RZ dominates over these parasitic impedances ESR in the load circuit. A minimum ESR for an external capacitance is not necessary in the previously described type of frequency compensation, since an internal resistance (internal resistance RZ) is guaranteed. Furthermore, sufficient for the realization of the zero point, a passive component, namely the said internal ohmic resistance RZ, which even can be integrated and thus energy-saving effect compared to the other known from the prior art solutions. In addition, the frequency fz, at which the transfer function has a zero, is well reproducible and depends only on the size of said internal resistance RZ and the buffer capacitance CL, but not on transistor parameters and operating voltages.

Despite these already very significant advantages, the solution of the stability problem according to the prior art last described has the disadvantage of a fault voltage Uf dependent on the load current I as a result of a voltage drop across the said internal ohmic resistor RZ with Uf = I * RZ. In addition, the integration of the internal ohmic resistor RZ is problematic because it must have a very low value and at the same time high current-carrying capacity.

In the publication US 5,631,598 a voltage regulator is disclosed which feeds an output of the voltage regulator back to an input of an operational amplifier in order to realize a regulation.

The invention is therefore based on the object, starting from the generic voltage regulator to provide a voltage regulator, which overcomes the above-described Fehlspannungsproblem with consistently good stability with sufficient phase margin.

According to the invention this object is achieved by a voltage regulator according to claim 1. Overcoming the Fehlspannungsproblems takes place in the voltage regulator according to the invention by Fehlspannungskompensation. For this purpose, the control is tapped both before and after the internal ohmic resistance and the voltage regulator designed such that act in different frequency ranges different control paths. Concretely, in the terms of claim 1, this means: the false voltage is for the Frequency range below the predetermined frequency by tapping at the second point, ie between the internal ohmic resistance and the voltage regulator output, regulated and thus can not be measured at the external load. For the frequency range above the predetermined frequency is through Tapped at the first point, which is separated from the second point by the internal ohmic resistance, regulated, whereby the zero point at fz becomes effective and the phase pre-rotation (frequency response correction) ensured.

Advantageous and preferred embodiments of the voltage regulator according to the invention are the subject matter of claims 2 to 15.

In the preferred embodiment of the voltage regulator according to the invention according to claim 2, the Fehlspannungskompensation is realized by means of a crossover network 2 in the feedback path.

In the preferred embodiment of the voltage regulator according to the invention according to claim 3, the coupling factors of the crossover 2 are chosen so that no additional pole can arise around the crossover frequency fw.

The particularly preferred embodiment of the voltage regulator according to the invention according to claim 8 is particularly suitable for the implementation as an integrated circuit, since the N individual resistors each seen individually only a low current carrying capacity of I / N must have.

By taking place in the particularly preferred embodiment of the voltage regulator according to the invention according to claim 13 receiving the otherwise purely external buffer capacity in the voltage regulator itself, the frequency at which the transfer function has a zero, be influenced more targeted.

In the likewise particularly preferred embodiment of the voltage regulator according to the invention according to claim 15, the internal ohmic resistor RZ is designed as an integrated component, which is particularly cost-effective.

Fig. 1

ein schematisches Schaltbild eines ersten Ausführungsbeispiels eines erfindungsgemäßen Spannungsreglers;

Fig. 2

allgemein ein Schema eines aus dem Stand der Technik bekannten Spannungsreglers ohne Frequenzgangkorrektur;

Fig. 3

Blockbilder einer geschlossenen Regelschleife und einer offenen Regelschleife;

Fig. 4

Beispiele von Frequenzgängen (Verstärkung, Phase) eines Spannungsreglers ohne und mit Frequenzgangkorrektur;

Fig. 5

allgemein ein Schema eines aus dem Stand der Technik bekannten Spannungsreglers mit Frequenzgangkorrektur durch Schaltung eines Serienwiderstandes in den Lastkreis; und

Fig. 6

schematisch ein Schaltbild eines zweiten Ausführungsbeispiels des erfindungsgemäßen Spannungsreglers.

Embodiments of the voltage regulator according to the invention are explained below with reference to figures. It shows:

Fig. 1

a schematic diagram of a first embodiment of a voltage regulator according to the invention;

Fig. 2

in general, a scheme of a known from the prior art voltage regulator without frequency response correction;

Fig. 3

Block diagrams of a closed loop and an open loop;

Fig. 4

Examples of frequency responses (gain, phase) of a voltage regulator without and with frequency response correction;

Fig. 5

generally a schematic of a known from the prior art voltage regulator with frequency response correction by switching a series resistor in the load circuit; and

Fig. 6

schematically a circuit diagram of a second embodiment of the voltage regulator according to the invention.

A first embodiment of a voltage regulator 10 according to the invention, which in Fig. 1 1, comprising a control amplifier 1 designed as an operational amplifier, which has two inputs 3, 4 and an output 5, a controlled current source Q and a voltage regulator output 6 for providing a regulated output voltage Uout. In the Fig. 1 only schematically represented controlled current source Q is in the present embodiment, a transistor, such as an NFET, PFET, npn bipolar transistor or pnp bipolar transistor.

The first input 3 of the control amplifier 1 is connected to a reference voltage source Uref. The second input 4 of the control amplifier 1 is connected to an electrical feedback path which leads outside of the control amplifier 1 from the output 5 of the control amplifier 1 via the transistor Q to the second input 4 of the control amplifier 1. Between the transistor Q and the second input 4 of the control amplifier 1 branches on in Fig. 1 with the "A" node from the electrical feedback path an electrical output path to the voltage regulator output 6 from. In this electrical output path, an ohmic resistor RZ is serially arranged between the branch A and the voltage regulator output 6, which is referred to below as "internal resistance RZ".

Furthermore, the illustrated embodiment of the voltage regulator 10 according to the invention on a crossover 2, which has two inputs 7, 8 and an output C. The crossover 2 is connected in series with its first input 7 and its output C in the electrical feedback path that its first input 7 in the direction of the branch A of the electrical output path and its output C in the direction of the second input 4 of the control amplifier 1 has. The second input 8 of the crossover network 2 is connected to a further electrical path, which between the internal ohmic resistor RZ and the voltage regulator output 6 at point B (see Fig. 1 ) branches off the electrical output path. In this case, the said further electrical path in the embodiment of the voltage regulator 10 of the invention Fig. 1 a voltage divider circuit consisting of two ohmic resistors R1, R2. The second input 8 of the crossover network 2 is connected between the two resistors R1, R2 of the voltage divider circuit to the further electrical path.

The crossover 2 is designed so that it transmits signals having frequencies above a predetermined crossover frequency fw from its first input 7 to its output C. Signals with frequencies below the predetermined crossover frequency fw are transmitted from the second input 8 of the crossover 2 to its output C. The respective other internal path of the crossover network 2 is essentially blocked for signals from the respective other frequency range. Relative to the selected node name in Fig. 1 this means that the crossover 2 transmits signals with frequencies «fw from B to C and signals with frequencies» fw from A to C.

The operation of the crossover 2 in the present circuit is the following: The error voltage Uf is compensated for the frequency range «fw by tapping at point B and thus can not be measured at the load. For the frequency range »fw is controlled by tapping at point A, whereby the zero point at fz becomes effective and ensures the phase pre-rotation (frequency response correction). However, this requires that fz <ft be selected.

In the embodiment of the voltage regulator of the invention Fig. 1 is the maximum coupling factor of the crossover 2 of A → C is greater than or at least equal to the maximum coupling factor of the crossover 2 of B → C chosen so as not to create an additional pole by fw.

The crossover 2 is realized in the present embodiment circuitry as a passive RC filter.

Fig. 6 shows a second embodiment of the voltage regulator 11 according to the invention, in which the voltage regulator 11 is designed as an integrated circuit. In the embodiment of the voltage regulator 11 of the invention Fig. 6 is said internal resistance RZ, together with the control transistor Q as a parallel connection of N individual elements executed with R = RZ · N (N> 1), which must have only a low current carrying capacity of I / N per se.

The dimensioning of the frequency compensation at the in Fig. 6 In the exemplary embodiment described, the integrated voltage regulator 11 should deliver an output voltage Uout of 1.5 V at I = 0.1 A maximum current. The sum of the voltage divider resistors R1 + R2 is 150 kΩ. fp0 of the control amplifier 1 is by design 100 kHz. The regulated supply voltage is supported by an external capacitance CL = 1μF. In a further embodiment of the voltage regulator according to the invention, this capacitive support of the regulated supply voltage takes place even by an internally arranged in the voltage regulator capacitance, which is connected in parallel to be connected to the voltage regulator output 6 consumers in an electrical branch, between the voltage regulator output 6 and the internal ohmic resistance RZ branches off in the direction of mass.

• RLges ist minimal ≈ 1,5 V / 0,1 A = 15 Ω und maximal 150 kΩ. fp1 liegt somit im Bereich von ≈ 1 Hz bis 10 kHz.

The estimation of the pole and zero frequencies is as follows:

• RLges is minimal ≈ 1.5 V / 0.1 A = 15 Ω and a maximum of 150 kΩ. fp1 is thus in the range of ≈ 1 Hz to 10 kHz.

The internal resistance RZ is set to 0.32 Ω. The voltage drop at RZ at maximum current is maximum 0.32 Ω · 0.1 A = 0.032 V.

With a capacitance of CL = 1 μF and a resistance RZ = 0.32 Ω, the desired zero parts is fz = 1 / ( ₂ · π · 0.32 Ω · 1 μF) ≈ 500 kHz.

The corresponding frequency response is in Fig. 4 represented (curve "frequency response correction by zero"). The frequency response has enough phase reserve in every permissible load case 9 on. Fig. 4 corresponds to 10% of the maximum load (fp1 = 1 kHz). Looking at the phase response in Fig. 4 It can be seen that even at minimum load (fp1 = 1 Hz) and at full load (fp1 = 10 kHz) the phase reserve would not fall below 45 °.

If you compare that in Fig. 6 illustrated embodiment 11 with the in Fig. 1 illustrated embodiment 10 of the voltage regulator according to the invention, it should be noted that the resistor R2 from the voltage divider circuit after Fig. 1 in the embodiment of Fig. 6 divided into two parts R2 'and R2 ".

At the in Fig. 6 2, the frequency divider 2 is essentially formed from R1, R2 ', R2 "and CF. Approximately, fw ≈ 1 / (2 * π * CF * (R2" ∥ (R1 + R2'))) ,

Like all other components within the voltage regulator 11 Fig. 6 the capacity CF is also integrated on the chip. It is possible to realize the capacitance CF as gate capacitance or junction capacitance, since sufficient voltage is applied during operation.

A peculiarity of in Fig. 6 illustrated embodiment of the voltage regulator 11 according to the invention is that it is not necessary, the points A1, A2, ..., AN (see Fig. 6 ) electrically directly connect. Dynamically and statically, the points A1, A2,..., AN are at the same potential, since the loading of the point AN by CF is negligible.

As in the embodiment 10 of Fig. 1 , so are in the embodiment of the voltage regulator 11 according to the invention after Fig. 6 the controlled current sources Q1, Q2, ..., QN formed as transistors. A particular advantage of the embodiment of the voltage regulator according to the invention 11 after Fig. 6 is that each single transistor Q1, Q2, ..., QN is provided with a series resistor of the size RZ · N, resulting in increased ESD protection. When bipolar transistors are used for Q1, Q2,..., QN, the provision of the series resistors RZ.N is also of particular advantage for their thermal decoupling.

In its frequency function, the crossover (R1, R2 ', R2 ", CF) in the circuit of the embodiment 11 after Fig. 6 in principle designed the same as the crossover 2 in the circuit of the embodiment 10 after Fig. 1 , This means that the crossover network (R1, R2 ', R2 ", CF) transmits signals with frequencies" fw from B to C and signals with frequencies "fw from AN to C. In addition, in the exemplary embodiment of the voltage regulator 11 according to the invention Fig. 6 the maximum coupling factor of the crossover AN → C is chosen to be greater than or at least equal to the maximum crossover factor of the crossover B → C so as not to create an additional pole around fw.

Claims (15)

1. Voltage regulator (10, 11) having

   - a voltage regulator output (6) for providing a regulated output voltage (Uout) via a load branch;

   - an internal electrical regulation feedback path;
   and

   - an internal non-reactive resistor (RZ), which is arranged in the internal load branch of the voltage regulator (10, 11) in such a way that it is located electrically in series with the external load (RL) to be connected to the voltage regulator output (6),
   characterized by

   - a frequency diplexer (2), which is connected into the regulation feedback path in series, and is connected by a first input to a first point (A) upstream of the internal non-reactive resistor (RZ), and by a second input to a second point (B) downstream of the internal non-reactive resistor (RZ), the second point (B) lying between the internal non-reactive resistor (RZ) and the voltage regulator output (6), and

   - the frequency diplexer (2) having an output (C) for feeding back the signal into the regulation feedback path; and

   - the frequency diplexer (2) being designed in such a way that the frequency diplexer (2) transmits signals having frequencies above a predetermined diplexer frequency (fw) from its first input (7) to its output (C), and that the frequency diplexer (2) transmits signals having frequencies below the predetermined diplexer frequency (fw) from it second input (8) to its output (C).
2. Voltage regulator (10, 11) according to Claim 1, having

   - a regulating amplifier (1), which has two inputs (3, 4) and an output (5),
   and

   - a controlled current source (Q), in which case

   - the first input (3) of the regulating amplifier (1) serves for connection to a reference voltage source (Uref),

   - the second input (4) of the regulating amplifier (1) is connected to the regulation feedback path which leads outside the regulating amplifier (1) from the output (5) of the regulating amplifier (1) via the controlled current source (Q) to the second input (4) of the regulating amplifier (1), and

   - between the controlled current source (Q) and the second input (4) of the regulating amplifier (1), and an electrical output path branches (A) from the regulation feedback path to the voltage regulator output (6), in which the internal non-reactive resistor (RZ) is arranged in series between the branching (A) and the voltage regulator output (6).
3. Voltage regulator (10, 11) according to Claim 2,
   characterized in that
   the maximum coupling factor of the frequency diplexer (2) from its first input (7) to its output (C) is greater than or equal to the maximum coupling factor from its second input (8) to its output (C).
4. Voltage regulator (10, 11) according to Claim 2 or 3,
   characterized in that
   the regulating amplifier (1) is an operational amplifier.
5. Voltage regulator (10) according to one of Claims 2 to 4,
   characterized in that

   - the further electrical path mentioned has a voltage divider circuit and

   - the second input (8) of the frequency diplexer (2) is connected to the further electrical path between resistors (R1, R2) of the voltage divider circuit.
6. Voltage regulator (11) according to Claim 2,
   characterized in that the frequency diplexer is a passive RC filter (CF, R1, R2', R2").
7. Voltage regulator (11) according to Claim 6,
   characterized in that
   the frequency diplexer has a voltage divider circuit (R1, R2', R2").
8. Voltage regulator (11) according to one of the preceding claims,
   characterized
   in that the internal non-reactive resistor (RZ) is embodied as a parallel circuit of N individual resistors, where N is greater than 1.
9. Voltage regulator (11) according to one of Claims 2 to 8,
   characterized
   in that the controlled current source Q mentioned is embodied as a parallel circuit of N individual controlled current sources (Q1 to QN), where N is greater than 1.
10. Voltage regulator (11) according to Claim 9 referred back to Claim 8,
    characterized in that

    - each of the N individual controlled current sources (Q1 to QN) is in each case electrically connected directly to its respectively associated individual resistor from the set of N individual resistors, thereby producing N direct electrical connections between the N individual controlled current sources (Q1 to QN) and the N individual resistors,

    - the N direct electrical connections mentioned are not electrically interconnected, and

    - the first input of the frequency diplexer is directly connected only to one of the N direct electrical connections mentioned (AN).
11. Voltage regulator (10, 11) according to one of the preceding claims,
    characterized
    in that the controlled current source (Q) or at least one of the N individual controlled current sources (Q1 to QN) is a transistor.
12. Voltage regulator (10, 11) according to claim 11,
    characterized
    in that the transistor is a FET or a bipolar transistor.
13. Voltage regulator according to one of the preceding claims,
    characterized by
    an internal capacitance which is located electrically in parallel with the external load to be connected to the voltage regulator output and is arranged in an electrical branch which branches in the direction of ground between the internal non-reactive resistor and the voltage regulator output.
14. Voltage regulator (10, 11) according to one of the preceding claims,
    characterized
    in that the dimensions of its components (1, 2, RZ, Q, R1, R2) are chosen such that a frequency (FZ) at which its transfer function has a zero is less than its transition frequency (ft).
15. Voltage regulator (10, 11) according to one of the preceding claims,
    characterized
    in that it is embodied as an integrated circuit.

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