EP1415349A2 - Memory cell - Google Patents
Memory cellInfo
- Publication number
- EP1415349A2 EP1415349A2 EP02767055A EP02767055A EP1415349A2 EP 1415349 A2 EP1415349 A2 EP 1415349A2 EP 02767055 A EP02767055 A EP 02767055A EP 02767055 A EP02767055 A EP 02767055A EP 1415349 A2 EP1415349 A2 EP 1415349A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- source
- drain
- control gate
- memory cell
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000002347 injection Methods 0.000 claims abstract description 37
- 239000007924 injection Substances 0.000 claims abstract description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 36
- 235000012239 silicon dioxide Nutrition 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 4
- 108091006146 Channels Proteins 0.000 description 41
- 238000003860 storage Methods 0.000 description 35
- 239000002800 charge carrier Substances 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000012212 insulator Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 102100037807 GATOR complex protein MIOS Human genes 0.000 description 3
- 101000950705 Homo sapiens GATOR complex protein MIOS Proteins 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical group 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
Definitions
- the invention relates to a memory cell.
- Computers with memory arrangements are used in a wide variety of applications, be it as a mainframe, as a personal computer, in washing machines, in kitchen appliances, in motor vehicles, in telephones, in answering machines or in other applications.
- a computer is to be understood in the broadest sense as an electronic control and / or computing device.
- the memory arrangement of the computer is used for the permanent or temporary storage of data, for example parameters which are necessary for the operation of the computer, or of calculation results which are generated by the computer during operation of the computer.
- the memory arrangement has a memory with at least one, usually with a plurality of memory cells.
- Each memory cell has a memory element in which an amount of electrical charge can be stored so as to adjust the memory content of the memory cell.
- the memory cells have volatile and non-volatile memory cells.
- a memory content stored in the memory element typically remains in the memory element for only about one second. The memory content must therefore be refreshed periodically.
- a memory content stored in the memory element remains permanently in the memory element for a storage time of the order of years.
- MOSFET metal oxide semiconductor field effect transistor
- the gate electrode is used as the control gate.
- a memory element for storing a memory content of the memory cell is provided between the control gate and the gate oxide layer over the channel region.
- the storage element has a potential barrier both towards the channel area and towards the control gate. Characterized in that a suitable, sufficiently high electrical voltage is applied to the control gate, electrical charge carriers can be charged from the channel area into the storage element or can be discharged from the storage element into the channel area. As a result, a memory content of the memory cell can either be programmed or deleted.
- Non-volatile memory is the EEPROM (Electrically Erasable Programmable Read Only Memory). With the EEPROM, a programmed memory content can be deleted by applying an electrical voltage.
- EEPROM Electrically Erasable Programmable Read Only Memory
- MIOS metal insulator oxide semiconductor
- the memory element is formed by a metallically conductive floating gate.
- the memory element is formed from an insulator memory element made of (at least) one insulator material.
- the storage content of the storage element is formed by a charge quantity of electrical charge carriers located (“trapped”) in the insulator storage element.
- the aim is to reduce the power consumption when programming the memory cell.
- a floating gate memory cell is known from [1].
- the memory cell from [1] has a source region, a drain region, a channel region, a memory element arrangement with a floating gate and a control gate arranged above it, and a side-side selection gate provided next to the memory element arrangement.
- a comparatively low voltage is applied to the selection gate in order to generate a small electrical current flow in the channel region.
- An electrical voltage is applied to the control gate which is sufficiently high to charge electrical charge carriers into the floating gate.
- the electrical voltage applied to the selection gate in the memory cell from [1] can be significantly lower than the voltage required to charge the floating gate. This enables programming with a lower current than with a floating gate memory cell without a selection gate.
- the voltage for the selection gate must be selected to be sufficiently large that electrical charge carriers can reach the channel region from the source region, so that a continuous electrically conductive channel is formed between the source region and the drain region.
- each individual memory cell is typically reduced.
- [2] discloses a non-volatile semiconductor memory in which a first gate region section arranged above a first ONO memory layer and above a source region, and a second gate arranged above a second ONO memory layer and above a drain region. Area section and a third gate area section arranged above a channel area and above a gate insulating layer are provided, the first, second and third gate area sections being electrically coupled to one another.
- the invention is based on the problem of creating an efficient, energy-saving and reliable memory cell.
- a memory cell is created with: a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region running between the source region and the drain region with a variable electrical conductivity, a source-side control gate, which extends at least partially over a source-side edge section of the channel area adjoining the source area and is designed to change the electrical conductivity of the source-side edge section, a drain-side control gate, which extends at least partially over a drain-side edge section of the channel region that adjoins the drain region and is designed to change the electrical conductivity of the drain-side edge section, one between the source-side control gate and the drain -side control gate arranged in ection gate, which extends over a central section of the channel region and is designed to change the electrical conductivity of the central section, the central section extending between the source-side edge section and the drain-side edge section of the channel region, one A source-side memory element that extends at least between the source-side edge section and the source-side control gate, and a drain-side
- a separate memory content and thus one bit of data each can be stored in the source-side memory element and in the drain-side memory element.
- the memory capacity of the memory cell is thus doubled in comparison to a memory cell with only one memory element.
- the memory cell can also be programmed to save energy and reliably.
- the memory cell is programmed according to the following procedure.
- An (electrical) source voltage with a source voltage value is applied to the source region.
- An (electrical) drain voltage with a drain is applied to the drain area. Voltage value applied.
- the source voltage value and the drain voltage value are different.
- a source-drain voltage is thus present between the source region and the drain region, the value of which is equal to the difference between the source voltage value and the drain voltage value.
- An electrical injection gate voltage with an injection gate voltage value is applied to the injection gate.
- An electrical source control gate voltage with a source control gate voltage value is applied to the source-side control gate.
- An electrical drain control gate voltage with a drain control gate voltage value is applied to the drain-side control gate. The source control gate voltage value and the drain control gate voltage value are each greater in magnitude than the injection gate voltage value.
- the source control gate voltage value and the drain control gate voltage value can be the same.
- a suitable electrical voltage is therefore applied between the source region and the drain region.
- the source-side control gate By means of the source-side control gate, electrical charge carriers are charged from the source region into the source-side edge section of the channel region under the source-side control gate.
- a comparatively high electrical voltage is applied to the source-side control gate, and there is still no tunneling of charge carriers into the source-side storage element.
- a relatively low electrical voltage is applied to the injection gate.
- the electrical current in the central channel region can be chosen to be particularly low due to the control gate on the source side, without the flow of the electrical current in the channel region being interrupted between the source region and the drain region.
- the memory cell can therefore be programmed to save energy.
- a suitable electrical source-drain voltage is applied between the source region and the drain region, which polarity is reversed when comparing the source-drain voltage when programming the drain-side memory element and in terms of amount can be the same size. If the source-drain voltage is of the same magnitude, the other voltages can be selected to be the same as when programming the drain-side memory element.
- the power consumption is particularly low due to the injection gate.
- the storage element can have silicon nitride.
- the storage element can have silicon dioxide or another suitable insulator material.
- the memory element can be an integrated part of an ONO layer, which is formed from a first silicon dioxide layer, a silicon nitride layer formed on the first silicon dioxide layer and a second silicon dioxide layer formed on the silicon nitride layer.
- the gate oxide layer and the first silicon dioxide layer can be formed as separate layers. Alternatively, the gate oxide layer can be formed in one piece with the first silicon dioxide layer.
- the source-side control gate and the drain-side control gate can be contacted separately. This is advantageous if different electrical voltages are to be applied to the source-side control gate and the drain-side control gate.
- the source-side control gate and the drain-side control gate are preferably electrically coupled to one another.
- only one voltage source is required for the source-side control gate and the drain-side control gate to apply a respective voltage.
- particularly simple and thus efficient programming of the memory cell can be achieved in this way.
- the drain-side memory element can be programmed first, then the source-drain voltage can be interchanged, and then the source-side memory element can be programmed without further changes, as already described above.
- the source-side storage element can be programmed first and then the drain-side storage element.
- the channel area can have an n-channel.
- the channel area can have a p-channel.
- a memory arrangement according to the invention which is designed as an EEPROM, has at least one memory cell which is constructed as described above.
- Fig. 1 shows a memory cell according to a first embodiment of the invention, in which the drain-side memory element is programmed.
- FIG. 2 shows the memory cell from FIG. 1, in which the memory contents of the source-side memory element and the drain-side memory element are erased.
- 3a shows a memory cell according to a second embodiment of the invention in cross section in a first manufacturing state during its manufacture.
- 3b shows the memory cell according to the second embodiment of the invention in cross section in a second manufacturing state during its manufacture.
- 3c shows the memory cell according to the second embodiment of the invention in cross section in a third manufacturing state during its manufacture.
- 3d shows the memory cell according to the second embodiment of the invention in cross section in a fourth manufacturing state during its manufacture.
- Fig. 3e the memory cell according to the second embodiment of the invention in cross section in the completed manufacturing state.
- Fig. 3f two memory cells according to the invention like the one shown in Fig. 3e from above.
- FIG. 1 shows a memory cell according to a first embodiment of the invention, in which the drain-side memory element is programmed.
- n-type channel area 103 has a substrate 100, an n + -doped source region 101 formed in the substrate 100, an n + -doped drain region 102 formed in the substrate 100 and one between the source region 101 and the drain - Area 102 extending n-type channel area 103 with a variable electrical conductivity.
- the memory cell also has a source-side control gate 104, which extends at least partially over a source-side edge section 105 of the channel region 103 which adjoins the source region 101 and for Changing the electrical conductivity of the source-side edge section 105 is formed.
- the memory cell also has a drain-side control gate
- the 107 of the channel region 103 extends and is designed to change the electrical conductivity of the drain-side edge section 107.
- An injection gate 108 is arranged between the source-side control gate 104 and the drain-side control gate 106, which extends over a central section 109 of the channel region 103 and is designed to change the electrical conductivity of the central section 109.
- the middle section 109 extends between the source-side edge section 105 and the drain-side edge section 107 of the channel region 103.
- the memory cell also has a source-side memory element 110 made of silicon nitride, which extends between the source-side control gate 104 on the one hand and the injection gate 108, the source-side edge section 105 and the source region 101 on the other.
- the memory cell has a drain-side storage element 111 made of silicon nitride, which extends between the drain-side control gate 106 on the one hand and the injection gate 108, the drain-side edge section 107 and the drain region 102 on the other.
- the memory cell also has a gate oxide arrangement 112 made of silicon dioxide.
- the gate oxide arrangement 112 has a gate oxide layer 113 which extends between the substrate 100 on the one hand and the source-side control gate 104, the drain-side control gate 106 and the injection gate 108 on the other hand.
- Between the source-side control gate 104 and the source-side memory element 110, between the source-side memory element 110 and the injection gate 108, between the injection gate 108 and the A drain-side memory element 111 and between the drain-side memory element 111 and the drain-side control gate 106 each have a layer of silicon dioxide, these layers of silicon dioxide forming part of the gate oxide arrangement 112 and being formed in one piece with the gate oxide layer 113.
- An electrical voltage of 0 V is applied to the source region 101.
- An electrical voltage of 5 V is applied to the drain region.
- An electrical voltage of 10 V is applied to the source-side control gate 104 and to the drain-side control gate 105 by means of a common voltage source.
- An electrical voltage of 1.5 V is applied to the injection gate 108.
- a memory cell has a p + -doped source region, a p + - doped drain region and a p-type channel region running between the source region and the drain region and having a variable electrical conductivity.
- FIG. 2 shows the memory cell from FIG. 1, in which the memory contents of the source-side memory element 110 and the drain-side memory element 111 are erased.
- the same positive electrical voltage of 5 V is applied to the source region 101 and to the drain region 102.
- To the source-side control gate 104 and to the drain-side Control gate 106 is applied the same negative electrical voltage of -5 volts.
- An electrical voltage of 0 V is applied to the injection gate 108.
- holes from the channel region 103 are loaded into the source-side storage element 110.
- These holes recombine with negative electrical charge carriers located in the source-side storage element 110.
- the negative electrical charge of the negative charge carriers located in the source-side storage element 110 is compensated for, and thus the memory content in the source-side storage element 110 is erased.
- holes are loaded from the channel region 103 into the drain-side storage element 111.
- a negative electrical voltage can alternatively be applied to the injection gate 108.
- an electrical voltage of 1.2 V can be applied between the source region 101 (0 V) and the drain region 102 (1.2 V). A voltage of approximately 2 V is then respectively applied to the source-side control gate 104, to the drain-side control gate 106 and to the injection gate 108.
- an electrical voltage of -1.2 V is applied between the source region 101 (1.2 V) and the drain region 102 (0 V).
- the voltages at the source side control gate 104, the drain side control gate 106 and the injection gate 108 are also 2 V, i.e. only the source-drain voltage is reversed.
- Table 1 shows typical electrical voltages which are to be applied to the different elements of the memory cell and which are suitable in the stated combination for programming, erasing or reading out the memory cell.
- FIGS. 3a to 3f A method for producing a memory cell according to the invention is described below with reference to FIGS. 3a to 3f.
- 3a shows a memory cell according to a second
- a p-type substrate 300 is used as the starting material for the memory cell.
- a 10 nm thick gate oxide layer 301 is formed on the substrate 300.
- An injection gate layer with a layer sequence of successively polysilicon 302a, tungsten silicide 302b, TEOS is formed on the gate oxide layer 301
- the injection gate layer is structured photolithographically
- a silicon nitride layer is deposited on the structure from FIG. 3a.
- the silicon nitride layer is etched back, so that laterally of injection gate 302 nitride spacer 303 remain and the structure shown in FIG. 3b is formed.
- An arsenic implantation step is carried out on the structure from FIG. 3b, in which a source region 304 and a drain region 305 are formed, as shown in FIG. 3c.
- a channel region extends between the source region 304 and the drain region 305.
- a layer of thick oxide 306 is formed above the source region 304 and the drain region 305 by means of oxidation, so that the structure shown in FIG. 3c is formed.
- the nitride spacers 303 are now removed by a wet etching step.
- a silicon dioxide layer acts as an etching stop layer, so that the gate oxide layer 301 is not attacked and the structure shown in FIG. 3d is formed.
- a silicon dioxide etching step is first carried out, in which the gate oxide layer 301 is removed in regions 307 next to the injection gate 302 (and the thick oxide 306 is thinned out).
- a lower oxide layer 308 of silicon dioxide is then formed on the surface of the partially finished structure.
- a storage element layer 309 made of silicon nitride is formed on the lower oxide layer 308.
- An upper oxide layer 310 made of silicon dioxide is formed on the memory element layer 309.
- the source-side storage element 311 and the drain-side storage element 312 are each formed from the storage element layer 309 made of silicon nitride and delimited on one side by the lower oxide layer 308 and on the other side by the upper oxide layer 310.
- a polysilicon layer is formed on top oxide layer 310
- a tungsten silicide layer 314 is formed in the polysilicon layer 313.
- Tungsten silicide layer 314 are structured photolithographically (photolithography and subsequent etching of the
- Polysilicon layer 313 and tungsten layer 314 thus become a source-side control gate 315 and a drain-side
- Control gate 316 formed.
- the source-side control gate 315 and the drain-side control gate 316 are electrically coupled to one another.
- 3e shows the finished memory cell in cross section.
- FIG. 3f shows, for further illustration, two memory cells according to the invention arranged next to one another, like the one shown in FIG. 3e, from above.
- the substrate 100, 300 is an n-substrate.
- the channel area has a p-channel.
- 302 injection gate 302a polysilicon 302b tungsten 302c TEOS
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10138585A DE10138585A1 (en) | 2001-08-06 | 2001-08-06 | memory cell |
DE10138585 | 2001-08-06 | ||
PCT/DE2002/002759 WO2003017374A2 (en) | 2001-08-06 | 2002-07-26 | Memory cell |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1415349A2 true EP1415349A2 (en) | 2004-05-06 |
Family
ID=7694577
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02767055A Withdrawn EP1415349A2 (en) | 2001-08-06 | 2002-07-26 | Memory cell |
Country Status (8)
Country | Link |
---|---|
US (1) | US6998672B2 (en) |
EP (1) | EP1415349A2 (en) |
JP (1) | JP4481004B2 (en) |
KR (1) | KR100679775B1 (en) |
CN (1) | CN1539170A (en) |
DE (1) | DE10138585A1 (en) |
TW (1) | TW556320B (en) |
WO (1) | WO2003017374A2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7184315B2 (en) * | 2003-11-04 | 2007-02-27 | Micron Technology, Inc. | NROM flash memory with self-aligned structural charge separation |
US7202523B2 (en) | 2003-11-17 | 2007-04-10 | Micron Technology, Inc. | NROM flash memory devices on ultrathin silicon |
JP2008053270A (en) * | 2006-08-22 | 2008-03-06 | Nec Electronics Corp | Semiconductor memory device, and its manufacturing method |
KR100846393B1 (en) * | 2007-03-30 | 2008-07-15 | 주식회사 하이닉스반도체 | Transistor in semiconductor device and method for manufacturing the same |
Family Cites Families (24)
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JPS6418270A (en) * | 1987-07-13 | 1989-01-23 | Oki Electric Ind Co Ltd | Semiconductor memory device |
US5219774A (en) * | 1988-05-17 | 1993-06-15 | Xicor, Inc. | Deposited tunneling oxide |
US5270559A (en) * | 1990-10-15 | 1993-12-14 | California Institute Of Technology | Method and apparatus for making highly accurate potential well adjustments in CCD's |
US5284784A (en) * | 1991-10-02 | 1994-02-08 | National Semiconductor Corporation | Buried bit-line source-side injection flash memory cell |
JPH0613627A (en) * | 1991-10-08 | 1994-01-21 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
US5910912A (en) * | 1992-10-30 | 1999-06-08 | International Business Machines Corporation | Flash EEPROM with dual-sidewall gate |
US6057575A (en) * | 1996-03-18 | 2000-05-02 | Integrated Memory Technologies, Inc. | Scalable flash EEPROM memory cell, method of manufacturing and operation thereof |
US5963806A (en) * | 1996-12-09 | 1999-10-05 | Mosel Vitelic, Inc. | Method of forming memory cell with built-in erasure feature |
JP3264365B2 (en) * | 1997-03-28 | 2002-03-11 | ローム株式会社 | Non-volatile storage element |
US5900657A (en) * | 1997-05-19 | 1999-05-04 | National Semiconductor Corp. | MOS switch that reduces clock feed through in a switched capacitor circuit |
US6281545B1 (en) * | 1997-11-20 | 2001-08-28 | Taiwan Semiconductor Manufacturing Company | Multi-level, split-gate, flash memory cell |
US6091101A (en) * | 1998-03-30 | 2000-07-18 | Worldwide Semiconductor Manufacturing Corporation | Multi-level flash memory using triple well |
US6043530A (en) * | 1998-04-15 | 2000-03-28 | Chang; Ming-Bing | Flash EEPROM device employing polysilicon sidewall spacer as an erase gate |
US5991204A (en) * | 1998-04-15 | 1999-11-23 | Chang; Ming-Bing | Flash eeprom device employing polysilicon sidewall spacer as an erase gate |
US6093945A (en) * | 1998-07-09 | 2000-07-25 | Windbond Electronics Corp. | Split gate flash memory with minimum over-erase problem |
US6107139A (en) * | 1998-07-17 | 2000-08-22 | Worldwide Semiconductor Manufacturing Corporation | Method for making a mushroom shaped DRAM capacitor |
KR100297720B1 (en) * | 1998-10-19 | 2001-08-07 | 윤종용 | Flash memory cell and method of fabricating the same |
US6313500B1 (en) * | 1999-01-12 | 2001-11-06 | Agere Systems Guardian Corp. | Split gate memory cell |
JP3973819B2 (en) * | 1999-03-08 | 2007-09-12 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
US6228695B1 (en) * | 1999-05-27 | 2001-05-08 | Taiwan Semiconductor Manufacturing Company | Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate |
US6388293B1 (en) * | 1999-10-12 | 2002-05-14 | Halo Lsi Design & Device Technology, Inc. | Nonvolatile memory cell, operating method of the same and nonvolatile memory array |
JP2001148434A (en) * | 1999-10-12 | 2001-05-29 | New Heiro:Kk | Non-volatile memory cell and its usage, manufacturing method, and non-volatile memory array |
US6504207B1 (en) * | 2000-06-30 | 2003-01-07 | International Business Machines Corporation | Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same |
DE10036911C2 (en) * | 2000-07-28 | 2002-06-06 | Infineon Technologies Ag | Method for producing a multi-bit memory cell |
-
2001
- 2001-08-06 DE DE10138585A patent/DE10138585A1/en not_active Ceased
-
2002
- 2002-07-26 WO PCT/DE2002/002759 patent/WO2003017374A2/en active Application Filing
- 2002-07-26 KR KR1020047001792A patent/KR100679775B1/en not_active IP Right Cessation
- 2002-07-26 JP JP2003522178A patent/JP4481004B2/en not_active Expired - Fee Related
- 2002-07-26 CN CNA028154541A patent/CN1539170A/en active Pending
- 2002-07-26 EP EP02767055A patent/EP1415349A2/en not_active Withdrawn
- 2002-08-06 TW TW091117675A patent/TW556320B/en not_active IP Right Cessation
-
2004
- 2004-02-06 US US10/779,557 patent/US6998672B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
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See references of WO03017374A2 * |
Also Published As
Publication number | Publication date |
---|---|
JP4481004B2 (en) | 2010-06-16 |
WO2003017374A2 (en) | 2003-02-27 |
DE10138585A1 (en) | 2003-03-06 |
CN1539170A (en) | 2004-10-20 |
KR100679775B1 (en) | 2007-02-06 |
TW556320B (en) | 2003-10-01 |
US6998672B2 (en) | 2006-02-14 |
WO2003017374A3 (en) | 2003-05-30 |
US20040183125A1 (en) | 2004-09-23 |
KR20040023718A (en) | 2004-03-18 |
JP2004538662A (en) | 2004-12-24 |
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