DE4335834C2 - Non-volatile memory cell with an L-shaped floating gate electrode and method for its production - Google Patents

Description

The invention relates to a non-volatile memory cell with an L-shaped floating gate electrode and a process for its manufacture.

In general, memory devices are either volatile memory or non-volatile memory. With volatile memory, new information can be be stored, whereby stored, old information is deleted, while in the case of a non-volatile memory, "programmed" information is saved permanently.

RAM, which is representative of volatile memory is an array of memory cells that store information in binary form chern, whereby information each  in or out of any cell as needed can be sen. In other words, a RAM is a read / Write memory. On the other hand, in a ROM where it is a building representative of non-volatile storage element is "programmed" information in the memory filed, and only one read operation is carried out.

As a non-volatile memory are also an erasable, pro programmable ROM and an electrically erasable, program mierbaren ROM known, in which the stored informa tion can be deleted and new information can be programmed that can. Solceh EPROMs and EEPROMs are in terms of Programming process identical, but differ regarding the deletion process. In other words, that an EPROM can be erased by ultraviolet light can while an EEPROM can be erased electrically. However, an EPROM and EEPROM have the same basic principles Structure and the same basic operation.

When scaling down an EEPROM or an EPROM component many enter into the lower submicrometer range Difficulties on such. B. the that the degree of coupling and the programming speed is reduced. Accordingly, be there is a limit to the degree of integration.

Prior art EPROM and EEPROM devices are discussed below along with the difficulties encountered in order to gain a better understanding of the background of the invention. Reference is made to the accompanying drawings, initially to FIG. 4. It is a cross section showing the structure of a conventional EEPROM cell with a symmetrical structure. As shown in FIG. 4, such an EEPROM cell has a semiconductor substrate 11 which is insulated by an insulating film 12 from a floating gate 13 , which is covered by an interlayer insulating film 14 which insulates a control gate 15 from the floating gate , A source region 16 and a drain region 17 are formed in the substrate and are separated from one another by a channel region 18 which overlaps with the gate 13 .

Information is stored in the floating gate 13 , which lies on the channel region 18 formed in the substrate between the source region 16 and the drain region 17 . The mechanism for storing information is that when a voltage is applied to the control gate 15, hot electrons with high energy are generated in the channel region 18 and then through the applied to the control gate 15 electric field through the gate insulating film 12 through into the floating gate 13 injected and stored there. The information stored in the floating gate 13 can be deleted by irradiation of ultraviolet light.

However, the symmetrical EPROM cell in which both the source region 16 and the drain region 17 overlap with the channel region has a low degree of coupling, and only a small electric current is generated by hot electrons generated therein, which causes the problem has that the programming efficiency is reduced. In addition, to achieve a relatively strong gate current, a relatively high voltage must be applied to the control gate 15 for programming. However, an intricate external circuit is required to apply the high voltage to the control gate so that the degree of integration of the cell cannot be increased sufficiently.

The following is a detailed description of a conventional method for manufacturing a symmetrical EPROM device with reference to FIG. 5.

First, in a step A, a pair of gate oxide films 23 are formed over a p-type substrate 21 , on which a pair of gates 25 , control gates 29 and interlayer insulating films 25 are then formed between the gates 25 and the control gates 29 . Then, a thin insulating film is formed on the entire resulting structure.

Then, in a step B, a thick insulating film is deposited and then subjected to anisotropic etching in order to form spacers 33 on side walls of the gates.

Step C is performed to remove one of the spacers formed on the side walls of the gate. For this purpose, a photoresist film is applied over the entire structure and then subjected to a patterning process to form a photoresist pattern 35 , through which the spacer 33 formed on a side wall of the gate is exposed.

Finally, a source and a drain region are formed in a step D. Using the insulating film 31 as an etching stop, the exposed spacer 33 is removed by dry etching. Thereafter, the photoresist pattern 35 is removed, leaving the spacer formed on a side wall of the gate. Subsequently, high density n-type impurities are implanted in the substrate to form 37 and 39 in this impurity region. For example, the n ⁺ impurity region 37 acts as the source region of the memory cell, while the n ⁺ impurity region 39 acts as the drain region.

In a conventional EPROM component with a layer gate structure, the source region 37 is formed with such an asymmetrical structure that the source region 37 overlaps the gate, but the drain region 39 does not overlap it. In such an EPROM component with a layered structure, it is necessary to apply a high voltage to the drain region 32 for programming. The high voltage enables a strong gate current to flow, so that the programming speed is faster than that of the conventional symmetrical EPROM device.

However, the conventional method of manufacturing one Asymmetric EPROM device with a photoetching process a limitation on high integration density for Cells, since the gate by a conventional photoetching process cannot be set with submicron size.

In addition, as can be seen from Fig. 5, the coupling degree between the control gate and the floating gate is small, whereby there arises a problem that the programming efficiency is reduced.

Fig. 6 shows a cross section of a conventional asymmetrical EEPROM device. The component is formed on a substrate 41 in which a drain region 43 with a flat transition and a relatively deep source region are formed, which define a channel 44 between them. In this component, a gate insulating film 45 is formed over the channel region 44 , namely into the drain region 43 , overlapping with a part of the source region 42 . A floating gate 46 is formed over the gate insulating film 45 and is insulated from a control gate 48 by an interlayer insulating film 47 to provide high capacitance.

Although the conventional EEPROM cell has an asymmetrical structure, it differs from the asymmetrical EPROM component according to FIG. 5. That is, in the EEPROM component, the source region 42 and the drain region 43 individually overlap the gate, the former consists of a diffusion region 42-1 with a flat transition and a diffusion region 42-2 with a deep transition and the latter consists of a single, flat diffusion region.

In the conventional EEPROM structure, hot electrons are generated in the channel region 44 when the drain region 43 is supplied with a higher voltage than the source region 42 and the control gate 48 is supplied with a much higher voltage. These hot electrodes are then injected via the gate film 45 into the floating gate 46 and stored there. Accordingly, information is programmed into the EEPROM component.

An erasing process is carried out by switching the drain region 43 to potential-free and applying a high voltage to the source region 42 , the control gate 48 being kept at ground potential. Under this condition, tunneling takes place between the superimposed sections of the floating gate 46 and the source region 42 , so that the information stored in the floating gate 46 is deleted.

In the conventional EEPROM device, the capacitive coupling between the floating gate 46 and the STEU 48 plays ge an important role for defining the Ladungsmen ergate that are stored in the floating gate 46 and this can be removed. In other words, a strong gate current is generated when the capacitive coupling degree is large. Accordingly, the programming speed is increased.

Such an EPROM component, as shown in FIGS . 4, 5 and 6, is known from US 4,852,062.

Since as well as the floating gate and the control gate are present in such a conventional EEPROM device in the EPROM device shown in FIG. 5 as a planar structure, the length must be of the gate can be increased to the overlap area between the floating gate 46 and control gate 48 to increase. However, the length of the gate has an influence on the degree of integration of the component, so that there is a limitation for the size and accordingly the area of overlap between the gate is also limited. Accordingly, the coupling level decreases with increasing integration density, whereby the programming speed becomes slow.

A method for producing a non-volatile memory with the following steps is already known from US Pat. No. 5,138,573:

• - Deposition of a CVD oxide film over a semiconductor substrate from the first th line type; Photo-etch the CVD oxide film around a part of it leaving the substrate behind; Form a gate oxide film on the free one placed part of the substrate; Applying a first polysilicon film over the overall resulting structure; Etching back the first polysilicon film to form a floating gate; Implanting dopant fen of the second conductivity type into the substrate to form drain regions; Be sides of the CVD oxide film, application of an insulating film and a second Polysilicon film, etching of the second polysilicon film and the insulating film, to obtain a control gate covering the floating gate and the Otherwise expose substrate; Implanting dopants from the second Conduction type to form source areas; Apply an oxide film over the overall resulting structure, and anisotope etching back of the oxide film, to form spacers on both sides of the gate.

The US 5,138,573 thus shows a non-volatile memory, which is in the Potential-independent, essentially perpendicular to the substrate Gate, on which a U-shaped control gate is arranged so that the Control unit overlaps the floating gate. On the so constructed Side wall insulators are provided in the stack gate. A source area ho forth density of the second conductivity type is formed in the substrate so that it extends to the edge of the control gate, while the drain region ei A first area of high density, which is under the control gate to the Floa tinggate extends, and has a second high density region, which in the first area is formed and it extends to the edge of the control gate stretches.

Another non-volatile memory cell is known from JP 61-58272 A, where a floating gate is essentially perpendicular to the substrate stretches. An L-shaped control gate is formed on the floating gate so  that it has a long leg extending perpendicular to the substrate kel is adjacent to the floating gate, while it is with its short Schen kel on a gate insulating film on the substrate.

The invention has for its object a non-volatile memory cell admit that the degree of coupling improves significantly and the gate current is maximized, while the dimensions of the gate electrode in the lower submicron range, so that a high integration density can be achieved. Another object of this invention is a method of making egg specify such a non-volatile memory cell.

The above tasks are accomplished by the method according to the Claim 1 or by the non-volatile memory cell according to the Claim 2 solved.

The above and other objects and advantages of the invention will be apparent from the following description.

The description and the accompanying drawings illustrate embodiments Examples that only illustrate different ways in which the Principle of the invention can be realized.

The following is shown in the drawings:

Fig. 1 is a flowchart in the form of cross sections illustrating a method for manufacturing an asymmetrical EPROM device according to the invention;

Fig. 2 is a diagram showing gate currents versus gate voltages in a device according to the invention and a conventional device;

Fig. 3 is a diagram showing the relationship between the programming speed and programming paths for the invention and the prior art;

Fig. 4 is a schematic cross section of a conventional symmetrical EPROM device;

Fig. 5 is a flow chart in cross sections illustrating a method of manufacturing a conventional asymmetrical EPROM; and

Fig. 6 is a schematic cross section of a conventional asymmetric EEPPROM device.

In a step A illustrated by FIG. 1A, a thick CVD oxide film 53 is deposited over a p-type semiconductor 51 .

Then, in a step B, the CVD oxide film 53 is coated with a photoresist film, which is then subjected to a pattern formation process to leave a photoresist pattern 55 only in a portion in which a source region is to be formed in a later step. As a result, part of the CVD film is exposed.

Thereafter, the exposed CVD oxide film 53 is subjected to photoetching using the photoresist film as a mask in a step C, followed by formation of a gate insulating film 57 over the resulting substrate with the CVD film removed.

In a step D, a first polysilicon film 59 , an interlayer insulating film 61 and a second polysilicon film 63 are successively deposited entirely over the resulting structure.

In step E, an etch back process is carried out to form a gate 65 on a side part of the CVD oxide film, whereby there is a gate formed as a side wall. During this process, the first polysilicon film 59 is formed as a floating gate, while the second polysilicon film 63 is formed as a control gate.

Accordingly, the gate 65 has the floating gate 59 , the control gate 69 and the interlayer insulating film 61 formed therebetween, resulting in a large capacitance value. The floating gate 59 consists of a region 59-1 just formed on the gate insulating film 57 and a region 59-2 which extends along the side wall of the CVD oxide film 53 from the region 59-1 at right angles to the latter. The flat region 59-1 and the elongated region 59-2 have the same thickness.

The control gate 63 is structured so that it extends at right angles to the flat region 59-2 of the potential-free gate 59 in its longitudinal direction.

The interlayer insulating film 61 , which insulates the floating gate 59 from the control gate 61 , is interposed therebetween and is made of a thin film of a dielectric substance having an oxide-nitride-oxide structure.

According to the first polysilicon film 59 , the interlayer insulating film 61 and the second polysilicon film 63 are each formed with the desired thickness so that the length of the gate can be formed in the lower submicron range or below.

In a step F, n-dopants with a high density are diffused into the substrate using the CVD oxide film 53 and the gate 65 as a mask in order to form an n ⁺ diffusion region 67 with a flat transition therein. Such a diffusion region 67 forms a drain region which deletes the information stored in the floating gate 59 .

In the following, as can be seen from a step G, spacers are formed. For this purpose, the CVD oxide film 53 is removed, followed by the deposition of an oxide film over the entire surface of the resulting structure. The oxide film is then anisotropically etched to form spacers 69 and 70 on the side walls of the gate 65 . While a spacer 69 is formed on one side wall of the gate 65 , the other spacer 70 is formed on the other side wall of the gate 65 .

Finally, in a step H, using the gate 65 and the spacers 69 and 70 as a mask, n-dopants are implanted with high density in the substrate in order to create diffusion regions 71 and 72 with a deep transition.

The diffusion region 71 , which forms a source region, is removed from the gate by the thickness of the spacer 69 . The diffusion region 72 , which forms the drain region together with the diffusion region with a flat transition, is at a distance from the gate by the thickness of the spacer 70 .

As for the drain region, it consists of the diffusion region 67 with a flat transition and high foreign matter density, which lies below the floating gate 59 , and the diffusion region with a deep transition and high foreign matter density, which is subsequently formed on the diffusion region 67 with a flat transition is that gate 65 partially overlaps the drain region. On the other hand, the source region consists only of the diffusion region with a deep transition with a high impurity density, which does not overlap with the potential-free gate. Accordingly, the source region and the drain region have an asymmetrical structure.

The one produced by the method according to the invention is not volatile memory has the following: a semiconductor sub strat of the first line type; one on the substrate formed gate insulating film; a floating gate that is out consists of two integrally manufactured areas, of which the  one lies flat on the gate film and the other of an end region of the first region perpendicular to this extends, a longitudinally extending control gate over the other end part of the flat area of the potential-free gates and is perpendicular to the flat Be stands rich; an interlayer insulation that between the floating gate and the control gate is arranged and provides great capacity; a pair of spacers, from which one on a side wall of the extended area of the floating gate is formed and the other on the side wall is formed, which consists of the floating Gate and control gate; a source area higher Density of the second conductivity type, which is formed in the substrate is and by the thickness of the former spacer from the pot zero gate is removed; a first drain area high density of the second conductivity type, which out in the substrate forms and under the floating gate with this overlaps; and a second high density drain region of second conduction type, the thickness of the latter Ab is removed from the floating gate and subsequent to the first high density drain region.

In the EEPROM component according to the invention, information is programmed into the potential-free gate 59 by the gate current generated in the source region 71 , whereas deletion is achieved in that the charge carriers stored in the potential-free gate are drawn into the drain regions 67 and 72 .

In FIG. 2 gate currents are shown depending on the gate voltages at a the present invention and a conventional device. As shown in Fig. 2, the component according to the Invention is superior to the conventional component in terms of gate current.

Fig. 3 is a diagram showing the relationship between the program speed and the program paths for the invention and the prior art. From the figure it can be clearly seen that the programming speed in the invention is excellent.

As described above, a conventional one non-volatile memory with a layer structure the control gate flat above the floating gate, which means that only the Bottom of the control gate with the top of the potential free gates overlap, making the degree of coupling low is. In contrast, is non-volatile in the invention Store the floating gate in an L-shape, which means that it can overlap two surfaces of the control gate, d. H. With the underside and one side surface of the control gate, so that the degree of coupling is improved.

In addition, the source region does not overlap with it below half of the gate, but is spaced from it by the thickness of the spacer, which contributes to the asymmetrical structure of the non-volatile memory, together with the fact that the drain region extends below the gate, thereby the gate current can be maximized. Accordingly, a high programming speed is possible even with low voltage, as shown in FIGS . 2 and 3 Darge.

Furthermore, the floating gate and the control gate according to the invention by a conventional etching process on the Sidewall in the lower submicrometer range or below be formed. In addition, the invention a drain region with a flat transition is formed, without a conventional process for eliminating Ab is required, which increases the degree of integration of the component can be improved.

Claims (6)

1. A method for producing a non-volatile memory cell with the following steps:

• - depositing a CVD oxide film ( 53 ) over a semiconductor substrate ( 51 ) of the first conductivity type;
• - Photoetching the CVD oxide film ( 53 ) to leave a part of it on the semiconductor substrate ( 51 );
• - Forming a gate oxide film ( 57 ) on the exposed part of the semiconductor substrate ( 51 );
• - successively applying a first polysilicon film ( 59 ), an insulating film ( 61 ) and a second polysilicon film ( 63 );
• - Etching back the first polysilicon film ( 59 ), the insulating film ( 61 ) and the second polysilicon film ( 63 ) to form a gate stack which consists of a floating gate electrode ( 59 ) on a side wall of the CVD oxide film ( 53 ), an interlayer insulating film ( 61 ) and a control gate electrode ( 63 ), the floating gate electrode ( 59 ) being L-shaped and having two regions ( 59-1 , 59-2 ), of which a flat region ( 59-1 ) is connected to the gate oxide film ( 57 ) and another region ( 59-2 ) extends from a first end portion of the flat region ( 59-1 ) at right angles to the flat region ( 59-1 ), the control gate electrode ( 63 ) extends in the longitudinal direction and over a second end portion of the flat portion ( 59-1 ) of the floating gate electrode and perpendicular to the flat portion ( 59-1 ), and the interlayer insulating film ( 61 ) between the floating gate electrode ( 59 ) and the S expensive gate electrode ( 63 ) and ensures a large capacity;
• - implanting dopants of the second conductivity type in the semiconductor substrate ( 51 ) in order to achieve a drain region ( 67 ) of high density with a flat transition;
• - removing the CVD oxide film ( 53 );
• - applying an oxide film over the entire resulting structure;
• - anisotropically etching the oxide film to form spacers ( 69 , 70 ) on both sides of the gate stack; and
• - Implanting dopants of the second conductivity type into the semiconductor substrate ( 51 ) in order to produce a source region ( 71 ) of high density with a low transition and a drain region ( 72 ) of high density with a low transition.

2. Non-volatile memory cell with:
a first conductivity type semiconductor substrate ( 51 );
a gate insulating film ( 57 ) formed on the semiconductor substrate ( 51 );
a potential-free gate electrode ( 59 ) which is L-shaped and has two regions ( 59-1 , 59-2 ), of which a flat region ( 59-1 ) adjoins the gate insulating film ( 57 ) and another region ( 59 -2 ) extending from a first end portion of the flat portion ( 59-1 ) perpendicular to the flat portion ( 59-1 );
a control gate electrode ( 63 ) extending longitudinally and overlying the second end portion of the flat region ( 59-1 ) of the floating gate electrode ( 59 ) perpendicular to the flat region ( 59-1 );
an interlayer insulation ( 61 ) which lies between the floating gate electrode ( 59 ) and the control gate electrode ( 63 ) and ensures a large capacitance;
a pair of spacers ( 69 , 70 ), of which the first spacer ( 69 ) is adjacent to a side wall of the other region ( 59-2 ) of the floating gate electrode ( 59 ) and the second spacer ( 70 ) is adjacent to the flat region ( 59- 1 ) the floating gate electrode ( 59 ) and the control gate electrode ( 63 ) adjoins;
a high density and second conductivity type source region ( 71 ) formed in the semiconductor substrate ( 51 ) and spaced from the floating gate electrode ( 59 ) by the thickness of the first spacer ( 69 );
a first high density drain region ( 67 ) which extends below the floating gate electrode ( 59 ); and
a second drain region ( 72 ) of the second conductivity type, which is located by the thickness of the second spacer ( 70 ) from the floating gate electrode ( 59 ) and is then adjacent to the first high density drain region ( 67 ). 3. The non-volatile memory cell according to claim 2, wherein the depth of the transition in the second drain region ( 72 ) is as deep as that in the source region ( 71 ), but deeper than that in the first drain region ( 67 ). 4. Non-volatile memory cell according to one of claims 2 or 3, characterized in that the first drain region ( 67 ) serves as a path for erasing information stored in the floating gate electrode ( 59 ). 5. Non-volatile memory cell according to one of claims 2 to 4, characterized in that a lower surface and a side surface of the control gate electrode ( 63 ) on the surface of the flat region ( 59-1 ) and on a side surface of the other region ( 59-2 ) of the floating gate electrode ( 59 ). 6. Non-volatile memory cell according to one of the preceding claims, characterized in that the flat region ( 59-1 ) and the other loading region ( 59-2 ) of the floating gate electrode ( 59 ) have the same thickness.