DE102005006734A1 - Fabrication of split-gate transistor involves forming control gate structure conforming to side surface and including projecting portion that extends over portion of floating gate structure - Google Patents

Abstract

Split-gate transistor is fabricated by forming a control gate structure adjacent to an intermediate insulating structure. The control gate structure conforms to a side surface of intermediate insulating structure, and includes a projecting portion that extends over a portion of a floating gate structure. Fabrication of split-gate transistor involves forming an insulating structure having a sidewall surface with a concave region and a protruding region, which is positioned below the concave region. A semiconductor layer is etched using the protruding region of the insulating structure as an etch mask to form a floating gate structure (104a). An insulating layer is formed on the floating gate structure to form an intermediate insulating structure incorporating the floating gate structure and having a side surface. The side surface includes a concave region. A control gate structure (120) is formed adjacent to the intermediate insulating structure. The control gate structure conforms to the side surface and includes a projecting portion that extends over a portion of the floating gate structure. Independent claims are also included for: (a) method of forming a non-volatile split-gate memory cell; and (b) semiconductor memory cell comprising a split-gate cell structure. method of forming the non-volatile split-gate memory cell comprising: (i) forming a first insulating layer on a substrate (100); (ii) forming a first semiconductor layer on the first insulating layer; (iii) forming a second insulating layer on the first semiconductor layer; (iv) forming a third insulating layer on the second insulating layer; (v) patterning and etching the third insulating layer to form an opening of vertical sidewalls that exposes a portion of the second insulating layer; (vi) oxidizing a portion of the first semiconductor layer to form a semiconductor oxide layer; (vii) depositing a sidewall material layer; (viii) etching the sidewall material layer using an anisotropic etch to form spacers adjacent the sidewalls of the opening and to expose a portion of the semiconductor oxide layer; (ix) etching the exposed portion of the semiconductor oxide layer to expose a portion of the first semiconductor layer; (x) etching the exposed portion of the first semiconductor layer to expose a portion of the first insulating layer; (xi) implanting a dopant species through the exposed portion of the first insulating layer to form a source region in a portion of the substrate; (xii) depositing a fourth insulating layer to a thickness to fill the opening; (xiii) removing an upper portion of the fourth insulating layer to expose a surface of the third insulating layer and produce a planar surface; (xiv) removing the third insulating layer and the spacers to form an insulator structure having sidewalls that include a recessed area; (xv) removing the second insulating layer; (xvi) etching the first semiconductor layer using a remaining portion of the semiconductor oxide layer to expose the first insulating layer and form first conductor elements; (xvii) forming a fifth insulating layer on the first conductor elements; (xviii) depositing a second semiconductor layer for conforming to a surface of the insulator structure and filling the recessed area in the sidewalls; (ixx) etching the second semiconductor layer to form semiconductor spacers adjacent to the sidewalls of the insulator structure and expose a portion of the first insulating layer, in which each semiconductor spacer is a second conductor element that is paired with and partially overlays a corresponding first conductor element; (xx) implanting a dopant species through the exposed portion of the first insulating layer to form a drain region in the substrate; (xxi) depositing a sixth insulating layer to insulate the second conductor element; and (xxii) establishing separate electrical connections to the source region, the drain region and the second conductor element.

Description

The The invention relates to a method for producing a transistor gate structure, in particular a split-gate transistor structure, according to the preamble of claim 1 and to a corresponding transistor gate structure, especially for a semiconductor memory cell.

Semiconductor memory cells the floating gate electrodes which change the behavior of it linked Channel areas can be loaded, and control gate electrodes are used in a variety of ways Configurations made. Such memory cells are used for Formation of non-volatile Memory cell arrays and corresponding memory devices used, in which stored data for a relatively long period of time can be saved without To consume power or to require frequent refresher. such Components are especially for Beneficial for applications where performance is not available for extended periods of time or interrupted more often is, or in battery-dependent Applications where low power consumption is desired.

Accordingly devices of this type are often found in applications such as mobile communication equipment, Memory blocks, which are built in microprocessor or microcomputer chips, and in stores used to store music and / or image data become. The floating gate memory cells may be in split gate or stacked gate configurations being realized, being also a combination of the two configurations can be contained in a single component.

Memory cell transistors with Splitgate, d. H. Split gate, offer some advantages over conventional ones Flash memory, such as byte mode, d. H. Write and delete with eight bits, relatively low programming currents of about 1 μA, good resistance against interference with the control gate in use as a selection transistor and higher Operating speeds through the use of an injection of hot carriers. Split gate memory cell transistors However, they also have some issues, such as larger size in comparison to a corresponding flash memory cell and lower resistance as a corresponding electrically erasable and programmable read-only memory (EEPROM), which is a charge carrier injection through Fowler-Nordheim (F-N) tunnels used.

A with the production of memory cell arrays with floating gate electrodes linked difficulty is the alignment of the different functional elements including the Source, drain, control gate and floating gate regions. Because the Design rules for higher Integration densities the dimension and spacing of these different ones As items continue to decrease, the need for accurate and increased demand increases controllable adjustment. A suitable relative adjustment and orientation of different memory cell elements results in an increased production yield, a reduced dispersion of performance and increased reliability the final Semiconductor products.

self-adjustment is a well known technique in semiconductor manufacturing and includes certain process steps for arranging and configuring the resulting structures such that certain elements, such as CMOS gate electrodes and adjacent source / drain regions, automatically as a result of the special process sequence aligned with each other so do not rely on the adjustment of multiple photolithography patterns must be trusted.

In the split-gate memory cell configuration, the control gate field effect transistor (FET) plays a major role in determining the programming injection efficiency for memory cells with source side injection. Good control of the control gate length L _cg , also referred to as word line (WL) poly length, ie, the length of the control or select gate located above the channel region, can provide complete shutdown of the control gate device and the risk of interference Reduce interference during programming of mirror-image cells.

One difficulty associated with the manufacture of split-gate memory cells is also a possible mismatching of the lengths and positions of the paired control gate electrodes. As in 1 , which will be discussed in detail below, are typically two control gate electrodes 120 on both sides of a common source area 116 and over part of a channel between the source region 116 and an associated drainage area 126 arranged. If the associated control gate lengths L _cg1 and L _{cg2 are} not nearly identical, the difference between Source 116 and drain 126 flowing amount of electricity, so that the operation of the two mirror-image cells varies accordingly.

Data may be obtained in such a split-gate memory cell by utilizing the changes in the current flowing across the respective transistors as a function of the state of the floating gate electrodes 104a ie depending on whether these are loaded or programmed or unloaded or deleted. During a load / program operation, electrons may enter the floating gate 104a For example, by applying a relatively high voltage of about 8V to about 12V to the common source electrode, an intermediate voltage of about 1V to about 3V to the corresponding control gate 120 and a relatively low voltage of about 0V to about 0.5V to the corresponding drain electrode 126 while the substrate 100 near ground, ie 0V. With increasing accumulation of electrons in the floating gate 104a due to the resulting mechanism of injection of hot channel electrons (CHEI mechanism), the effective threshold voltage V _{th of} the transistor typically rises above about 3V.

Conversely, during a discharge / erase operation, electrons may leak from the floating gate 104a be deducted, for example, by applying a relatively high voltage of about 8V to about 12V to the control gate 120 while the common source 116 , the associated drain 126 and the substrate 100 at or near ground, ie 0V. With increasing discharge of the floating gate electrode 104a of accumulated electrons across the resulting FN tunneling mechanism, the effective threshold voltage _Vth typically decreases to a value below about 1V, or even below 0V.

Once the splitgate memory cell of 1 programmed or cleared, it can by applying a read voltage of about 2V to the control gate 120 and a voltage of about 1V to the drain 126 be read, the source 116 and the substrate 100 at or near ground, ie 0V. When the floating gate is charged when reading, the threshold voltage V _{th is} so far above the read voltage that the transistor remains turned off. Conversely, if the floating gate is discharged during reading, the threshold voltage V _{th is} so far below the read voltage that it is ensured that the transistor is turned on. It will be appreciated that the sizing and doping of the split-gate transistor elements are chosen taking into account the required performance of the final semiconductor product and determine the exact voltage and current ranges needed to operate such a transistor.

How out 1 As can be seen, the split-gate memory cell generally has a structure in which the divided floating gate electrodes 104a and the associated split control gate electrodes 120 on opposite sides of the common source region 116 are arranged, wherein the floating gate electrodes 104a and the control gate electrodes 120 separated from each other by one or more insulating materials. The floating gate electrodes 104a are also electrically isolated from surrounding power sources by external power sources.

An insulation material 200 between substantially vertical parts of the floating gate electrode 104a and the control gate electrode 120 that is, substantially laterally between these gate electrode portions is also referred to as an inter-gate insulation layer, tunnel insulator, or tunnel oxide. An insulation material 204 between the floating gate electrode 104a and the substrate 100 is also referred to as a coupling isolator or coupling oxide. Analog becomes an insulation material 206 between the control gate 120 and the substrate 100 referred to as a gate insulator or gate oxide. The insulation materials 204 and 206 Kings nen formed, for example, in different steps during the manufacturing process of the transistor and accordingly be slightly different in their composition and / or thickness. An insulation material 202 between the top of the floating gate electrode 104a and the control gate 120 is also referred to as intermediate polyoxide (IPO).

Each of the insulating areas 200 . 202 . 204 . 206 has an associated capacitance C _tun , C _IPO , C _c and C _g , respectively, which contribute to a total capacitance C _{tot of} the split-gate transistor. These capacitances also affect the voltage applied to the floating gate 104a can be applied to generate the electric field that generates the hot electrons during charging / programming operation and leads to the floating gate. During the programming step, the floating gate hangs 104a induced voltage V _fg generally coincides with the common source applied voltage V _s according to Equation I below. V fg = V s · (C c / C dead ) (I)

Accordingly, the value C _c / C _{tot is} a factor that must be considered in the design of the split-gate transistor. Higher values C _c / C _tot allow inducing higher voltages in the floating gate to increase the electron injection efficiency, ie the programming efficiency, of the transistor.

During a discharge / erase operation, electrons from the floating gate move through the tunnel insulation layer by FN tunneling 200 and / or the intermediate polyoxide 202 through to the control gate 120 , In this case, it corresponds to the floating gate 104a voltage V _fg generally applied to the control gate 120 applied voltage V _cg according to the following equation II: V fg = V cg · ((C dead - C IPO - C G ) / C dead ) (II)

Therefore, for improved performance, it is desirable to increase the capacitance C _IPO and thereby reduce the effective voltage at the floating gate V _fg . A decrease in the voltage V _fg during discharges affects the life characteristics of the memory cell and the electron discharge efficiency. In addition, using the FN tunneling mechanism, the tunneling current can be reduced by electron trapping sites within the insulating layers, thereby lowering the performance of the device. This degradation can be somewhat suppressed by increasing the effective voltage of the floating gate electrode.

The relationship between the capacity contributions C _do , C _{IPO of} the tunnel insulator 200 and the intermediate polyoxide 202 and the behavior of the floating gate can also be expressed by the following coupling ratio α according to Equation III below: α = (C do + C IPO ) / C dead (III)

Specific corresponding manufacturing processes and the resulting structures of the floating gate electrode are described, for example, in the patents US 6,329,685 . US 6,362,048 . US 6,429,472 . US 6,486,508 . US 6,524,915 . US 6,562,673 and US 6,589,842 and US Pat. No. 2002/0034846 A, the contents of which are hereby incorporated by reference herein for further details.

Of the Invention is the technical problem of providing a Method for producing a transistor gate structure of the beginning mentioned type and the provision of a corresponding transistor gate structure underlying with which the above-mentioned difficulties of the state let the technology at least partially avoid and in particular high programming / erasing efficiency, good lifetime properties and high uniformity from component to component enable.

The Invention solves this problem by providing a method with the Features of claim 1 and a transistor gate structure with the Features of claim 29 or 32

advantageous Further developments of the invention are specified in the subclaims, the text of which is hereby expressly is incorporated by reference into the description.

According to the invention is a Self-adjustment of the control gate electrodes and floating gate electrodes provided with a high level of Controllability of tunnel and Zwischenpoly isolations achievable is. The improvements in the manufacturing process and in the manufactured Structure have one opposite the aforementioned State of the art improved programming / erasing efficiency and good fatigue life and device reproducibility.

The In particular, the invention also encompasses a process for the production complementary floating gate and control gate structures with the following steps: Forming an insulation structure with a side wall surface, the a concave part and a protruding part positioned below it Part includes; Use the protruding part of the isolation structure as an etching mask; Etching one Semiconductor layer for forming a floating gate structure; Form an isolation layer on the floating gate structure for generation an intermediate insulation structure having a side surface, the has a concave area; and forming a control gate structure adjacent to the intermediate isolation structure, wherein the control gate structure conform to the side surface and having a protruding part extending over part of the floating one Gate structure extends.

advantageous embodiments The invention is illustrated in the drawings and will be described below described. Hereby show:

1 a schematic cross-sectional view of a split-gate transistor structure and

2A to 2M schematic cross-sectional views for illustrating successive process steps of a method for producing the split-gate transistor structure of 1 ,

1 shows a split gate transistor structure according to the invention, by a in the 2A to 2M illustrated, inventive method can be produced. To better illustrate the invention, the drawings are not to scale. Insofar as it is explained below that layers or structures are arranged "on" or "above" another layer or structure or a substrate, this includes the possibility that the layer or structure may be directly or interspersed with one or more other layers or structures the layer or structure or the substrate is arranged. Likewise, terms such as "under,""adjacent," and "adjacent," etc. are to be understood as meaning that the elements associated therewith are directly adjacent to, adjacent to, or side by side there are one or more other elements in between.

Hereinafter, the production of the split-gate transistor structure of 1 with additional reference to the 2A to 2M explained in more detail.

First, at the initial stage of the process 2A a semiconductor substrate 100 , z. B. p-type silicon, provided and a first insulating layer 102 , z. For example, a silicon oxide layer having a thickness of typically between about 5 nm and 15 nm is formed thereon by oxidation of the substrate or by a deposition process. A first polysilicon layer 104 with a thickness of typically between about 50 nm and 150 nm is deposited on the first insulating layer 102 educated. In view of its intended use, the first polysilicon layer 104 also be referred to as a floating poly or FPoly. On the first polysilicon layer 104 becomes a second insulation layer 106 typically a thin silicon oxide layer having a thickness of about 3 nm to about 10 nm, for example formed by oxidizing a portion of the first polysilicon layer.

Subsequently, on the second insulation layer 106 a third insulation layer 108 , z. For example, a silicon nitride layer having a thickness of between about 200 nm and about 300 nm is formed, typically using a chemical vapor deposition (CVD) process such as low pressure CVD (LPCVD) and plasma assisted CVD (PECVD), or other suitable deposition process , On the third insulation layer 108 A photoresist layer, not shown, is formed and then exposed and developed to produce a photoresist pattern that forms part of the third insulating layer 108 exposes. The exposed part of the third insulation layer 108 is then used to create an opening or trench 110 etched, the or a part of the second insulating layer 106 exposes. The etching process used is preferably one which has a relatively high selectivity of z. B. greater than ten for the third insulation layer 108 relative to the second insulation layer 106 shows.

In the process stage of 2 B becomes the exposed part of the second insulation layer 106 and more particularly, the underlying portion of the poly silicon layer 104 subjected to additional oxidation to a fpoly oxide region 112 Among other things, it includes certain bird's-beak areas of reduced thickness located below the edges of the inside of the opening or trench 110 exposed third insulation layer 108 extend. The FPoly oxide 112 typically has a thickness between about 50 nm and 150 nm and may be more than half the thickness of the FPoly 104 during the oxidation process.

In the process stage of 2C becomes a second, substantially conformal polysilicon layer 114 over the third insulation layer 108 and the FPoly oxide 112 deposited. The second polysilicon layer 114 typically has a thickness between about 150 nm and 300 nm.

In the process stage of 2D becomes the second polysilicon layer 114 subjected to an anisotropic etching process, such as a reactive ion etching (RIE) process, to polysilicon spacers 114a on the sides of the opening or trench 110 to create. The polysillicon spacers 114a have on their underside a width w of typically between about 0.15 microns and 0.25 microns and thus cover a peripheral part of the FPoly-oxide 112 , The intermediate part of the polysilicon layer 114 in the central area of the ditch 110 is removed during spacer formation, so that a corresponding portion of the FPoly-oxide 112 is exposed.

In the process stage of 2E becomes the exposed part of FPoly-oxide 112 removed so that the underlying part of FPoly 104 is exposed, with remaining parts of the FPoly-oxide 112a under the spacers 114a remain. In the process stage of 2F becomes the exposed part of FPoly 104 removed, leaving the underlying part of the first insulation layer 102 is exposed. The for removing the exposed part of FPoly 104 The used etching process also tends to be the polysilicon spacers 114a reduce, thereby reducing polysilicon spacers 114b on the side walls of the trench 110 arise. The selectivity of this etching process with respect to the exposed polysilicon areas 104 and 114a and the first insulation layer 102 and the relative thickness of the insulating layer determine how much of the polysilicon spacers 114a is removed during this etching process and by how much its underside width w is reduced. The final underside width w is typically on the order of 0.1 μm.

As in 2F is illustrated after removal of the exposed portion of the FPoly layer 104 an implantation of dopants in the substrate, for. B. an n-type dopant such as As or P with a dose in the order of about 10 ¹⁵ ions / cm ² at an energy of about 40 keV, around the common source region 116 for the transistors to produce.

In the process stage of 2G After completion of the source implantation, a thick silicon oxide layer (not shown) will result deposited the structure, and with a thickness sufficient to completely fill the trench 110 sufficient, z. A thickness of the order of about 1500 nm. The top portions of this silicon oxide layer are then typically removed using a chemical mechanical polishing (CMP) process to form the top of the third insulating layer 108 expose. The remaining part of the silicon oxide layer forms an isolated oxide structure 118 the ditch 110 completely filled.

In the process stage of 2H becomes after formation of the oxide structure 118 the third insulation layer 108 away. If the third insulation layer 108 is formed of silicon nitride, it may, for. B. by a wet etching process with a hot aqueous solution of phosphoric acid (H ₃ PO ₃ ), typically at a temperature of more than 150 ° C, are removed. After removing the third insulation layer 108 are the reduced polysilicon spacers 114b exposed and can z. B. by a wet etching process with an aqueous solution of ammonium hydroxide (NH ₄ OH) are removed. The exposed portions of the resulting structure comprise the oxide structure 118 and the remaining parts of the second insulation layer 106 ,

In the process stage of 2I become the remaining parts of the second insulation layer 106 removed, typically using a wet etching process or a dry etching process, so that the underlying part of the FPoly layer 104 is exposed. Depending on the etching composition, the remaining parts of the second insulating layer 106 also during the removal of the reduced polysilicon spacers 114b to be removed. After removing the remaining parts of the second insulation layer 106 become the exposed parts of the FPoly layer 104 using the oxide structure 118 etched as an etching mask, whereby an underlying portion of the first insulating layer 102 is exposed. The remaining parts of the FPoly layer 104 then form the floating gate structures 104a ,

In the process stage of 2J becomes on the exposed surfaces of the oxide structure 118 and the floating gate structures 114a an insulating oxide layer, typically having a thickness of about 5 nm to about 15 nm, formed by a thermal oxidation and / or a CVD process around the floating gate structures 104a to isolate and create a gate oxide layer. A polysilicon layer, not shown, is deposited on the resulting structure to a thickness of about 200 nm to about 400 nm and subjected to an anisotropic etchback process, such as an RIE process, to control gate structures 120 adjacent to the oxide structure 118 to build. The tax estate structures 120 , Who also referred to as word line polysilicon who can, have a lower-side length L, extending from the tunnel oxide 200 outward in the region above the channel region of the substrate 100 extends. This under-side length L can be controlled by the thickness of the deposited polysilicon layer, the etch chemistry, and the amount of over-etching, if necessary, to provide a corresponding degree of sizing control. Typically, the underside length L is in the range of about 0.20 μm to about 0.35 μm.

In the process stage of 2K become weakly doped drain regions (LDD regions) 122 in the substrate 100 using the oxide structure 118 and the control gate structures 120 generated as an implantation mask. Like the common source area 116 can the LDD areas 122 by implanting one or more different n-type dopants, such as As and / or P, at an energy of about 40 keV, but at a reduced dose of about 10 ¹³ ions / cm ² , to form n ^- type drain regions ,

After the formation of LDD areas 122 is in the process stage of 2L deposited an oxide layer, not shown, on the resulting structure and subjected to an anisotropic etch back process, such as an RIE process, to oxide spacers 124 on the sidewalls of the control gate electrodes 120 to create. Using the oxide structure 118 , the tax estate structures 120 and the oxide spacer 124 as an implantation mask, an additional, stronger implantation of n-type dopants, such as As or P, into the substrate takes place 100 to form n ⁺ -type drain regions 126 typically using a combination of implantation energy and implantation dose, which generally corresponds to that used to form the common source region. These concentrated drain areas 126 may also be referred to as n ⁺ -type bit line transitions.

In the process stage of 2M becomes after the formation of the n ⁺ -type drain regions 126 a thick oxide layer 128 typically made of CVD oxide having a thickness of about 1,000 nm to about 1,500 nm, deposited on the resulting structure. This oxide layer 128 can z. B. be planarized by a CMP process to provide a structurally more suitable surface. A photoresist layer, not shown, is then placed on the oxide layer 128 formed, exposed and developed to produce a contact pattern, the parts of the oxide layer 128 exposes. The exposed parts of the oxide layer 128 are etched to create contact openings extending to the source region 116 , to the drainage areas 126 or to the control gate electrodes 120 extend. After removal of the photoresist pattern, the contact openings with a or a plurality of conductive materials, typically including an initial barrier metal having a combination of Ti and TiN followed by the deposition of another metal layer, such as W, that fills the remainder of the contact openings. Subsequently, a CMP process for removing the upper parts of the metal layer and forming contact pins 130 which provide electrical connections to underlying elements. One possible process using tungsten may be e.g. Example, the deposition of a tungsten layer having a thickness of about 200 nm to about 300 nm followed by a tungsten-CMP process, with the top of the thick oxide 128 is exposed so that tungsten pins are formed in the contact holes.

After filling the contact openings with conductive material is on the resulting structure, a further metal layer, for. As aluminum or an aluminum alloy formed. This metal layer is patterned and etched to form a layer for metal interconnects 132 to build. Depending on requirements, additional, not shown, metallization layers may be formed, for which purpose an intermediate insulation layer (not shown) is applied, through-holes for the first layer of the metallic interconnects 132 introduced and not shown conductive contact pins and a second layer of metallic interconnects, not shown, are formed.

As will be apparent from the above explanation, in the case of the illustrated embodiment, the invention provides by controlling the formation of the first polysilicon spacers 114a standing on the floating gate 104a formed insulating layers) and the control gate structures 120 an improved level of controllability of the relative dimension and positioning of the floating gate electrode 104a and the control gate electrode 120 and the insulating materials disposed between the control gate and the floating gate. This improved controllability coupled with the self-aligned configuration provides a method for fabricating split-gate memory devices with more consistent performance and improved efficiency. In addition, the improved control over the relative dimensions of the gate structures allows fabrication of devices with increased program / erase efficiency and improved lifetime characteristics.

Claims (37)

Method for producing a transistor gate structure, in particular a split-gate transistor structure, having a floating gate structure ( 104a ) and a tax register structure ( 120 ), in which - the floating gate structure ( 104a ) on a base ( 100 . 102 ), - an insulating gate interlayer ( 200 . 202 ) covering an exposed surface of the floating gate structure, and the control gate structure (FIG. 120 ) is formed on the insulating gate interlayer, characterized in that - the control gate structure ( 120 ) is formed on a side wall of an insulating structure such that it is disposed with a lower part adjacent to the floating gate structure and extends with a protruding part at least partially over the floating gate structure. The method of claim 1, further characterized in that the formation of the isolation structure, the floating gate structure, the gate insulating interlayer, and the control gate structure comprises the steps of: forming a semiconductor layer; 104 ) on the base ( 100 . 102 ), - forming the isolation structure ( 118 ) having a side wall surface having a concave portion and a laterally protruding portion below the concave portion, over the semiconductor layer (FIG. 104 Etching the semiconductor layer using the projecting portion of the insulating structure as an etching mask to form the floating gate pattern, forming the gate insulating interlayer, and forming the control gate structure with the protruding part at least partially over the floating gate pattern conforming to the side surface of the insulating structure , Method according to claim 2, further characterized by the following steps: - forming a common source region ( 116 ) in a substrate ( 100 ) of the substrate before forming the insulation structure ( 118 ), - forming a drain region ( 126 ) in the substrate after forming the control gate structure, - forming a thick insulating layer ( 126 after the formation of the drain region and forming a plurality of contact openings through the thick insulating layer to provide separate electrical contacts to the common source region, the drain region and the control gate structure. The method of claim 3, further characterized by the following steps: applying a Ti layer in the contact openings, applying a TiN layer on the Ti layer in the contact openings, applying a W layer on the TiN layer in the contact openings and - planarizing the surface to expose a top of the thick insulation layer and wolf ram contact pins which fill the contact openings. The method of claim 3 or 4, further characterized characterized in that the formation of the insulation structure with the concave sidewall region applied a nitride layer, a trench formed in the nitride layer and on a side wall of the trench forming a spacer sacrificial layer of polysilicon, the remaining trench filled with silicon oxide and the silica for Exposing a top of the nitride layer is planarized and the nitride layer and the sidewall spacer made of polysilicon be removed. Method according to one of claims 3 to 5, further characterized characterized in that the formation of the laterally projecting portion the isolation structure comprises the following steps: - Form a polysilicon layer and a nitride layer and generating a Trench in the nitride layer, Oxidizing a part of the Polysilicon layer for producing a silicon oxide region, the extends below an edge region of the nitride layer. - filling the remaining trench with silica and planarizing the silica for exposing an upper surface of the nitride layer and - Remove the nitride layer and a silicon oxide deposition layer formed under the nitride layer. Method according to one of claims 1 to 6, further characterized characterized in that the projecting portion of the insulation structure with a rejuvenated End region is formed, to which the floating gate structure with complies with their top, so that in this area an upward projection of the floating gate structure is formed. The method of claim 1, further characterized in that the formation of the isolation structure, the floating gate structure, the gate insulating interlayer, and the control gate structure comprises the steps of: - forming a mask structure (FIG. 108 ) on a substrate ( 100 ), wherein the mask structure has a trench ( 110 ) having a substantially vertical side wall which forms part of an insulating layer ( 112 ) exposed on a semiconductor layer ( 104 ), - forming a polysilicon spacer ( 114a ) on the trench sidewall, - removing the exposed part of the insulating layer and an underlying part of the semiconductor layer and a part of the polysilicon spacer, so that a reduced polysilicon spacer ( 114b ), and the trench is enlarged, filling the enlarged trench with silicon oxide, removing the mask pattern and the reduced polysilicon spacer such that the silicon oxide remains as the oxide structure forming the insulation pattern, removing a part of the semiconductor layer by an etching process using the Oxide structure as an etching mask, wherein a remaining part of the semiconductor layer below the lateral projection of the oxide structure, the floating gate structure ( 104a ), - forming an insulating layer ( 200 ) covering the floating gate structure, and - forming the control gate structure ( 120 ) on the sidewall of the oxide structure, extending into the concave portion of the oxide structure to form its laterally projecting portion. Method according to claim 8, further characterized in that - the substrate has a substrate main body ( 100 ), a first insulating layer formed thereon ( 102 ), a first semiconductor layer formed thereon ( 104 ) and a second insulating layer formed on the first semiconductor layer ( 106 ), - forming a third insulating layer on the second insulating layer and patterning by etching, - forming the insulating layer by oxidizing a portion of the first semiconductor layer as a semiconductor oxide layer, and - polysilicon spacers by depositing a polysilicon layer and anisotropic etching is formed of the same. Method according to claim 9, further characterized for forming the control gate structure, a second semiconductor layer substantially conforming to the surface of the oxide structure under filling of their concave sidewall area applied and then anisotropic etched is added to the control gate structure as a semiconductor spacer to the Sidewall of the oxide structure to form. The method of claim 9 or 10, further characterized in that the substrate base body used is a semiconductor wafer is for the first insulation layer, for the second insulating layer and the semiconductor oxide layer Silica is used for the third insulating layer of silicon nitride is used and for the first Semiconductor layer and the second semiconductor layer polysilicon is used. The method of claim 11, further characterized by using as the semiconductor wafer one of the p-type, the first insulating layer is formed to a thickness of about 5 nm to about 15 nm, the first semiconductor layer having a thickness of about 50 nm 150 nm is formed, the second insulating layer is formed to a thickness of about 3 nm to about 10 nm, the third insulating layer is formed to have a thickness of about 200 nm to about 300 nm, the semiconductor oxide layer is formed with a thickness of about 50 nm to 150 nm, the polysilicon layer is formed for the polysilicon spacer having a thickness of about 150 nm to about 300 nm, and the second semiconductor layer is formed with a thickness of about 200 nm to about 400 nm becomes. The method of any one of claims 9 to 12, further characterized characterized in that the first semiconductor layer has a thickness which is at least about 90% and at most about 110% of the thickness the semiconductor oxide layer formed on it. A method according to any one of claims 9 to 13, further characterized characterized in that the first semiconductor layer in a region remains under the semiconductor oxide layer having a thickness at least about 40% of the original Thickness of the first semiconductor layer is. The method of claim 1, further characterized in that the formation of the isolation structure, the floating gate structure, the gate insulating interlayer, and the control gate structure comprises the steps of: forming a first isolation layer; 102 ) on a substrate ( 100 ), - forming a first semiconductor layer ( 102 ) on the first insulation layer, - forming a second insulation layer ( 104 ) on the first semiconductor layer, - forming a third insulation layer ( 106 ) on the second insulating layer, - patterning and etching the third insulating layer to form an opening exposing a portion of the second insulating layer and having a substantially vertical sidewall, - oxidizing a portion of the first semiconductor layer to form a semiconductor oxide layer, - depositing a second semiconductor layer Anisotropic etching of the second semiconductor layer to form a spacer on the sidewall of the opening and exposing a portion of the semiconductor oxide layer, etching the exposed portion of the semiconductor oxide layer to expose a portion of the first semiconductor layer, etching the exposed portion of the first semiconductor layer to expose one Part of the first insulating layer, - applying a fourth insulating layer in a thickness sufficient to fill the opening, - removing an upper part of the fourth insulating layer to expose an upper side of the third removing the third insulation layer, wherein the spacer essentially stops and forms a base structure, removing the second insulation layer, etching the first semiconductor layer using the base structure as an etching mask, around the first insulation layer and for producing a substantially planar surface Insulating layer on the floating gate structure, applying a third semiconductor layer substantially conforming to the surface of the base structure, etching the third semiconductor layer to generate the control gate structure on the sidewall of the base structure in association with the floating one Gate structure, but isolated from this, and - depositing a fourth insulating layer to isolate the control gate structure. Method according to claim 15, further characterized that for the substrate is a semiconductor wafer used for the first Insulation layer, the second insulation layer, the semiconductor oxide layer and the fourth insulating layer of silicon oxide is used for the third Insulation layer silicon nitride is used and for the first Semiconductor layer, the second semiconductor layer and the third semiconductor layer Polysilicon is used. A method according to claim 16, further characterized that used as a semiconductor wafer such a p-type conductivity is the first insulating layer with a thickness of about 5 nm is formed to about 15 nm, the first semiconductor layer having a Thickness of about 50 nm to about 150 nm is formed, the second insulating layer is formed with a thickness of about 3 nm to about 10 nm, the third insulating layer having a thickness of about 200 nm to about 300 nm is formed, the semiconductor oxide layer with a thickness is formed from about 50 nm to about 150 nm, the second semiconductor layer is formed with a thickness of about 150 nm to about 300 nm, the fourth insulation layer formed with a thickness of about 1500 nm and the third semiconductor layer having a thickness of about 200 nm is formed to about 400 nm. The method of any of claims 15 to 17, further characterized characterized in that the first semiconductor layer has a thickness is applied, the maximum about 110% of the thickness of the over the semiconductor oxide layer formed on the exposed part of the first semiconductor layer is. The method of any of claims 15 to 18, further characterized characterized in that the thickness of the under the semiconductor oxide layer remaining part of the first semiconductor layer at least about 40% the original one Thickness of the first semiconductor layer is. Method according to one of claims 1 to 19, further characterized in that the floating gate structure and the control gate structure are each formed in several parts as a split-gate structure. A method according to claim 20, further characterized that is, for producing a split-gate transistor structure for a nonvolatile memory cell serves and includes the following steps: - Forming a first insulating layer on a substrate, - Form a first semiconductor layer on the first insulating layer, - Form a second insulating layer on the first semiconductor layer, - Form a third insulation layer on the second insulation layer, - Structure and etching the third insulation layer for creating an opening, which exposes a portion of the second insulating layer and substantially vertical side walls having, - Oxidize a part of the first semiconductor layer for forming a semiconductor oxide layer, - Apply a sidewall material layer, Anisotropic etching of the Sidewall material layer for creating spacers on the sidewalls the opening and exposing a part of the semiconductor oxide layer, - etching the exposed portion of the semiconductor oxide layer for exposing a Part of the first semiconductor layer, - etching the exposed part the first semiconductor layer for exposing a part of the first Insulating layer, - Implant a dopant through the exposed part of the first insulating layer through to generate a source region in a corresponding one Part of the substrate, - Apply a fourth insulating layer having a thickness sufficient to fill the opening, - Remove an upper part of the fourth insulation layer for exposure an upper side of the third insulating layer and generating a essentially planar surface, - Remove the third insulation layer and the spacer so that one Insulation structure with side walls remains, each having a concave, recessed area, - Remove the second insulation layer, - Etching the first semiconductor layer using a remaining portion of the semiconductor oxide layer for exposing the first insulation layer and for generating the first, as a floating gate structure of functioning conductor elements, - Form a fifth Insulation layer on the first conductor elements, - Apply a second semiconductor layer substantially conforming to the surface the insulating structure, wherein the second semiconductor layer is the concave, recessed area in the sidewalls of the isolation structure crowded, - etching the second semiconductor layer for the production of semiconductor spacers the side walls the isolation structure and to expose part of the first Isolation layer, wherein each semiconductor spacer has a second, forms as a control gate structure acting conductor element, which with the first conductor element forms a pair isolated from this and with at least partially overlapping it, - Implant a dopant through the exposed part of the first insulating layer through to create a drain region in the substrate, - Apply a sixth insulating layer for insulating the second conductor element and - Produce separate electrical connections to the source region, to the drain region and to the second conductor element. A method according to claim 21, further characterized that during etching of the exposed part of the first semiconductor layer also the spacers on the side walls the opening partially etched so that reduced first spacers arise. The method of claim 21 or 22, further characterized characterized in that the etching of the exposed part of the first semiconductor layer over-etching with an over-etching period which is used to control a base width of the formed on the side walls of the opening Spacers selected becomes. A method according to claim 23, further characterized the second conductor element overlaps the first conductor element with an overlap length, controlled by the control of the base width of the spacers on the opening side walls becomes. The method of any one of claims 21 to 24, further characterized characterized in that the etching of the second semiconductor layer over-etching with an over-etching period which is used to control a base width of the semiconductor spacers chosen becomes. A method according to claim 25, further characterized that by controlling the base width of the semiconductor spacers Length of one Channel area defined by a top of the page Substrate is formed, which is substantially between the source region and the drain region and below the first conductor element and the second conductor element extends. A method according to any one of claims 21 to 26, further characterized in that implanting the dopant through the exposed portion of the first insulating layer to form the drain region in the substrate comprises the steps of: Implanting a first dopant through the exposed portion of the first insulating layer to form a lightly doped drain region in the substrate, applying a second sidewall material layer, anisotropically etching the second sidewall material layer to form second spacers on the sidewalls of the semiconductor spacers around the exposed portion reducing the first insulating layer; and implanting a second dopant through the reduced exposed portion of the first insulating layer to complete the drain region. A method according to claim 27, further characterized that for the first dopant is selected to be an n-type dopant, implanted with a first dose, and for the second Dopant an n-type dopant is selected, with a second Dose is implanted, with the ratio of the first dose to second dose at most 1 : 25. Transistor gate structure, in particular of the split gate type for a semiconductor memory cell, comprising - a substrate ( 100 ), - a common source area ( 116 ) in the substrate, - a drain region separated from the source region by a channel region ( 126 ) in the substrate, - a dielectric layer ( 204 ) over the channel region, - a floating gate electrode disposed on the dielectric layer over a first part of the channel region adjacent to the source region ( 104a ) and - a control gate electrode ( 120 ), characterized in that - the control gate electrode ( 120 ) is disposed on the dielectric layer over a second portion of the channel region adjacent to the drain region and extends with a protruding portion over an adjacent portion of the floating gate electrode, the protruding portion having an upper portion with a substantially vertical termination surface and a lower portion with non-conductive features. vertical end surface, wherein the lower portion laterally than the upper portion overlaps laterally with the floating gate electrode. A transistor gate structure according to claim 29, further characterized in that - a bottom of the lower portion of the projecting portion of the control gate electrode is spaced from the floating gate electrode by an interpolyoxide (IPO) of a predetermined thickness T _IPO , - a lower portion of the non-protruding portion of the control gate electrode a substantially vertical side surface extending from the floating gate electrode through a tunnel oxide ( 200 ) is spaced apart with a predeterminable thickness T _tun , and has a substantially horizontal base area, which is spaced from the channel region by a gate oxide region of the dielectric layer with a predeterminable thickness T _g , and - a lower part of the floating gate electrode has a substantially horizontal base surface which is spaced from the channel region by a coupling oxide part of the dielectric layer having a predetermined thickness T _c , the thickness relationships T _IPO > T _tun and T _IPO > T _c and T _IPO > T _g . Transistor gate structure according to claim 29 or 30, further characterized in that the floating gate electrode one upwards directed projection in one of the control gate electrode facing Has area. Transistor gate structure, in particular of the split gate type for a semiconductor device, comprising - a substrate ( 100 ), - a source ( 116 ), a drain ( 126 ) and a channel between the source and the drain in the substrate, - a gate insulation layer ( 204 ) on the substrate, - a floating gate ( 104a ) on the gate insulating layer and over a peripheral part of the source and a first part of the channel, - an intermediate polyoxide layer ( 202 ) over the top of the floating gate and a tunnel oxide layer ( 200 ) on a side surface of the floating gate and - a control gate ( 120 ) on the gate insulation layer, characterized in that - the control gate ( 120 ) is formed over an outer part of the floating gate, a peripheral part of the drain and a second part of the channel, and from the floating gate through the inter-polyoxide layer (FIG. 202 ) and the tunnel oxide layer ( 200 ) is separated and isolated. Transistor gate structure according to claim 32, further characterized in that the floating gate in cross-section a predetermined cross-sectional area A _f and the control gate has a predetermined cross-sectional area A _c and laterally to the side of the source and over an outer part of the floating gate protruding part, wherein the cross-sectional ratio A _f / A _{c is} between about 1: 2 and about 1:10. Transistor gate structure according to claim 33, further characterized in that the floating gate in cross-section has a predetermined gate length L _f and the projecting part of the control gate with a predetermined length L _p laterally overlaps the floating gate, the aspect ratio L _p / L _f between about 2 : 3 and about 1: 5 lies. Transistor gate structure according to one of claims 32 to 34, further characterized in that - a bottom of the projecting part of the control gate is spaced from the floating gate by an intermediate polyoxide (IPO) with a predetermined thickness T _IPO , - a lower portion of the non-protruding part of the control gate a substantially vertical side surface spaced from the floating gate by a tunnel oxide of a predetermined thickness T _{tun and} having a substantially horizontal base spaced from the second portion of the channel by a gate oxide of a predetermined thickness T _g , and a lower portion of the floating gate has a substantially horizontal footprint spaced from the first portion of the channel by a coupling oxide of a predetermined thickness T _c , the thickness relationships T _IPO > T _tun and T _IPO > T _c and T _IPO > T _g apply. Transistor gate structure according to claim 35, further characterized in that the thickness ratio T _c / T _g between about 3: 1 and 1: 3, in particular about 1: 1, is. Transistor gate structure according to one of claims 29 to 36, further characterized in that the floating gate and the Control gate are formed as a split gate structure.