EP1412972A2 - Method for reducing surface rugosity - Google Patents

Method for reducing surface rugosity

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Publication number
EP1412972A2
EP1412972A2 EP20020782466 EP02782466A EP1412972A2 EP 1412972 A2 EP1412972 A2 EP 1412972A2 EP 20020782466 EP20020782466 EP 20020782466 EP 02782466 A EP02782466 A EP 02782466A EP 1412972 A2 EP1412972 A2 EP 1412972A2
Authority
EP
European Patent Office
Prior art keywords
wafer
rapid thermal
pure argon
annealing
thermal annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP20020782466
Other languages
German (de)
French (fr)
Inventor
Eric Neyret
Ludovic Ecarnot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of EP1412972A2 publication Critical patent/EP1412972A2/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the present invention relates generally to the surface treatment of materials, and in particular the treatment of substrates intended for the manufacture of components for applications in microelectronics and / or optoelectronics. More specifically, the invention relates to a method for reducing the roughness of the free surface of a wafer of semiconductor material, said method comprising an annealing step in order to smooth said free surface.
  • free surface is meant the surface of a wafer which is exposed to the external environment (as opposed to an interface surface which is in contact with the surface of another wafer or of another element) .
  • the invention can be implemented in a particularly advantageous manner - but not limiting - in combination with a process for manufacturing thin films or layers of semiconductor material of the type described in patent FR 2 681 472.
  • a process reproducing the teachings of the document cited above is known as the SMARTCUT® process. Its main steps are schematically as follows: • A step of implanting atoms, under one face of a substrate of semiconductor material (in particular silicon), in a zone of implantation of the substrate, • A step of placing intimate contact of the implanted substrate with a stiffener, and • A step of cleaving the implanted substrate at the implantation zone, to transfer the part of the substrate located between the surface subjected to implantation and the implantation zone, onto the stiffener and thereby form a thin film, or layer, of semiconductor thereon.
  • a substrate of semiconductor material in particular silicon
  • implantation of atoms means any bombardment of atomic or ionic species capable of introducing these species into the material of the wafer with a maximum concentration of species. implanted located at a determined depth of the wafer with respect to the bombarded surface so as to define a weakening zone.
  • the depth of the embrittlement zone depends on the nature of the implanted species, and the energy associated with them for implantation.
  • the wafer (which is made of semiconductor material) can thus be associated with a stiffener, and possibly with other intermediate layers.
  • slice also covers in this text any slice, layer or film of semiconductor material such as silicon, whether the slice was produced by a process of the SMARTCUT ® type or not, the objective being in all case of reducing the roughness of the free surface of the wafer.
  • the roughness specifications associated with the free surface of the wafers are indeed very strict, and the quality of the free surface of the wafers is a parameter which conditions the quality of the components which will be produced. on the edge.
  • the roughness is measured on surfaces scanned by the tip of the AFM microscope, ranging from 1x1 ⁇ m 2 to 10x10 ⁇ m 2 and more rarely 50x50 ⁇ m 2 , even 100x100 ⁇ m 2 .
  • Roughness can be characterized, in particular, in two ways. According to one of these methods, the roughness is said to be at high frequencies and corresponds to swept surfaces of the order of 1x1 ⁇ m 2 .
  • the roughness is said to be at low frequencies and corresponds to swept surfaces of the order of 10 ⁇ 10 ⁇ m 2 , or more.
  • the specification of 5 Angstroms given above as an indication is thus a roughness corresponding to a swept surface of 10 ⁇ 10 ⁇ m2.
  • SMARTCUT ® or other have surface roughness values greater than specifications of the order of those mentioned above, in the absence of the application to the surface of the wafer of a specific treatment such as '' a polishing.
  • a first type of known method for reducing the surface roughness of the wafers consists in subjecting the wafer to a “conventional” heat treatment (sacrificial oxidation for example).
  • a treatment of this type does not make it possible to bring the roughness of the wafers to the level of the specifications mentioned above.
  • document EP 1 061 565 thus discloses a process of this type, which teaches long annealing (of the order of 60 minutes) at high temperature, followed by cooling under an atmosphere comprising hydrogen.
  • a second type of known method consists in carrying out a chemical mechanical polishing of the free surface of the wafer.
  • This type of process can effectively reduce the roughness of the free surface of the wafer.
  • this second known type of process can also allow said slab to be abraded to an area having an acceptable defect concentration.
  • this second type of known method has the drawback of compromising the uniformity of the free surface of the wafer.
  • a third type of process consists in subjecting the slice to rapid annealing under a controlled atmosphere, according to a so-called RTA mode (corresponding to the acronym of the Anglo-Saxon expression Rapid Thermal Annealing).
  • RTA Rapid Thermal Annealing
  • this mode of annealing will be denoted indifferently by the acronym RTA, or by the French-speaking designation of "rapid thermal annealing”.
  • the wafer is annealed at a high temperature, which can be of the order of 1100 ° C. to 1300 ° C., for 1 to 60 seconds.
  • a smoothing of the free surface of the wafer is carried out by means of an RTA annealing of the wafer under an atmosphere consisting of '' a mixture generally comprising hydrogen in combination with reactive gases (HCI, HF, HBr, SF 6 , CF 4 , NF 3) CCI 2 F 2 , ).
  • reactive gases HCI, HF, HBr, SF 6 , CF 4 , NF 3
  • the aggressiveness of the mixture which constitutes the annealing atmosphere makes it possible to etch the free surface of the wafer (by a phenomenon of "etching" according to English terminology), which results a decrease in its roughness.
  • This first variant can have advantages.
  • a limitation is however that the gaseous mixture which constitutes the atmosphere used in such a process is aggressive, and elements other than the free surface of the wafer may be exposed to its action (face of wafer or of the structure whose she is united who is opposite to said free surface of the wafer, walls of the annealing chamber).
  • this variant implementing an annealing atmosphere comprising different gases, some of which are reactive, it is necessary to provide for the implementation of such a process an installation which can be relatively complex (routing of the different gases, measurements of security, ).
  • An embodiment taught by document EP 1 061 565 corresponds to this first variant of this third type of process.
  • an RTA annealing is carried out under an atmosphere systematically comprising hydrogen.
  • the wafer is subjected to an RTA annealing under an atmosphere which does not have the function of attacking the material of the wafer.
  • the smoothing results not from an etching of the free surface of the wafer, but from the reconstruction of the surface of the wafer.
  • the annealing atmosphere is in this case typically composed of hydrogen mixed with argon or nitrogen.
  • EP 1 158 581 also discloses a finishing treatment systematically comprising two anneals, one of which is an RTA annealing, these annealing operations being able to be carried out in an atmosphere containing hydrogen or argon.
  • the two anneals taught by this document both have the function of smoothing the free surface of a slice.
  • the reduction in low frequency roughness is illustrated by the last column of table 2 of this document, which shows in particular the effect of the second annealing which follows the RTA annealing.
  • EP 1 158 581 is thus focused on a sequence of two smoothing anneals (smoothing being characterized by a reduction in roughness at low frequencies), the first of these two anneals being an RTA annealing.
  • the process taught by EP 1 158 581, systematically comprising two smoothing anneals, is relatively cumbersome and time-consuming to implement.
  • the invention proposes to provide an improvement to the methods mentioned above. Indeed, it would be advantageous to further simplify such methods.
  • slip lines any slip lines which may appear in the crystallographic structure of the wafer material, in particular following a heat treatment (such as that which can be applied to the wafer to cause its cleavage in the context of a SMARTCUT ® type process).
  • the hydrogen used in the known implementations of this variant is a relatively expensive gas, while we are looking for constantly reducing costs associated with wafer processing processes.
  • the object of the invention is to make it possible to implement a method meeting these needs.
  • the invention proposes, according to a first aspect, a method for reducing the roughness of the free surface of a wafer of semiconductor material, said method comprising an annealing step in order to smooth said free surface, characterized in that that the method for reducing the roughness of the free surface comprises a single smoothing annealing carried out in the form of a rapid thermal annealing in an atmosphere composed exclusively of pure argon.
  • Preferred, but non-limiting aspects of the process according to the invention are the following:
  • the process also includes the following preliminary steps: A step of implantation of atoms, under one face of a substrate from which the wafer must be produced, in a zone of implantation of the substrate, A step of bringing into contact intimate substrate implanted with a stiffener, and • S A step of cleaving the implanted substrate at the implantation zone, to form the edge with the part of the substrate located between the surface subjected to implantation and the implantation, and transfer said section to the stiffener,
  • polishing step is followed by a sacrificial oxidation step, • the following stages are carried out: sacrificial oxidation, rapid thermal annealing under pure argon, polishing, sacrificial oxidation.
  • FIG. 1 is a general and schematic representation in longitudinal section of an annealing chamber enabling the invention to be implemented
  • Figure 2 is a graph illustrating the reduction in roughness obtained by the implementation of the invention on a silicon wafer.
  • FIG. 1 there is shown schematically a non-limiting example of de_ annealing chamber 1 for implementing the invention.
  • This chamber is intended for the implementation of an annealing step under a pure argon atmosphere according to the RTA operating mode.
  • This chamber 1 comprises an enclosure 2, a reactor 4, a substrate carrier plate 6, two networks of halogen lamps 8, 10 and two pairs of side lamps.
  • the enclosure 2 comprises in particular a lower wall 12, an upper wall 14 and two side walls 16, 18, situated respectively at the longitudinal ends of the enclosure 2.
  • One of the side walls 16, 18 comprises a door 20.
  • the reactor 4 consists of a quartz tube extending longitudinally between the two side walls 16, 18. It is provided at each of these side walls 16, 18, respectively with a gas inlet 21 and a gas outlet 22.
  • the gas outlet 22 is located on the side of the side wall 18 comprising the door 20.
  • Each network of halogen lamps 8, 10 is located respectively above and below the reactor 4, between the latter and the lower 12 and upper 14 walls.
  • Each network of halogen lamps 8, 10 comprises 17 lamps 26 arranged perpendicular to the longitudinal axis of the reactor 4.
  • the two pairs of side lamps (not shown in the figure).
  • the substrate-holder plate 6 slides in the reactor 4. It supports a wafer 50 intended to undergo the annealing step under a hydrogenated atmosphere 100 and allows them to be brought in or taken out of the chamber 1.
  • a room 1 of this type is marketed by STEAG ®, as "SHS AST 2800".
  • the "wafer” 50 can be, in general, any type of monolayer or multilayer structure comprising a surface layer of a semiconductor material (such as silicon, "in a preferred but non-limiting manner).
  • an object of the invention is to make it possible to reduce the roughness of the free surface of such a surface layer.
  • the invention can in fact be implemented to reduce the roughness of the free surface of a wafer 50 which has not undergone any prior treatment but also wafers obtained by specific treatments.
  • the various variants of the invention apply in a particularly advantageous manner to the reduction of the roughness of the surfaces of an SOI structure and / or of the substrate of semiconductor material from which such a structure is derived, in particular as a result of the application of a SMARTCUT ® type process.
  • the invention can be implemented with advantage to decrease the roughness of the one or the other of the two surfaces of semiconductor material that resulted from the cleavage of the zone of weakness formed during the implantation stage, or of these two surfaces.
  • wafers 50 comprising a useful layer of semiconductor material 52 (made for example of silicon), said layer itself having a free surface 54.
  • the layer 52 is designated as “useful” because it will be used for the constitution of the electronic, optical or opto-electronic elements on the wafer 50.
  • the free surface 54 may be a cleavage surface obtained by the implementation of a SMARTCUT ® process.
  • the wafer 50 is an SOI substrate from the process SMARTCUT ®, the wafer 50 comprises in the useful layer 52 a buried oxide layer which covers itself a support substrate.
  • the invention can thus be implemented only by performing an RTA annealing step of the wafer 50, under an atmosphere of pure argon.
  • the annealing step under pure argon comprises the steps consisting in:
  • the pressure can also be fixed at a lower value, which can range from a few mTorr to atmospheric pressure, • increase, by lighting the halogen lamps 26, the temperature in chamber 1, at a speed of order of 50 ° C per second, up to a processing temperature,
  • the argon used is as pure as possible because the Applicant has found that the presence of small amounts of additional elements (such as oxygen in particular) could lead to an attack on the material. of the useful layer (formation of very volatile SiO in the case of a silicon surface layer exposed to an annealing atmosphere comprising a small amount of oxygen, for example). And the Applicant has found that such a step of annealing under an atmosphere of pure argon made it possible to significantly reduce the roughness of the free surface 54. The results obtained were in particular of much better quality than the reduction in roughness which can be obtained only by a conventional treatment such as a heat treatment of sacrificial oxidation type. And the uniformity of the useful layer is also much better than if the slice had been subjected to a polishing operation.
  • the RTA annealing step under pure argon can for example comprise a heating stage lasting 5 to 30 seconds, at a treatment temperature of between 1100 and 1250 ° C.
  • FIG. 2 illustrates the reduction in roughness by such a method. More precisely, this figure shows the gain in “haze” obtained following the application of a method according to the invention as mentioned above.
  • the abscissa axis makes it possible to browse different slices, the haze having been measured for each of these slices before the application of an annealing according to the invention (measurement from the top), and after (measurement from the bottom) .
  • the upper curve thus corresponds to a haze measured on the surface of SOI structures after cleavage, and the lower curve to the same measurements, carried out after an RTA annealing under argon at 1230 ° C. with a heating stage of 30s.
  • haze designates the optical signal scattered by the surface of the substrate 50, in response to a light excitation. This haze is representative of the surface roughness.
  • the reduction in haze 6220 is of a level comparable to the results which can be obtained by other RTA annealing techniques, for example RTA annealing in an atmosphere composed of a mixture of hydrogen and argon . More precisely, the gain of haze corresponds to a division of haze by a factor of the order of 6 to 10.
  • the implementation of the method according to the invention makes it possible to obtain results of this high level of quality by overcoming the limitations mentioned above with regard to known RTA annealing.
  • argon being an excellent thermal conductor
  • the implementation of an atmosphere of pure argon makes it possible to distribute the heat in the most homogeneous way possible inside the chamber 1, and thus to reduce the slip lines that can be observed in the case of the implementation of these known methods.
  • the invention can be implemented only by the RTA annealing step under pure argon: this step makes it possible to obtain a considerable improvement in the surface condition of the wafer 50. And this improvement is obtained practically without removing material from the wafer, but on the contrary by reconstruction of the surface 54 and smoothing.
  • the step of annealing RTA under pure argon is followed by a step of polishing the surface of the wafer 50.
  • This polishing step is carried out by chemical mechanical polishing, known per se. It makes it possible to remove the material from the useful layer 52 which is located near the free surface 54 and which may also have surface defects.
  • the step of annealing RTA under pure argon is followed not only by a polishing step, but also then by an additional sacrificial oxidation step combined with a heat treatment.
  • the sacrificial oxidation step is intended to remove the defects possibly remaining after the polishing step.
  • the defects may be related to implantation steps or cleavage.
  • the sacrificial oxidation step is broken down into an oxidation step and a deoxidation step.
  • the heat treatment is interposed between the oxidation step and the deoxidation step.
  • the oxidation step is preferably carried out at a temperature between 700 ° C and 1100 ° C.
  • the oxidation step can be carried out dry or wet.
  • the oxidation step is, for example, carried out by heating the wafer 50 under gaseous oxygen.
  • the oxidation step is, for example, carried out by heating the wafer 50 in an atmosphere charged with water vapor.
  • the oxidation atmosphere can also be loaded with hydrochloric acid.
  • the oxidation step results in the formation of an oxide 60 which covers the surface 54 of the useful layer 52.
  • the heat treatment step is carried out by any thermal operation intended to improve the qualities of the material constituting the useful layer 52.
  • This heat treatment can be carried out at constant temperature or at variable temperature.
  • the heat treatment is carried out, for example, with a gradual increase in temperature between two values, or with a cyclic oscillation between two values, etc.
  • the heat treatment step is carried out at least in part at a temperature above 1000 ° C., and more particularly there around 1100-1200 ° C.
  • This heat treatment is preferably carried out under a non-oxidizing atmosphere, which can include argon, nitrogen, hydrogen, etc., or a mixture of these gases.
  • the heat treatment can also be carried out under vacuum.
  • the oxidation step is carried out before the heat treatment step.
  • the oxide 60 protects the rest of the useful layer during the heat treatment and avoids the pitting phenomenon.
  • the stitching phenomenon is well known to a person skilled in the art, who also calls it "pitting". It occurs on the surface of certain semiconductors when they are annealed under a non-oxidizing atmosphere, such as nitrogen, argon, under vacuum, etc. It occurs in the case of silicon, in particular when the latter is bare, that is to say when it is not at all covered with oxide.
  • the oxidation step begins with the start of the rise in temperature of the heat treatment and ends before the end of the latter.
  • the heat treatment makes it possible to cure, at least in part, the defects generated during the preceding stages of the manufacturing and treatment process of the wafer 50.
  • the heat treatment can be carried out for a duration and at a temperature such that it achieves a healing of crystalline defects, such as stacking faults, “HF” defects, etc., generated in the useful layer 52, during the oxidation step.
  • crystalline defects such as stacking faults, “HF” defects, etc.
  • HF is called fault, a fault whose presence is detected by a decorative halo in the buried oxide that is located under the active layer 52 (the case where the wafer 50 is an SOI process from a SMARTCUT ®) after treatment of the slice in a hydrofluoric acid bath.
  • the present heat treatment also has the advantage to strengthen the bonding interface, for example between the transferred layer during transfer by the SMARTCUT ® process and the support substrate.
  • the deoxidation step is preferably carried out in solution.
  • This solution is for example a 10 or 20% hydrofluoric acid solution. A few minutes are enough to remove a thousand to a few thousand angstroms of oxide 60, by immersing the slice 50 in such a solution.
  • the steps of the second variant described above are preceded by an additional sacrificial oxidation step of the surface of the wafer 50, this sacrificial oxidation step (identical to that described above) preferably being combined with heat treatment.
  • the first and second sacrificial oxidation steps are broken down into an oxidation step and a deoxidation step.
  • the first and second sacrificial oxidation steps as well as the heat treatment steps are similar to those already described for the second variant described above, of the process according to the present invention.
  • the step of annealing RTA under pure argon is followed by two steps of sacrificial oxidation of the free surface of the wafer 50.
  • an additional mechanical-chemical polishing step is inserted between the two sacrificial oxidation steps.
  • two steps of annealing RTA under pure argon are carried out on the wafer 50, by interposing between these two steps a chemical-mechanical polishing step.
  • a step of sacrificial oxidation of the surface of the wafer 50 is carried out (step always identical to those described above, and preferably combined with a heat treatment), after which it is subjected to at section 50, an RTA annealing under an atmosphere of pure argon.
  • a seventh variant of the invention the order of the two main stages of the sixth variant is reversed, by carrying out the RTA annealing under pure argon before the sacrificial oxidation.
  • an RTA annealing step of the slice under pure argon between two sacrificial oxidation steps (always identical to those described above, and preferably combined with a heat treatment) of the surface of the wafer 50, an RTA annealing step of the slice under pure argon.
  • This unique smoothing annealing corresponds to rapid thermal annealing in an atmosphere composed exclusively of pure argon.
  • the heat treatments associated with sacrificial oxidation operations are intended to remove material and strengthen the bonding interfaces, and not to smooth the free surface of the wafer.
  • the method for reducing the roughness of the free surface comprises a single smoothing annealing carried out in the form of a rapid thermal annealing in an atmosphere composed exclusively of pure argon.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention relates to a method for reducing the rugosity of the free surface of a slice of semiconductor material. Said method comprises an annealing step in order to smooth said free surface. The invention is characterized in that the method for reducing free surface rugosity comprising a single smoothing annealing step which is carried out in the form of rapid thermal annealing in an atmosphere which is exclusively comprised of pure argon. The invention also relates to a structure produced by said method.

Description

PROCEDE DE DIMINUTION DE RUGOSITE DE SURFACE METHOD FOR REDUCING SURFACE ROUGHNESS
La présente invention concerne de manière générale le traitement de surface des matériaux, et particulièrement le traitement de substrats destinés à la fabrication de composants pour des applications en microélectronique et/ou en opto-électronique. Plus précisément, l'invention concerne un procédé de diminution de la rugosité de la surface libre d'une tranche de matériau semiconducteur, ledit procédé comprenant une étape de recuit afin de lisser ladite surface libre.The present invention relates generally to the surface treatment of materials, and in particular the treatment of substrates intended for the manufacture of components for applications in microelectronics and / or optoelectronics. More specifically, the invention relates to a method for reducing the roughness of the free surface of a wafer of semiconductor material, said method comprising an annealing step in order to smooth said free surface.
Par « surface libre », on entend la surface d'une tranche qui est exposée à l'environnement extérieur (par opposition à une surface d'interface qui est au contact de la surface d'une autre tranche ou d'un autre élément).By "free surface" is meant the surface of a wafer which is exposed to the external environment (as opposed to an interface surface which is in contact with the surface of another wafer or of another element) .
Et comme on le verra, l'invention pourra être mise en œuvre de manière particulièrement avantageuse - mais non limitative - en combinaison avec un procédé de fabrication de films minces ou de couches de matériau semiconducteur du type décrit dans le brevet FR 2 681 472.And as we will see, the invention can be implemented in a particularly advantageous manner - but not limiting - in combination with a process for manufacturing thin films or layers of semiconductor material of the type described in patent FR 2 681 472.
Un procédé reproduisant les enseignements du document cité ci- dessus est connu comme le procédé SMARTCUT®. Ses étapes principales sont schématiquement les suivantes : • Une étape d'implantation d'atomes, sous une face d'un substrat de matériau semiconducteur (en particulier du silicium), dans une zone d'implantation du substrat, • Une étape de mise en contact intime du substrat implanté avec un raidisseur, et • Une étape de clivage du substrat implanté au niveau de la zone d'implantation, pour transférer la partie du substrat située entre la surface soumise à l'implantation et la zone d'implantation, sur le raidisseur et former ainsi un film mince, ou une couche, de semiconducteur sur celui-ci. Par implantation d'atomes, on entend tout bombardement d'espèces atomiques ou ioniques, susceptible d'introduire ces espèces dans le matériau de la tranche avec un maximum de concentration des espèces implantées situé à une profondeur déterminée de la tranche par rapport à la surface bombardée de manière à définir une zone de fragilisation.A process reproducing the teachings of the document cited above is known as the SMARTCUT® process. Its main steps are schematically as follows: • A step of implanting atoms, under one face of a substrate of semiconductor material (in particular silicon), in a zone of implantation of the substrate, • A step of placing intimate contact of the implanted substrate with a stiffener, and • A step of cleaving the implanted substrate at the implantation zone, to transfer the part of the substrate located between the surface subjected to implantation and the implantation zone, onto the stiffener and thereby form a thin film, or layer, of semiconductor thereon. The term “implantation of atoms” means any bombardment of atomic or ionic species capable of introducing these species into the material of the wafer with a maximum concentration of species. implanted located at a determined depth of the wafer with respect to the bombarded surface so as to define a weakening zone.
La profondeur de la zone de fragilisation est fonction de la nature des espèces implantées, et de l'énergie qui leur est associée pour l'implantation.The depth of the embrittlement zone depends on the nature of the implanted species, and the energy associated with them for implantation.
On précise qu'on désigne dans ce texte par le terme générique de « tranche » le film ou la couche transférée par un tel procédé du type SMARTCUT®.It is specified that refers herein by the generic term "slice" the film or layer transferred by such a method the type SMARTCUT ®.
La tranche (qui est en matériau semiconducteur) peut ainsi être associée à un raidisseur, et éventuellement à d'autres couches intermédiaires.The wafer (which is made of semiconductor material) can thus be associated with a stiffener, and possibly with other intermediate layers.
Et ce terme de « tranche » recouvre également dans le présent texte toute tranche, couche ou film de matériau semiconducteur tel que le silicium, que la tranche ait été produite par un procédé du type SMARTCUT® ou non, l'objectif étant dans tous les cas de diminuer la rugosité de la surface libre de la tranche.And this term "slice" also covers in this text any slice, layer or film of semiconductor material such as silicon, whether the slice was produced by a process of the SMARTCUT ® type or not, the objective being in all case of reducing the roughness of the free surface of the wafer.
Pour les applications du type mentionnées au début de ce texte, les spécifications de rugosité associées à la surface libre des tranches sont en effet très sévères, et la qualité de la surface libre des tranches est un paramètre qui conditionne la qualité des composants qui seront réalisés sur la tranche.For applications of the type mentioned at the beginning of this text, the roughness specifications associated with the free surface of the wafers are indeed very strict, and the quality of the free surface of the wafers is a parameter which conditions the quality of the components which will be produced. on the edge.
Il est ainsi courant de trouver des spécifications de rugosité ne devant pas dépasser 5 Angstroms en valeur rms (correspondant à l'acronyme anglo-saxon « root mean square »). On précise que les mesures de rugosité sont généralement effectuées grâce à un microscope à force atomique (AFM selon l'acronyme qui correspond à l'appellation anglo-saxonne de Atomic Force Microscope).It is thus common to find roughness specifications not to exceed 5 Angstroms in rms value (corresponding to the acronym “root mean square”). It is specified that the roughness measurements are generally carried out using an atomic force microscope (AFM according to the acronym which corresponds to the Anglo-Saxon name of Atomic Force Microscope).
Avec ce type d'appareil, la rugosité est mesurée sur des surfaces balayées par la pointe du microscope AFM, allant de 1x1 μm2 à 10x10 μm2 et plus rarement 50x50 μm2, voire 100x100 μm2.With this type of device, the roughness is measured on surfaces scanned by the tip of the AFM microscope, ranging from 1x1 μm 2 to 10x10 μm 2 and more rarely 50x50 μm 2 , even 100x100 μm 2 .
La rugosité peut être caractérisée, en particulier, selon deux modalités. Selon l'une de ces modalités, la rugosité est dite à hautes fréquences et correspond à des surfaces balayées de l'ordre de 1x1 μm2.Roughness can be characterized, in particular, in two ways. According to one of these methods, the roughness is said to be at high frequencies and corresponds to swept surfaces of the order of 1x1 μm 2 .
Selon l'autre de ces modalités, la rugosité est dite à basses fréquences et correspond à des surfaces balayées de l'ordre de 10x10 μm2, ou plus. La spécification de 5 Angstrôms donnée ci-dessus à titre indicatif est ainsi une rugosité correspondant à une surface balayée de 10x10 μm2.According to the other of these methods, the roughness is said to be at low frequencies and corresponds to swept surfaces of the order of 10 × 10 μm 2 , or more. The specification of 5 Angstroms given above as an indication is thus a roughness corresponding to a swept surface of 10 × 10 μm2.
Et les tranches qui sont produites par les procédés connus (de typeAnd the slices which are produced by known processes (of the type
SMARTCUT® ou autre) présentent des rugosités de surface dont les valeurs sont supérieures à des spécifications de l'ordre de celles mentionnées ci-dessus, en l'absence de l'application à la surface de la tranche d'un traitement spécifique tel qu'un polissage.SMARTCUT ® or other) have surface roughness values greater than specifications of the order of those mentioned above, in the absence of the application to the surface of the wafer of a specific treatment such as '' a polishing.
Un premier type de procédé connu pour diminuer la rugosité de surface des tranches consiste à faire subir à la tranche un traitement thermique « classique » (oxydation sacrificielle par exemple). Mais un traitement de ce type ne permet pas d'amener la rugosité des tranches au niveau des spécifications mentionnées ci-dessus.A first type of known method for reducing the surface roughness of the wafers consists in subjecting the wafer to a “conventional” heat treatment (sacrificial oxidation for example). However, a treatment of this type does not make it possible to bring the roughness of the wafers to the level of the specifications mentioned above.
Et si on peut certes imaginer de multiplier les étapes de tels traitements thermiques classiques, et/ou de les combiner avec d'autres types de procédé connus, en vue de réduire encore la rugosité, ceci conduirait à un procédé long et complexe.And if it can certainly be imagined to multiply the steps of such conventional heat treatments, and / or to combine them with other types of known process, in order to further reduce the roughness, this would lead to a long and complex process.
On connaît par exemple ainsi du document EP 1 061 565 un procédé de ce type, qui enseigne un recuit long (de l'ordre de 60 minutes) à haute température, suivi d'un refroidissement sous une atmosphère comprenant de l'hydrogène. Un deuxième type de procédé connu consiste à effectuer un polissage mécano-chimique de la surface libre de la tranche.For example, document EP 1 061 565 thus discloses a process of this type, which teaches long annealing (of the order of 60 minutes) at high temperature, followed by cooling under an atmosphere comprising hydrogen. A second type of known method consists in carrying out a chemical mechanical polishing of the free surface of the wafer.
Ce type de procédé peut effectivement permettre de réduire la rugosité de la surface libre de la tranche.This type of process can effectively reduce the roughness of the free surface of the wafer.
Dans le cas où il existe un gradient de concentration de défauts croissant en direction de la surface libre de la tranche, ce deuxième type de procédé connu peut e i outre permettre d'abraser ladite tranche jusqu'à une zone présentant une concentration de défauts acceptable. Cependant, ce deuxième type de procédé connu présente l'inconvénient de compromettre l'uniformité de la surface libre de la tranche.In the case where there is an increasing gradient of defect concentration towards the free surface of the wafer, this second known type of process can also allow said slab to be abraded to an area having an acceptable defect concentration. However, this second type of known method has the drawback of compromising the uniformity of the free surface of the wafer.
Et cet inconvénient est accru dans le cas où on procède à un polissage important de la surface de la tranche, ce qui serait le cas pour arriver à des rugosités telles que mentionnées ci-dessus.And this drawback is increased in the case where a significant polishing of the surface of the wafer is carried out, which would be the case in order to achieve roughness as mentioned above.
Un troisième type de procédé consiste à faire subir à la tranche un recuit rapide sous atmosphère contrôlée, selon un mode dit RTA (correspondant à l'acronyme de l'expression anglo-saxonne Rapid Thermal Annealing). Dans la suite de ce texte, on désignera ainsi indifféremment ce mode de recuit par l'acronyme RTA, ou par l'appellation francophone de "recuit thermique rapide".A third type of process consists in subjecting the slice to rapid annealing under a controlled atmosphere, according to a so-called RTA mode (corresponding to the acronym of the Anglo-Saxon expression Rapid Thermal Annealing). In the remainder of this text, this mode of annealing will be denoted indifferently by the acronym RTA, or by the French-speaking designation of "rapid thermal annealing".
Dans ce troisième type de procédé, on recuit la tranche à une température élevée, pouvant être de l'ordre de 1100°C à 1300°C, pendant 1 à 60 secondes.In this third type of process, the wafer is annealed at a high temperature, which can be of the order of 1100 ° C. to 1300 ° C., for 1 to 60 seconds.
Selon une première variante de ce troisième type de procédé dont on trouvera un exemple dans le document US 6 171 965, on réalise un lissage de la surface libre de la tranche par le biais d'un recuit RTA de la tranche sous une atmosphère constituée d'un mélange comprenant généralement de l'hydrogène en combinaison avec des gaz réactifs (HCI, HF, HBr, SF6, CF4, NF3) CCI2F2,...).According to a first variant of this third type of process, an example of which will be found in document US 6,171,965, a smoothing of the free surface of the wafer is carried out by means of an RTA annealing of the wafer under an atmosphere consisting of '' a mixture generally comprising hydrogen in combination with reactive gases (HCI, HF, HBr, SF 6 , CF 4 , NF 3) CCI 2 F 2 , ...).
Dans cette première variante du troisième type de procédé, l'agressivité du mélange qui constitue l'atmosphère de recuit permet de graver la surface libre de la tranche (par un phénomène de « etching » selon la terminologie anglo-saxonne), ce qui aboutit à une diminution de sa rugosité.In this first variant of the third type of process, the aggressiveness of the mixture which constitutes the annealing atmosphere makes it possible to etch the free surface of the wafer (by a phenomenon of "etching" according to English terminology), which results a decrease in its roughness.
Cette première variante peut présenter des avantages.This first variant can have advantages.
Une limitation en est cependant que le mélange gazeux qui constitue l'atmosphère mise en œuvre dans un tel procédé est agressif, et des éléments autres que la surface libre de la tranche peuvent être exposés à son action (face de tranche ou de la structure dont elle est solidaire qui est opposée à ladite surface libre de la tranche, parois de la chambre de recuit).A limitation is however that the gaseous mixture which constitutes the atmosphere used in such a process is aggressive, and elements other than the free surface of the wafer may be exposed to its action (face of wafer or of the structure whose she is united who is opposite to said free surface of the wafer, walls of the annealing chamber).
Il peut ainsi être nécessaire de prendre des mesures supplémentaires pour protéger ces éléments, ce qui tend à complexifier encore le procédé.It may thus be necessary to take additional measures to protect these elements, which tends to further complicate the process.
Et l'agressivité du mélange mis en œuvre est éventuellement susceptible d'aggraver des défauts de la tranche, ce qui peut également nécessiter des traitements supplémentaires.And the aggressiveness of the mixture used is possibly liable to worsen defects in the wafer, which may also require additional treatments.
En outre, cette variante mettant en œuvre une atmosphère de recuit comprenant des gaz différents, dont certains sont réactifs, il est nécessaire de prévoir pour la mise en œuvre d'un tel procédé une installation pouvant être relativement complexe (acheminement des différents gaz, mesures de sécurité, ...).In addition, this variant implementing an annealing atmosphere comprising different gases, some of which are reactive, it is necessary to provide for the implementation of such a process an installation which can be relatively complex (routing of the different gases, measurements of security, ...).
Un mode de réalisation enseigné par le document EP 1 061 565 correspond à cette première variante de ce troisième type de procédé. Dans ce mode de réalisation, on réalise un recuit RTA sous une atmosphère comprenant systématiquement de l'hydrogène.An embodiment taught by document EP 1 061 565 corresponds to this first variant of this third type of process. In this embodiment, an RTA annealing is carried out under an atmosphere systematically comprising hydrogen.
Selon une deuxième variante de ce troisième type de procédé, on fait subir à la tranche un recuit RTA sous une atmosphère qui n'a pas pour fonction d'attaquer le matériau de la tranche.According to a second variant of this third type of process, the wafer is subjected to an RTA annealing under an atmosphere which does not have the function of attacking the material of the wafer.
Dans cette variante en effet, le lissage résulte non pas d'une gravure de la surface libre de la tranche, mais de la reconstruction de la surface de la tranche.In this variant, in fact, the smoothing results not from an etching of the free surface of the wafer, but from the reconstruction of the surface of the wafer.
L'atmosphère de recuit est dans ce cas typiquement composée d'hydrogène mélangée à de l'argon ou de l'azote.The annealing atmosphere is in this case typically composed of hydrogen mixed with argon or nitrogen.
On trouvera dans la demande française 99 10667 au nom de la Demanderesse un exemple de cette deuxième variante du troisième type de procédé.An example of this second variant of the third type of process will be found in French application 99 10667 in the name of the Applicant.
On connaît également par EP 1 158 581 un traitement de finition comportant systématiquement deux recuits dont un recuit RTA, ces recuits pouvant être effectués dans une atmosphère contenant de l'hydrogène ou de l'argon. Les deux recuits enseignés par ce document ont tous deux pour fonction de lisser la surface libre d'une tranche. La diminution de rugosité basses fréquences est illustrée par la dernière colonne de la table 2 de ce document, qui montre en particulier l'effet du deuxième recuit qui suit le recuit RTA.EP 1 158 581 also discloses a finishing treatment systematically comprising two anneals, one of which is an RTA annealing, these annealing operations being able to be carried out in an atmosphere containing hydrogen or argon. The two anneals taught by this document both have the function of smoothing the free surface of a slice. The reduction in low frequency roughness is illustrated by the last column of table 2 of this document, which shows in particular the effect of the second annealing which follows the RTA annealing.
En effet, avec un traitement sous recuit RTA seul (« exemple comparatif 1 »), la rugosité basses fréquences après traitement est deIndeed, with a treatment using RTA annealing alone (“comparative example 1”), the low frequency roughness after treatment is
1,60nm RMS. En mettant en œuvre les deux recuits enseignés par ce document, la rugosité basses fréquences est sensiblement améliorée, atteignant les valeurs de 0,28nm RMS et 0,30nm RMS.1.60nm RMS. By using the two anneals taught in this document, the low frequency roughness is significantly improved, reaching the values of 0.28nm RMS and 0.30nm RMS.
L'enseignement de EP 1 158 581 est ainsi focalisé sur un enchaînement de deux recuits de lissage (le lissage étant caractérisé par une diminution de la rugosité basses fréquences), le premier de ces deux recuits étant un recuit RTA. Mais le procédé enseigné par EP 1 158 581, comportant systématiquement deux recuits de lissage, est relativement lourd et long à mettre en œuvre.The teaching of EP 1 158 581 is thus focused on a sequence of two smoothing anneals (smoothing being characterized by a reduction in roughness at low frequencies), the first of these two anneals being an RTA annealing. However, the process taught by EP 1 158 581, systematically comprising two smoothing anneals, is relatively cumbersome and time-consuming to implement.
L'invention se propose d'apporter une amélioration aux procédés évoqués ci-dessus. En effet, il serait avantageux de simplifier encore de tels procédés.The invention proposes to provide an improvement to the methods mentioned above. Indeed, it would be advantageous to further simplify such methods.
En outre, il serait également avantageux de réduire les éventuelles lignes de glissement (« slip lines » selon la terminologie anglo-saxonne) qui peuvent apparaître dans la structure cristallographique du matériau de la tranche, en particulier suite à un traitement thermique (tel que celui qui peut être appliqué à la tranche pour provoquer son clivage dans le cadre d'un procédé de type SMARTCUT®).In addition, it would also be advantageous to reduce any slip lines (“slip lines” according to English terminology) which may appear in the crystallographic structure of the wafer material, in particular following a heat treatment (such as that which can be applied to the wafer to cause its cleavage in the context of a SMARTCUT ® type process).
On sait en effet que de telles lignes de glissement peuvent résulter d'inhomogénéités de la chaleur reçue par différentes régions de la tranche (ceci étant plus particulièrement sensible dans le cas de fours présentant des points froids).It is known in fact that such sliding lines can result from inhomogeneities of the heat received by different regions of the wafer (this being more particularly sensitive in the case of ovens having cold points).
Par ailleurs, l'hydrogène utilisé dans les mises en œuvre connues de cette variante est un gaz relativement onéreux, alors qu'on cherche constamment à diminuer les coûts associés aux procédés de traitement des tranches.Furthermore, the hydrogen used in the known implementations of this variant is a relatively expensive gas, while we are looking for constantly reducing costs associated with wafer processing processes.
Enfin, il serait particulièrement avantageux de pouvoir mettre en œuvre un procédé répondant aux objectifs mentionnés ci-dessus, en combinaison avec un procédé du type SMARTCUT®.Finally, it would be particularly advantageous to implement a process that meets the above objectives, in combination with a SMARTCUT ® type process.
Le but de l'invention est de permettre de mettre en œuvre un procédé répondant à ces besoins.The object of the invention is to make it possible to implement a method meeting these needs.
Afin d'atteindre ce but l'invention propose selon un premier aspect un procédé de diminution de la rugosité de la surface libre d'une tranche de matériau semiconducteur, ledit procédé comprenant une étape de recuit afin de lisser ladite surface libre, caractérisé en ce que le procédé de diminution de rugosité de surface libre comporte un unique recuit de lissage réalisé sous la forme d'un recuit thermique rapide sous une atmosphère composée exclusivement d'argon pur. Des aspects préférés, mais non limitatifs du précédé selon l'invention sont les suivants :In order to achieve this aim, the invention proposes, according to a first aspect, a method for reducing the roughness of the free surface of a wafer of semiconductor material, said method comprising an annealing step in order to smooth said free surface, characterized in that that the method for reducing the roughness of the free surface comprises a single smoothing annealing carried out in the form of a rapid thermal annealing in an atmosphere composed exclusively of pure argon. Preferred, but non-limiting aspects of the process according to the invention are the following:
• le procédé comprend également les étapes préalables suivantes : Une étape d'implantation d'atomes, sous une face d'un substrat à partir duquel la tranche doit être réalisée, dans une zone d'implantation du substrat, Une étape de mise en contact intime du substrat implanté avec un raidisseur, et •S Une étape de clivage du substrat implanté au niveau de la zone d'implantation, pour constituer la tranche avec la partie du substrat située entre la surface soumise à l'implantation et la zone d'implantation, et transférer ladite tranche sur le raidisseur,• the process also includes the following preliminary steps: A step of implantation of atoms, under one face of a substrate from which the wafer must be produced, in a zone of implantation of the substrate, A step of bringing into contact intimate substrate implanted with a stiffener, and • S A step of cleaving the implanted substrate at the implantation zone, to form the edge with the part of the substrate located between the surface subjected to implantation and the implantation, and transfer said section to the stiffener,
• le recuit thermique rapide est effectué avec un palier de température dans une gamme comprise entre 1100 et 1250 °C, pendant 5 à 30 secondes, • l'étape de recuit thermique rapide sous argon pur est suivie d'une étape de polissage,• rapid thermal annealing is carried out with a temperature level in a range of between 1100 and 1250 ° C., for 5 to 30 seconds, • the rapid thermal annealing step under pure argon is followed by a polishing step,
• on fait suivre l'étape de polissage par une étape d'oxydation sacrificielle, • on réalise la succession des étapes suivantes : oxydation sacrificielle, recuit thermique rapide sous argon pur, polissage, oxydation sacrificielle.• the polishing step is followed by a sacrificial oxidation step, • the following stages are carried out: sacrificial oxidation, rapid thermal annealing under pure argon, polishing, sacrificial oxidation.
• on fait suivre l'étape de recuit thermique rapide sous argon pur par les étapes suivantes : oxydation sacrificielle, -/ polissage, oxydation sacrificielle.• the rapid thermal annealing step under pure argon is followed by the following steps: sacrificial oxidation, - / polishing, sacrificial oxidation.
• on réalise la succession des étapes suivantes : recuit thermique rapide sous argon pur,• the following stages are carried out: rapid thermal annealing under pure argon,
• polissage, recuit thermique rapide sous argon pur. • on fait précéder l'étape de recuit thermique rapide sous argon pur par une étape d'oxydation sacrificielle, • polishing, rapid thermal annealing under pure argon. • the rapid thermal annealing step under pure argon is preceded by a sacrificial oxidation step,
• on fait suivre l'étape de recuit thermique rapide sous argon pur par une étape d'oxydation sacrificielle,• the rapid thermal annealing step under pure argon is followed by a sacrificial oxidation step,
• on fait précéder l'étape de recuit thermique rapide sous argon pur par une étape d'oxydation sacrificielle, et on fait suivre ladite étape de recuit thermique rapide sous argon pur par une étape supplémentaire d'oxydation sacrificielle.• the rapid thermal annealing step under pure argon is preceded by a sacrificial oxidation step, and said rapid thermal annealing step under pure argon is followed by an additional sacrificial oxidation step.
L'invention propose selon un deuxième aspect une structure SOI obtenue par un tel procédé. D'autres aspects, buts et avantages de l'invention apparaîtront mieux à la lecture de la description suivante de formes préférées de réalisation de l'invention, faite en référence aux dessins annexés sur lesquels :The invention proposes according to a second aspect an SOI structure obtained by such a method. Other aspects, aims and advantages of the invention will appear better on reading the following description of preferred embodiments of the invention, given with reference to the appended drawings in which:
• la figure 1 est une représentation générale et schématique en coupe longitudinale d'une chambre de recuit permettant de mettre en œuvre l'invention, • la figure 2 est un graphe illustrant la diminution de rugosité obtenue par la mise en œuvre de l'invention sur une tranche de silicium.FIG. 1 is a general and schematic representation in longitudinal section of an annealing chamber enabling the invention to be implemented, • Figure 2 is a graph illustrating the reduction in roughness obtained by the implementation of the invention on a silicon wafer.
En référence tout d'abord à la figure 1, on a représenté schématiquement un exemple non limitatif de chambre de_ recuit 1 permettant de mettre en œuvre l'invention.Referring first to Figure 1, there is shown schematically a non-limiting example of de_ annealing chamber 1 for implementing the invention.
Cette chambre est destinée à la mise en œuvre d'une étape de recuit sous atmosphère d'argon pure selon le mode opératoire RTA.This chamber is intended for the implementation of an annealing step under a pure argon atmosphere according to the RTA operating mode.
Cette chambre 1 comporte une enceinte 2, un réacteur 4, un plateau porte substrat 6, deux réseaux de lampes halogènes 8, 10 et deux paires de lampes latérales.This chamber 1 comprises an enclosure 2, a reactor 4, a substrate carrier plate 6, two networks of halogen lamps 8, 10 and two pairs of side lamps.
L'enceinte 2 comporte en particulier une paroi inférieure 12, une paroi supérieure 14 et deux parois latérales 16, 18, situées respectivement aux extrémités longitudinales de l'enceinte 2. L'une des parois latérales 16, 18 comporte une porte 20. Le réacteur 4 est constitué d'un tube de quartz s'étendant longitudinalement entre les deux parois latérales 16, 18. Il est muni au niveau de chacune de ces parois latérales 16, 18, respectivement d'une entrée de gaz 21 et d'une sortie de gaz 22. La sortie de gaz 22 est située du côté de la paroi latérale 18 comportant la porte 20. Chaque réseau de lampes halogènes 8,10 est situé respectivement au-dessus et en dessous du réacteur 4, entre celui-ci et les parois inférieure 12 et supérieure 14.The enclosure 2 comprises in particular a lower wall 12, an upper wall 14 and two side walls 16, 18, situated respectively at the longitudinal ends of the enclosure 2. One of the side walls 16, 18 comprises a door 20. The reactor 4 consists of a quartz tube extending longitudinally between the two side walls 16, 18. It is provided at each of these side walls 16, 18, respectively with a gas inlet 21 and a gas outlet 22. The gas outlet 22 is located on the side of the side wall 18 comprising the door 20. Each network of halogen lamps 8, 10 is located respectively above and below the reactor 4, between the latter and the lower 12 and upper 14 walls.
Chaque réseau de lampes halogènes 8, 10 comporte 17 lampes 26 disposées perpendiculairement à l'axe longitudinal du réacteur 4. Les deux paires de lampes latérales (non représentées sur la figureEach network of halogen lamps 8, 10 comprises 17 lamps 26 arranged perpendicular to the longitudinal axis of the reactor 4. The two pairs of side lamps (not shown in the figure
1) sont situées parallèlement à l'axe longitudinal du réacteur 4, chacune d'un côté de celui-ci, globalement aux extrémités longitudinales des lampes 26 des réseaux de lampes halogènes 8, 10.1) are located parallel to the longitudinal axis of the reactor 4, each on one side thereof, generally at the longitudinal ends of the lamps 26 of the halogen lamp networks 8, 10.
Le plateau porte-substrat 6 coulisse dans le réacteur 4. Il supporte une tranche 50 destinée à subir l'étape de recuit sous atmosphère hydrogénée 100 et permet de les rentrer ou de les sortir de la chambre 1. Une chambre 1 de ce type est commercialisée par STEAG®, sous le nom «SHS AST 2800».The substrate-holder plate 6 slides in the reactor 4. It supports a wafer 50 intended to undergo the annealing step under a hydrogenated atmosphere 100 and allows them to be brought in or taken out of the chamber 1. A room 1 of this type is marketed by STEAG ®, as "SHS AST 2800".
On précise que la « tranche » 50 peut être, de manière générale, tout type de structure monocouche ou multicouche comportant une couche superficielle d'un matériau semiconducteur (tel que le silicium, de" manière préférée mais non limitative).It is specified that the "wafer" 50 can be, in general, any type of monolayer or multilayer structure comprising a surface layer of a semiconductor material (such as silicon, "in a preferred but non-limiting manner).
On rappelle en effet qu'un but de l'invention est de permettre de diminuer la rugosité de la surface libre d'une telle couche superficielle.It is in fact recalled that an object of the invention is to make it possible to reduce the roughness of the free surface of such a surface layer.
L'invention peut en effet être mis en œuvre pour diminuer la rugosité de la surface libre d'une tranche 50 n'ayant subi aucun traitement préalable mais également de tranches obtenues par des traitements spécifiques.The invention can in fact be implemented to reduce the roughness of the free surface of a wafer 50 which has not undergone any prior treatment but also wafers obtained by specific treatments.
En particulier, les différentes variantes de l'invention s'appliquent de manière particulièrement avantageuse à la diminution de la rugosité des surfaces d'une structure SOI et/ou du substrat de matériau semiconducteur dont une telle structure est issue, en particulier par suite de l'application d'un procédé de type SMARTCUT®.In particular, the various variants of the invention apply in a particularly advantageous manner to the reduction of the roughness of the surfaces of an SOI structure and / or of the substrate of semiconductor material from which such a structure is derived, in particular as a result of the application of a SMARTCUT ® type process.
Ainsi, dans le cadre du procédé SMARTCUT® l'invention pourra être mise en œuvre avec profit pour diminuer la rugosité de l'une ou l'autre des deux surfaces de matériau semiconducteur qui sont issues du clivage de la zone de fragilisation réalisée lors de l'étape d'implantation, ou de ces deux surfaces.Thus, under the SMARTCUT ® method the invention can be implemented with advantage to decrease the roughness of the one or the other of the two surfaces of semiconductor material that resulted from the cleavage of the zone of weakness formed during the implantation stage, or of these two surfaces.
Et les différentes variantes de mise en œuvre du procédé selon l'invention qui vont être décrites ci-dessous à titre d'exemple, sont appliquées au traitement de tranches 50 comportant une couche utile de matériau semiconducteur 52 (réalisée par exemple en silicium), ladite couche ayant elle-même une surface libre 54.And the different implementation variants of the method according to the invention which will be described below by way of example, are applied to the processing of wafers 50 comprising a useful layer of semiconductor material 52 (made for example of silicon), said layer itself having a free surface 54.
La couche 52 est désignée comme « utile » car elle servira à la constitution des éléments électroniques, optiques ou opto-électroniques sur la tranche 50. Comme mentionné ci-dessus la surface libre 54 peut être une surface de clivage obtenue par la mise en œuvre d'un procédé SMARTCUT®. Dans le cas où la tranche 50 est un substrat SOI issu du procédé SMARTCUT®, la tranche 50 comporte sous la couche utile 52 une couche d'oxyde enterrée, qui recouvre elle-même un substrat support.The layer 52 is designated as “useful” because it will be used for the constitution of the electronic, optical or opto-electronic elements on the wafer 50. As mentioned above, the free surface 54 may be a cleavage surface obtained by the implementation of a SMARTCUT ® process. In the case where the wafer 50 is an SOI substrate from the process SMARTCUT ®, the wafer 50 comprises in the useful layer 52 a buried oxide layer which covers itself a support substrate.
On précise que sur la figure 1, l'épaisseur de la tranche 50 a été exagérée pour faire apparaître la couche utile 52 et sa surface libre" 54.It is specified that in FIG. 1, the thickness of the wafer 50 has been exaggerated to reveal the useful layer 52 and its free surface " 54.
L'invention peut ainsi être mise en œuvre uniquement en effectuant une étape de recuit RTA de la tranche 50, sous atmosphère d'argon pur.The invention can thus be implemented only by performing an RTA annealing step of the wafer 50, under an atmosphere of pure argon.
L'étape de recuit sous argon pur comprend les étapes consistant à :The annealing step under pure argon comprises the steps consisting in:
• disposer la tranche 50 dans la chambre 1, celle-ci étant froide au moment de l'introduction de la tranche,• place the slice 50 in the chamber 1, the latter being cold when the slice is introduced,
• introduire dans la chambre, à une pression égale ou voisine de la pression atmosphérique, une atmosphère de recuit d'argon pur. On précise que la pression peut également être fixée à une valeur plus basse, qui peut aller de quelques mTorr à la pression atmosphérique, • faire croître, en allumant les lampes halogènes 26, la température dans la chambre 1 , à une vitesse de l'ordre de 50°C par seconde, jusqu'à une température de traitement,• introduce into the chamber, at a pressure equal to or close to atmospheric pressure, an atmosphere of pure argon annealing. It is specified that the pressure can also be fixed at a lower value, which can range from a few mTorr to atmospheric pressure, • increase, by lighting the halogen lamps 26, the temperature in chamber 1, at a speed of order of 50 ° C per second, up to a processing temperature,
• maintenir la tranche 50 dans la chambre 1 , pendant une durée de palier de chauffage, • éteindre les lampes halogènes 26 et refroidir, par circulation d'air, la tranche 50, à une vitesse de plusieurs dizaines de degrés centigrades par seconde et variant selon toute loi désirée.• maintain section 50 in room 1, for a heating stage duration, • switch off the halogen lamps 26 and cool, by air circulation, section 50, at a speed of several tens of degrees centigrade per second and varying according to any desired law.
A cet égard, il est particulièrement important que l'argon mis en œuvre soit le plus pur possible car la Demanderesse a constaté que la présence de faibles quantités d'éléments supplémentaires (tels que l'oxygène notamment) pouvaient conduire à une attaque du matériau de la couche utile (formation de SiO très volatile dans le cas d'une couche superficielle en silicium exposée à une atmosphère de recuit comportant une faible quantité d'oxygène, par exemple). Et la Demanderesse a constaté qu'une telle étape de recuit sous atmosphère d'argon, pur permettait de diminuer de manière sensible la rugosité de la surface libre 54. Les résultats obtenus étaient en particulier de bien meilleure qualité que la diminution de rugosité qui peut être obtenue seulement par un traitement classique tel qu'un traitement thermique de type oxydation sacrificielle. Et l'uniformité de la couche utile est par ailleurs bien meilleure que si on avait soumis la tranche à une opération de polissage.In this regard, it is particularly important that the argon used is as pure as possible because the Applicant has found that the presence of small amounts of additional elements (such as oxygen in particular) could lead to an attack on the material. of the useful layer (formation of very volatile SiO in the case of a silicon surface layer exposed to an annealing atmosphere comprising a small amount of oxygen, for example). And the Applicant has found that such a step of annealing under an atmosphere of pure argon made it possible to significantly reduce the roughness of the free surface 54. The results obtained were in particular of much better quality than the reduction in roughness which can be obtained only by a conventional treatment such as a heat treatment of sacrificial oxidation type. And the uniformity of the useful layer is also much better than if the slice had been subjected to a polishing operation.
L'étape de recuit RTA sous argon pur peut par exemple comprendre un palier de chauffage d'une durée de 5 à 30 secondes, à une température de traitement comprise entre 1100 et 1250°C. La figure 2 illustre la diminution de rugosité par un tel procédé. Plus précisément cette figure expose le gain de « haze » obtenu suite à l'application d'un procédé selon l'invention tel que mentionné ci-dessus.The RTA annealing step under pure argon can for example comprise a heating stage lasting 5 to 30 seconds, at a treatment temperature of between 1100 and 1250 ° C. FIG. 2 illustrates the reduction in roughness by such a method. More precisely, this figure shows the gain in “haze” obtained following the application of a method according to the invention as mentioned above.
Sur cette figure, l'axe des abscisses permet de parcourir différentes tranches, le haze ayant été mesuré pour chacune de ces tranches avant l'application d'un recuit selon l'invention (mesure du haut), et après (mesure du bas).In this figure, the abscissa axis makes it possible to browse different slices, the haze having been measured for each of these slices before the application of an annealing according to the invention (measurement from the top), and after (measurement from the bottom) .
Sur la figure 2, la courbe du haut correspond ainsi à un haze mesuré à la surface de structures SOI après clivage, et la courbe du bas aux mêmes mesures, effectuées après un recuit RTA sous argon par 1230°C avec un palier de chauffage de 30s.In FIG. 2, the upper curve thus corresponds to a haze measured on the surface of SOI structures after cleavage, and the lower curve to the same measurements, carried out after an RTA annealing under argon at 1230 ° C. with a heating stage of 30s.
On précise que le terme « haze » désigne le signal optique diffusé par la surface du substrat 50, en réponse à une excitation lumineuse. Ce haze est représentatif de la rugosité de surface.It is specified that the term “haze” designates the optical signal scattered by the surface of the substrate 50, in response to a light excitation. This haze is representative of the surface roughness.
Cette caractéristique qui est représentative de la rugosité de la surface du substrat est dans le cas présent mesuré par un équipement de type KLA Tencor® , modèle Surfscan 6220® : le haze mesuré ici est ainsi désigné par la référence « haze 6220 ».This characteristic which is representative of the surface roughness of the substrate is in this case measured by a Type KLA Tencor ® equipment, model Surfscan 6220 ®: the haze measured here is so designated by the reference "haze 6220".
On observe que la diminution de haze 6220 est d'un niveau comparable aux résultats que l'on peut obtenir par d'autres techniques de recuit RTA, par exemple des recuits RTA sous atmosphère composés d'un mélange d'hydrogène et d'argon. Plus précisément, le gain de haze correspond à une division de haze par un facteur de l'ordre de 6 à 10.It is observed that the reduction in haze 6220 is of a level comparable to the results which can be obtained by other RTA annealing techniques, for example RTA annealing in an atmosphere composed of a mixture of hydrogen and argon . More precisely, the gain of haze corresponds to a division of haze by a factor of the order of 6 to 10.
Et de manière avantageuse, la mise en œuvre du procédé selon l'invention permet d'obtenir des résultats de ce haut niveau de qualité en s'affranchissant des limitations mentionnées ci-dessus à propos dés recuits RTA connus.And advantageously, the implementation of the method according to the invention makes it possible to obtain results of this high level of quality by overcoming the limitations mentioned above with regard to known RTA annealing.
En particulier, l'argon étant un excellent conducteur thermique, la mise en œuvre d'une atmosphère d'argon pur permet de distribuer la chaleur de la manière la plus homogène possible à l'intérieur de la chambre 1 , et de réduire ainsi les lignes de glissement que l'on peut observer dans le cas de la mise en œuvre de ces procédés connus.In particular, argon being an excellent thermal conductor, the implementation of an atmosphere of pure argon makes it possible to distribute the heat in the most homogeneous way possible inside the chamber 1, and thus to reduce the slip lines that can be observed in the case of the implementation of these known methods.
Comme on l'a dit, l'invention peut être mise en œuvre seulement par l'étape de recuit RTA sous argon pur : cette étape permet d'obtenir une amélioration considérable de l'état de surface de la tranche 50. Et cette amélioration est obtenue pratiquement sans retirer de matière à la tranche, mais au contraire par reconstruction de la surface 54 et lissage.As has been said, the invention can be implemented only by the RTA annealing step under pure argon: this step makes it possible to obtain a considerable improvement in the surface condition of the wafer 50. And this improvement is obtained practically without removing material from the wafer, but on the contrary by reconstruction of the surface 54 and smoothing.
On va maintenant décrire ci-dessous plusieurs variantes de mise en œuvre de l'invention, qui impliquent outre l'étape de recuit RTA sous argon pur des étapes de traitement complémentaires.We will now describe below several alternative embodiments of the invention, which involve, in addition to the RTA annealing step under pure argon, additional treatment steps.
Selon une première variante, on fait suivre l'étape de recuit RTA sous argon pur par une étape de polissage de la surface de la tranche 50.According to a first variant, the step of annealing RTA under pure argon is followed by a step of polishing the surface of the wafer 50.
Cette étape de polissage est réalisée par un polissage mécano- chimique, connu en soi. Elle permet de retirer la matière de la couche utile 52 qui est située à proximité de la surface libre 54 et qui peut encore comporter des défauts superficiels.This polishing step is carried out by chemical mechanical polishing, known per se. It makes it possible to remove the material from the useful layer 52 which is located near the free surface 54 and which may also have surface defects.
Selon une deuxième variante, on fait suivre l'étape de recuit RTA sous argon pur non seulement par une étape de polissage, mais en outre ensuite par une étape supplémentaire d'oxydation sacrificielle combinée à un traitement thermique. L'étape d'oxydation sacrificielle est destinée à retirer les défauts restant éventuellement après l'étape de polissage. Dans le cas de la mise en œuvre de l'invention après un procédé SMARTCUT®, les défauts peuvent être liés aux étapes d'implantation ou de clivage. L'étape d'oxydation sacrificielle se décompose en une étape d'oxydation et une étape de désoxydation.According to a second variant, the step of annealing RTA under pure argon is followed not only by a polishing step, but also then by an additional sacrificial oxidation step combined with a heat treatment. The sacrificial oxidation step is intended to remove the defects possibly remaining after the polishing step. In the case of the implementation of the invention after a SMARTCUT ® process, the defects may be related to implantation steps or cleavage. The sacrificial oxidation step is broken down into an oxidation step and a deoxidation step.
Le traitement thermique est intercalé entre l'étape d'oxydation et l'étape de désoxydation.The heat treatment is interposed between the oxidation step and the deoxidation step.
L'étape d'oxydation est préférentiellement réalisée à une température comprise entre 700°C et 1100°C.The oxidation step is preferably carried out at a temperature between 700 ° C and 1100 ° C.
L'étape d'oxydation peut être réalisée par voie sèche ou par voie humide.The oxidation step can be carried out dry or wet.
Par voie sèche, l'étape d'oxydation est, par exemple, menée en chauffant la tranche 50 sous oxygène gazeux. Par voie humide, l'étape d'oxydation est, par exemple, menée en chauffant la tranche 50 dans une atmosphère chargée en vapeur d'eau.By the dry route, the oxidation step is, for example, carried out by heating the wafer 50 under gaseous oxygen. By wet, the oxidation step is, for example, carried out by heating the wafer 50 in an atmosphere charged with water vapor.
Par voie sèche ou par voie humide, selon les procédés classiques connus de l'homme du métier, l'atmosphère d'oxydation peut aussi être chargée en acide chlorhydrique. L'étape d'oxydation aboutit à la formation d'un oxyde 60 qui recouvre la surface 54 de la couche utile 52.Dry or wet, according to conventional methods known to those skilled in the art, the oxidation atmosphere can also be loaded with hydrochloric acid. The oxidation step results in the formation of an oxide 60 which covers the surface 54 of the useful layer 52.
L'étape de traitement thermique est réalisée par toute opération thermique destinée à améliorer les qualités du matériau constitutif de la couche utile 52. Ce traitement thermique peut être effectué à température constante ou à température variable.The heat treatment step is carried out by any thermal operation intended to improve the qualities of the material constituting the useful layer 52. This heat treatment can be carried out at constant temperature or at variable temperature.
Dans ce dernier cas, le traitement thermique est réalisé, par exemple, avec une augmentation progressive de la température entre deux valeurs, ou avec une oscillation cyclique entre deux valeurs, etc. Préférentiellement, l'étape de traitement thermique est effectuée au moins en partie à une température supérieure à 1000°C, et plus y particulièrement vers 1100-1200°C. Ce traitement thermique est de préférence effectué sous une atmosphère non oxydante, qui peut comprendre de l'argon, de l'azote, de l'hydrogène, etc., ou encore un mélange de ces gaz. Le traitement thermique peut également être réalisé sous vide. Préférentiellement aussi, l'étape d'oxydation est réalisée avant l'étape de traitement thermique.In the latter case, the heat treatment is carried out, for example, with a gradual increase in temperature between two values, or with a cyclic oscillation between two values, etc. Preferably, the heat treatment step is carried out at least in part at a temperature above 1000 ° C., and more particularly there around 1100-1200 ° C. This heat treatment is preferably carried out under a non-oxidizing atmosphere, which can include argon, nitrogen, hydrogen, etc., or a mixture of these gases. The heat treatment can also be carried out under vacuum. Also preferably, the oxidation step is carried out before the heat treatment step.
De cette manière, l'oxyde 60 protège le reste de la couche utile pendant le traitement thermique et évite le phénomène de piquage.In this way, the oxide 60 protects the rest of the useful layer during the heat treatment and avoids the pitting phenomenon.
Le phénomène de piquage est bien connu de l'homme du métier qui le nomme aussi « pitting ». Il se produit à la surface de certains semiconducteurs lorsque ceux-ci sont recuits sous atmosphère non oxydante, telle que l'azote, l'argon, sous vide, etc. Il se produit dans le cas du silicium en particulier lorsque celui-ci est à nu, c'est-à-dire lorsqu'il n'est pas du tout recouvert d'oxyde. Selon une variante avantageuse, l'étape d'oxydation débute avec le début de la montée en température du traitement thermique et se termine avant la fin de ce dernier.The stitching phenomenon is well known to a person skilled in the art, who also calls it "pitting". It occurs on the surface of certain semiconductors when they are annealed under a non-oxidizing atmosphere, such as nitrogen, argon, under vacuum, etc. It occurs in the case of silicon, in particular when the latter is bare, that is to say when it is not at all covered with oxide. According to an advantageous variant, the oxidation step begins with the start of the rise in temperature of the heat treatment and ends before the end of the latter.
Le traitement thermique permet de guérir au moins en partie, les défauts générés au cours des étapes précédentes du procédé de fabrication et de traitement de la tranche 50.The heat treatment makes it possible to cure, at least in part, the defects generated during the preceding stages of the manufacturing and treatment process of the wafer 50.
Plus particulièrement, le traitement thermique peut être effectué pendant une durée et à une température telles que l'on réalise par celui-ci une guérison de défauts cristallins, tels que des fautes d'empilement, des défauts « HF », etc., engendrés dans la couche utile 52, au cours de l'étape d'oxydation.More particularly, the heat treatment can be carried out for a duration and at a temperature such that it achieves a healing of crystalline defects, such as stacking faults, “HF” defects, etc., generated in the useful layer 52, during the oxidation step.
On appelle défaut « HF », un défaut dont la présence est relevée par une auréole de décoration dans l'oxyde enterré qui est situé sous la couche utile 52 (cas où la tranche 50 est un SOI issu d'un procédé SMARTCUT®), après traitement de la tranche dans un bain d'acide fluorhydrique. Le traitement thermique présente en outre l'avantage de renforcer l'interface de collage, par exemple entre la couche transférée lors du transfert par le procédé SMARTCUT® et le substrat support. L'étape de désoxydation est préférentiellement réalisée en solution."HF" is called fault, a fault whose presence is detected by a decorative halo in the buried oxide that is located under the active layer 52 (the case where the wafer 50 is an SOI process from a SMARTCUT ®) after treatment of the slice in a hydrofluoric acid bath. The present heat treatment also has the advantage to strengthen the bonding interface, for example between the transferred layer during transfer by the SMARTCUT ® process and the support substrate. The deoxidation step is preferably carried out in solution.
Cette solution est par exemple une solution d'acide fluorhydrique à 10 ou 20%. Quelques minutes suffisent pour enlever mille à quelques milliers d'angstrôms d'oxyde 60, en plongeant la tranche 50 dans une telle solution.This solution is for example a 10 or 20% hydrofluoric acid solution. A few minutes are enough to remove a thousand to a few thousand angstroms of oxide 60, by immersing the slice 50 in such a solution.
Selon une troisième variante, on fait précéder les étapes de la deuxième variante décrite ci-dessus d'une étape supplémentaire d'oxydation sacrificielle de la surface de la tranche 50, cette étape d'oxydation sacrificielle (identique à celle décrite ci-dessus) étant de préférence combinée à un traitement thermique.According to a third variant, the steps of the second variant described above are preceded by an additional sacrificial oxidation step of the surface of the wafer 50, this sacrificial oxidation step (identical to that described above) preferably being combined with heat treatment.
Les étapes de recuit RTA sous argon pur et de polissage mécano- chimique de cette variante sont identiques à celles décrites pour les autres variantes décrites ci-dessus.The steps of annealing RTA under pure argon and of chemical-mechanical polishing of this variant are identical to those described for the other variants described above.
Les première et deuxième étapes d'oxydation sacrificielle se décomposent, comme l'étape d'oxydation sacrificielle décrite ci-dessus, en une étape d'oxydation et une étape de désoxydation.The first and second sacrificial oxidation steps, like the sacrificial oxidation step described above, are broken down into an oxidation step and a deoxidation step.
Les première et deuxième étapes d'oxydation sacrificielle ainsi que les étapes de traitement thermique sont analogues à celles déjà décrites pour la deuxième variante décrite ci-dessus, du procédé conforme à la présente invention.The first and second sacrificial oxidation steps as well as the heat treatment steps are similar to those already described for the second variant described above, of the process according to the present invention.
Selon une quatrième variante de l'invention, on fait suivre l'étape de recuit RTA sous argon pur par deux étapes d'oxydation sacrificielle de la surface libre de la tranche 50.According to a fourth variant of the invention, the step of annealing RTA under pure argon is followed by two steps of sacrificial oxidation of the free surface of the wafer 50.
Ces étapes d'oxydation sacrificielles sont identiques à celles décrites ci-dessus et peuvent de préférence être combinées avec un traitement thermique comme décrit ci-dessus.These sacrificial oxidation steps are identical to those described above and can preferably be combined with a heat treatment as described above.
Dans cette variante, une étape supplémentaire de polissage mécano-chimique est intercalée entre les deux étapes d'oxydation sacrificielle. Selon une cinquième variante de l'invention, on effectue sur la tranche 50 deux étapes de recuit RTA sous argon pur, en intercalant entre ces deux étapes une étape de polissage mécano-chimique. Selon une sixième variante de l'invention, on effectue une étape d'oxydation sacrificielle de la surface de la tranche 50 (étape toujours identique à celles décrites ci-dessus, et de préférence combinée avec un traitement thermique), après quoi on fait subir à la tranche 50 un recuit RTA sous atmosphère d'argon pur.In this variant, an additional mechanical-chemical polishing step is inserted between the two sacrificial oxidation steps. According to a fifth variant of the invention, two steps of annealing RTA under pure argon are carried out on the wafer 50, by interposing between these two steps a chemical-mechanical polishing step. According to a sixth variant of the invention, a step of sacrificial oxidation of the surface of the wafer 50 is carried out (step always identical to those described above, and preferably combined with a heat treatment), after which it is subjected to at section 50, an RTA annealing under an atmosphere of pure argon.
Selon une septième variante de l'invention, on inverse l'ordre des deux étapes principales de la sixième variante, en réalisant le recuit RTA sous argon pur avant l'oxydation sacrificielle.According to a seventh variant of the invention, the order of the two main stages of the sixth variant is reversed, by carrying out the RTA annealing under pure argon before the sacrificial oxidation.
Selon une huitième variante de l'invention, on intercale entre deux étapes d'oxydation sacrificielle (toujours identiques à celles décrites ci- dessus, et de préférence combinées avec un traitement thermique) de la surface de la tranche 50, une étape de recuit RTA de la tranche sous argon pur.According to an eighth variant of the invention, between two sacrificial oxidation steps (always identical to those described above, and preferably combined with a heat treatment) of the surface of the wafer 50, an RTA annealing step of the slice under pure argon.
On remarquera que les différentes variantes de l'invention qui ont été décrites ci-dessus mettent toutes en œuvre un seul recuit de lissage.It will be noted that the different variants of the invention which have been described above all implement a single smoothing annealing.
Cet unique recuit de lissage correspond au recuit thermique rapide sous une atmosphère composée exclusivement d'argon pur.This unique smoothing annealing corresponds to rapid thermal annealing in an atmosphere composed exclusively of pure argon.
Et certaines de ces variantes peuvent en outre faire intervenir d'autres types de recuit, ces recuits n'étant quant à eux pas destinés à lisser la surface libre de la tranche.And some of these variants can also involve other types of annealing, these annealing being not intended to smooth the free surface of the wafer.
En particulier, les traitements thermiques associés aux opérations d'oxydation sacrificielle sont destinés à retirer de la matière et à renforcer les interfaces de collage, et non à lisser la surface libre de la tranche.In particular, the heat treatments associated with sacrificial oxidation operations are intended to remove material and strengthen the bonding interfaces, and not to smooth the free surface of the wafer.
Et on précise que si les opérations d'oxydation sacrificielle peuvent avoir un effet sur la rugosité de la surface libre de la tranche, cet effet n'a pas de commune mesure avec l'effet qui est recherché lors d'unAnd it is specified that if the sacrificial oxidation operations can have an effect on the roughness of the free surface of the wafer, this effect has no common measure with the effect which is sought during a
« lissage », qui vise comme on l'a dit à diminuer sensiblement la rugosité basses fréquences de la surface libre de la tranche."Smoothing", which aims, as has been said, to significantly reduce the low frequency roughness of the free surface of the wafer.
On peut ainsi typiquement diminuer la rugosité basses fréquences de la surface libre d'une tranche d'un facteur 1 à 2 par une technique d'oxydation sacrificielle, alors que cette diminution est de l'ordre d'un facteur 10 par un recuit de type RTA (on pourra à cet égard se référer au tableau de la page 19 du document FR 2 797713).It is thus typically possible to reduce the low frequency roughness of the free surface of a wafer by a factor of 1 to 2 by a sacrificial oxidation technique, while this reduction is of the order of one factor 10 by an annealing of the RTA type (one can in this respect refer to the table on page 19 of the document FR 2 797713).
On précise ainsi en particulier que des enseignements relatifs aux traitements thermiques associés à une oxydation sacrificielle répondent à un besoin bien différent d'un objectif de lissage.It is thus specified in particular that lessons relating to heat treatments associated with sacrificial oxidation meet a very different need for a smoothing objective.
En particulier, les enseignements du document FR 2 777115 qui sont relatifs à de tels traitements thermiques compris dans une opération d'oxydation sacrificielle et qui mentionnent la possibilité d'utiliser une atmosphère d'argon, ne sont pas transposables au cas de la présente invention dont un élément essentiel réside dans le traitement thermique en mode RTA.In particular, the teachings of document FR 2 777 115 which relate to such heat treatments included in a sacrificial oxidation operation and which mention the possibility of using an argon atmosphere, cannot be transposed to the case of the present invention an essential element of which is the heat treatment in RTA mode.
Une caractéristique essentielle et commune à toutes les variantes qui viennent d'être décrites est donc que le procédé de diminution de rugosité de surface libre comporte un unique recuit de lissage réalisé sous la forme d'un recuit thermique rapide sous une atmosphère composée exclusivement d'argon pur. An essential characteristic common to all the variants which have just been described is therefore that the method for reducing the roughness of the free surface comprises a single smoothing annealing carried out in the form of a rapid thermal annealing in an atmosphere composed exclusively of pure argon.

Claims

REVENDICATIONS
1. Procédé de diminution de la rugosité de la surface libre d'une tranche de matériau semiconducteur, ledit procédé comprenant une étape de recuit afin de lisser ladite surface libre, caractérisé en ce que le procédé de diminution de rugosité de surface libre comporte un unique recuit de lissage réalisé sous la forme d'un recuit thermique rapide sous une atmosphère composée exclusivement d'argon pur.1. Method for reducing the roughness of the free surface of a wafer of semiconductor material, said method comprising an annealing step in order to smooth said free surface, characterized in that the method for reducing roughness of free surface comprises a single smoothing annealing carried out in the form of a rapid thermal annealing in an atmosphere composed exclusively of pure argon.
2. Procédé selon la revendication précédente, caractérisé en ce que le procédé comprend également les étapes préalables suivantes :2. Method according to the preceding claim, characterized in that the method also comprises the following preliminary steps:
• Une étape d'implantation d'atomes, sous une face d'un substrat à partir duquel la tranche doit être réalisée, dans une zone d'implantation du substrat,A step of implantation of atoms, under a face of a substrate from which the wafer must be produced, in a zone of implantation of the substrate,
• Une étape de mise en contact intime du substrat implanté avec un raidisseur, etA step of bringing the implanted substrate into intimate contact with a stiffener, and
• Une étape de clivage du substrat implanté au niveau de la zone d'implantation, pour constituer la tranche avec la partie du substrat située entre la surface soumise à l'implantation et la zone d'implantation, et transférer ladite tranche sur le raidisseur.• A step of cleaving the implanted substrate at the implantation area, to form the wafer with the part of the substrate located between the surface subjected to the implantation and the implantation area, and transfer said wafer to the stiffener.
3. Procédé selon l'un des revendications précédentes, caractérisé en ce que le recuit thermique rapide est effectué avec un palier de température dans une gamme comprise entre 1100 et 1250 °C, pendant 5 à 30 secondes.3. Method according to one of the preceding claims, characterized in that the rapid thermal annealing is carried out with a temperature level in a range between 1100 and 1250 ° C, for 5 to 30 seconds.
4. Procédé selon l'une des revendications précédentes, caractérisé en ce que l'étape de recuit thermique rapide sous argon pur est suivie d'une étape de polissage. 4. Method according to one of the preceding claims, characterized in that the rapid thermal annealing step under pure argon is followed by a polishing step.
5. Procédé selon la revendication précédente, caractérisé en ce qu'on fait suivre l'étape de polissage par une étape d'oxydation sacrificielle.5. Method according to the preceding claim, characterized in that the polishing step is followed by a sacrificial oxidation step.
6. Procédé selon l'une des revendications 1 à 3, caractérisé en ce qu'on réalise la succession des étapes suivantes :6. Method according to one of claims 1 to 3, characterized in that the following steps are carried out:
• oxydation sacrificielle,• sacrificial oxidation,
• recuit thermique rapide sous argon pur,• rapid thermal annealing under pure argon,
• polissage,• polishing,
• oxydation sacrificielle.• sacrificial oxidation.
7. Procédé selon l'une des revendications 1 à 3, caractérisé en ce qu'on fait suivre l'étape de recuit thermique rapide sous argon pur par les étapes suivantes :7. Method according to one of claims 1 to 3, characterized in that the rapid thermal annealing step under pure argon is followed by the following steps:
• oxydation sacrificielle, • polissage,• sacrificial oxidation, • polishing,
• oxydation sacrificielle.• sacrificial oxidation.
8. Procédé selon l'une des revendications 1 à 3, caractérisé en ce qu'on réalise la succession des étapes suivantes : • recuit thermique rapide sous argon pur,8. Method according to one of claims 1 to 3, characterized in that the following steps are carried out: • rapid thermal annealing under pure argon,
• polissage,• polishing,
• recuit thermique rapide sous argon pur.• rapid thermal annealing under pure argon.
9. Procédé selon l'une des revendications 1 à 3, caractérisé en ce qu'on fait précéder l'étape de recuit thermique rapide sous argon pur par une étape d'oxydation sacrificielle.9. Method according to one of claims 1 to 3, characterized in that precedes the rapid thermal annealing step under pure argon by a sacrificial oxidation step.
10. Procédé selon l'une des revendications 1 à 3, caractérisé en ce qu'on fait suivre l'étape de recuit thermique rapide sous argon pur par une étape d'oxydation sacrificielle. 10. Method according to one of claims 1 to 3, characterized in that the step of rapid thermal annealing under pure argon is followed by a sacrificial oxidation step.
11. Procédé selon l'une des revendications 1 à 3, caractérisé en ce qu'on fait précéder l'étape de recuit thermique rapide sous argon pur par une étape d'oxydation sacrificielle, et on fait suivre ladite étape de recuit thermique rapide sous argon pur par une étape supplémentaire d'oxydation sacrificielle.11. Method according to one of claims 1 to 3, characterized in that the step of rapid thermal annealing under pure argon is preceded by a sacrificial oxidation step, and said step of rapid thermal annealing is followed pure argon by an additional sacrificial oxidation step.
12. Structure SOI obtenue par un procédé selon l'une des revendications précédentes. 12. SOI structure obtained by a process according to one of the preceding claims.
EP20020782466 2001-07-04 2002-07-04 Method for reducing surface rugosity Withdrawn EP1412972A2 (en)

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FR0108859A FR2827078B1 (en) 2001-07-04 2001-07-04 METHOD FOR REDUCING SURFACE ROUGHNESS
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9986892B2 (en) 2010-09-20 2018-06-05 Endochoice, Inc. Operational interface in a multi-viewing element endoscope

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7749910B2 (en) 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
US7883628B2 (en) 2001-07-04 2011-02-08 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
WO2005055308A1 (en) * 2003-12-03 2005-06-16 S.O.I.Tec Silicon On Insulator Technologies Process for improving the surface roughness of a wafer
FR2852143B1 (en) * 2003-03-04 2005-10-14 Soitec Silicon On Insulator PROCESS FOR THE PREVENTIVE TREATMENT OF THE CROWN OF A MULTILAYER SLICE
JP2007500435A (en) * 2003-07-29 2007-01-11 エス．オー．アイ．テック、シリコン、オン、インシュレター、テクノロジーズ A method for obtaining thin layers with improved properties by co-implantation and thermal annealing.
JP4552856B2 (en) * 2003-09-05 2010-09-29 株式会社Ｓｕｍｃｏ Manufacturing method of SOI wafer
WO2005024918A1 (en) * 2003-09-08 2005-03-17 Sumco Corporation Soi wafer and its manufacturing method
FR2863771B1 (en) * 2003-12-10 2007-03-02 Soitec Silicon On Insulator PROCESS FOR PROCESSING A MULTILAYER WAFER HAVING A DIFFERENTIAL OF THERMAL CHARACTERISTICS
JP4285244B2 (en) * 2004-01-08 2009-06-24 株式会社Ｓｕｍｃｏ Manufacturing method of SOI wafer
FR2867607B1 (en) * 2004-03-10 2006-07-14 Soitec Silicon On Insulator METHOD FOR MANUFACTURING SUBSTRATE FOR MICROELECTRONICS, OPTO-ELECTRONICS AND OPTICS WITH LIMITATION OF SLIDING LINES AND CORRESPONDING SUBSTRATE
US8241996B2 (en) 2005-02-28 2012-08-14 Silicon Genesis Corporation Substrate stiffness method and resulting devices for layer transfer process
US7642205B2 (en) 2005-04-08 2010-01-05 Mattson Technology, Inc. Rapid thermal processing using energy transfer layers
FR2888663B1 (en) * 2005-07-13 2008-04-18 Soitec Silicon On Insulator METHOD OF REDUCING THE ROUGHNESS OF A THICK LAYER OF INSULATION
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US7166520B1 (en) * 2005-08-08 2007-01-23 Silicon Genesis Corporation Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process
US20070029043A1 (en) * 2005-08-08 2007-02-08 Silicon Genesis Corporation Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process
US7427554B2 (en) * 2005-08-12 2008-09-23 Silicon Genesis Corporation Manufacturing strained silicon substrates using a backing material
WO2007080013A1 (en) * 2006-01-09 2007-07-19 International Business Machines Corporation Method and apparatus for treating bonded wafer semiconductor substrates
CN100490860C (en) * 2006-01-25 2009-05-27 余内逊 Preparation method of liver-benefiting face-beautifying oral liquid with micron pine pollen and pearl powder for women
US7863157B2 (en) 2006-03-17 2011-01-04 Silicon Genesis Corporation Method and structure for fabricating solar cells using a layer transfer process
US7598153B2 (en) * 2006-03-31 2009-10-06 Silicon Genesis Corporation Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species
WO2007118121A2 (en) 2006-04-05 2007-10-18 Silicon Genesis Corporation Method and structure for fabricating solar cells using a layer transfer process
FR2903809B1 (en) * 2006-07-13 2008-10-17 Soitec Silicon On Insulator THERMAL TREATMENT OF INTERFACE STABILIZATION E COLLAGE.
US8153513B2 (en) 2006-07-25 2012-04-10 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process
WO2008082920A1 (en) * 2006-12-28 2008-07-10 Memc Electronic Materials, Inc. Methods for producing smooth wafers
JP5143477B2 (en) 2007-05-31 2013-02-13 信越化学工業株式会社 Manufacturing method of SOI wafer
JP5466410B2 (en) * 2008-02-14 2014-04-09 信越化学工業株式会社 SOI substrate surface treatment method
WO2010062852A1 (en) * 2008-11-26 2010-06-03 Memc Electronic Materials, Inc. Method for processing a silicon-on-insulator structure
FR2943458B1 (en) * 2009-03-18 2011-06-10 Soitec Silicon On Insulator METHOD FOR FINISHING A "SILICON ON INSULATION" TYPE SUBSTRATE
CN103835000A (en) * 2012-11-20 2014-06-04 上海华虹宏力半导体制造有限公司 Method for high temperature improvement of polysilicon surface roughness
CN103065956B (en) * 2012-12-27 2015-02-25 南京大学 Method and device for achieving smoothness of silicon surface structure
FR3046877B1 (en) * 2016-01-14 2018-01-19 Soitec METHOD FOR SMOOTHING THE SURFACE OF A STRUCTURE
CN109346562A (en) * 2018-08-30 2019-02-15 华灿光电（浙江）有限公司 A kind of preparation method and LED epitaxial slice of LED epitaxial slice
CN111270196B (en) * 2019-03-07 2022-03-04 苏州微创关节医疗科技有限公司 Method for preparing zirconium-niobium alloy surface ceramic oxide layer and application

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1242014B (en) * 1990-11-15 1994-02-02 Memc Electronic Materials PROCEDURE FOR THE TREATMENT OF SILICON SLICES TO OBTAIN IN IT CONTROLLED PRECIPITATION PROFILES FOR THE PRODUCTION OF ELECTRONIC COMPONENTS.
FR2681472B1 (en) 1991-09-18 1993-10-29 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL.
KR100200973B1 (en) * 1995-03-20 1999-06-15 후지이 아키히로 Inclined surface silicon wafer and its surface structure forming method
US5716720A (en) * 1995-03-21 1998-02-10 Howmet Corporation Thermal barrier coating system with intermediate phase bondcoat
US5738909A (en) * 1996-01-10 1998-04-14 Micron Technology, Inc. Method of forming high-integrity ultrathin oxides
KR20010013993A (en) * 1997-06-19 2001-02-26 야마모토 카즈모토 Soi substrate and process for preparing the same, and semiconductor device and process for preparing the same
CA2278578A1 (en) * 1997-11-28 1999-06-10 Tsuneo Mitsuyu Method and device for activating semiconductor impurities
FR2777115B1 (en) * 1998-04-07 2001-07-13 Commissariat Energie Atomique PROCESS FOR TREATING SEMICONDUCTOR SUBSTRATES AND STRUCTURES OBTAINED BY THIS PROCESS
JP2000124092A (en) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd Manufacture of soi wafer by hydrogen-ion implantation stripping method and soi wafer manufactured thereby
EP1061565A1 (en) * 1998-12-28 2000-12-20 Shin-Etsu Handotai Co., Ltd Method for thermally annealing silicon wafer and silicon wafer
JP3911901B2 (en) * 1999-04-09 2007-05-09 信越半導体株式会社 SOI wafer and method for manufacturing SOI wafer
US6171965B1 (en) 1999-04-21 2001-01-09 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
US6589609B1 (en) * 1999-07-15 2003-07-08 Seagate Technology Llc Crystal zone texture of glass-ceramic substrates for magnetic recording disks
FR2797713B1 (en) * 1999-08-20 2002-08-02 Soitec Silicon On Insulator PROCESS FOR PROCESSING SUBSTRATES FOR MICROELECTRONICS AND SUBSTRATES OBTAINED BY THIS PROCESS
JP2001144275A (en) * 1999-08-27 2001-05-25 Shin Etsu Handotai Co Ltd Method for producing bonding soi wafer and bonding soi wafer
EP1158581B1 (en) * 1999-10-14 2016-04-27 Shin-Etsu Handotai Co., Ltd. Method for producing soi wafer
KR100549257B1 (en) * 1999-12-08 2006-02-03 주식회사 실트론 Method of surface smoothing for soi wafer
JP2002164520A (en) * 2000-11-27 2002-06-07 Shin Etsu Handotai Co Ltd Method for manufacturing semiconductor wafer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
AIR LIQUIDE: "Bulk Liquid Pure Argon", Retrieved from the Internet <URL:http://www.uk.airliquide.com/en/products-and-services/bulk-gases/bulk-liquid-pure-argon.html> *
CFC STARTEC LLC: "Argon", Retrieved from the Internet <URL:http://www.c-f-c.com/specgas_products/argon.htm> *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9986892B2 (en) 2010-09-20 2018-06-05 Endochoice, Inc. Operational interface in a multi-viewing element endoscope

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