EP1399957A2 - Substrat micro-electronique comportant un materiau conducteur a ouvertures avec coins emousses, et procedes correspondants permettant d'enlever le materiau conducteur - Google Patents

Substrat micro-electronique comportant un materiau conducteur a ouvertures avec coins emousses, et procedes correspondants permettant d'enlever le materiau conducteur

Info

Publication number
EP1399957A2
EP1399957A2 EP02746596A EP02746596A EP1399957A2 EP 1399957 A2 EP1399957 A2 EP 1399957A2 EP 02746596 A EP02746596 A EP 02746596A EP 02746596 A EP02746596 A EP 02746596A EP 1399957 A2 EP1399957 A2 EP 1399957A2
Authority
EP
European Patent Office
Prior art keywords
conductive material
comer
substiate
electiodes
disposing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02746596A
Other languages
German (de)
English (en)
Inventor
Whonchee Lee
Scott G. Meikle
Scott E. Moore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/888,084 external-priority patent/US7112121B2/en
Priority claimed from US09/888,002 external-priority patent/US7160176B2/en
Priority claimed from US09/887,767 external-priority patent/US7094131B2/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of EP1399957A2 publication Critical patent/EP1399957A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/046—Lapping machines or devices; Accessories designed for working plane surfaces using electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/16—Polishing
    • C25F3/30—Polishing of semiconducting materials
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F5/00—Electrolytic stripping of metallic layers or coatings
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F7/00—Constructional parts, or assemblies thereof, of cells for electrolytic removal of material from objects; Servicing or operating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H01L21/32125—Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Electrochemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mechanical Engineering (AREA)
  • Weting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

L'invention concerne un substrat micro-électronique et un procédé permettant d'enlever un matériau conducteur d'un substrat micro-électronique. Dans un mode de réalisation, le substrat micro-électronique comprend un matériau conducteur ou semi-conducteur qui comporte un évidement possédant un coin initialement aigu à la surface du matériau conducteur. On peut émousser ou arrondir ledit coin, par exemple en appliquant une tension sur une électrode en communication fluidique avec un fluide électrolytique adjacent au coin. Le courant électrique circulant de l'électrode à travers ledit coin peut oxyder le matériau conducteur au niveau du coin, et on peut enlever le matériau oxydé par un processus d'attaque chimique.
EP02746596A 2001-06-21 2002-06-20 Substrat micro-electronique comportant un materiau conducteur a ouvertures avec coins emousses, et procedes correspondants permettant d'enlever le materiau conducteur Withdrawn EP1399957A2 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US888002 1997-07-03
US888084 2001-06-21
US09/888,084 US7112121B2 (en) 2000-08-30 2001-06-21 Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate
US09/888,002 US7160176B2 (en) 2000-08-30 2001-06-21 Methods and apparatus for electrically and/or chemically-mechanically removing conductive material from a microelectronic substrate
US887767 2001-06-21
US09/887,767 US7094131B2 (en) 2000-08-30 2001-06-21 Microelectronic substrate having conductive material with blunt cornered apertures, and associated methods for removing conductive material
PCT/US2002/019496 WO2003001582A2 (fr) 2001-06-21 2002-06-20 Substrat micro-electronique comportant un materiau conducteur a ouvertures avec coins emousses, et procedes correspondants permettant d'enlever le materiau conducteur

Publications (1)

Publication Number Publication Date
EP1399957A2 true EP1399957A2 (fr) 2004-03-24

Family

ID=27420529

Family Applications (2)

Application Number Title Priority Date Filing Date
EP02746596A Withdrawn EP1399957A2 (fr) 2001-06-21 2002-06-20 Substrat micro-electronique comportant un materiau conducteur a ouvertures avec coins emousses, et procedes correspondants permettant d'enlever le materiau conducteur
EP02744464A Withdrawn EP1399956A2 (fr) 2001-06-21 2002-06-20 Procedes et dispositif pour le retrait d'un materiau conducteur d'un substrat micro-electronique par voie electrique, mecanique ou chimique

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP02744464A Withdrawn EP1399956A2 (fr) 2001-06-21 2002-06-20 Procedes et dispositif pour le retrait d'un materiau conducteur d'un substrat micro-electronique par voie electrique, mecanique ou chimique

Country Status (6)

Country Link
EP (2) EP1399957A2 (fr)
JP (2) JP2004531899A (fr)
KR (2) KR100663662B1 (fr)
CN (1) CN100356523C (fr)
AU (1) AU2002316303A1 (fr)
WO (2) WO2003001581A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6848970B2 (en) 2002-09-16 2005-02-01 Applied Materials, Inc. Process control in electrochemically assisted planarization
US6837983B2 (en) * 2002-01-22 2005-01-04 Applied Materials, Inc. Endpoint detection for electro chemical mechanical polishing and electropolishing processes
US7842169B2 (en) 2003-03-04 2010-11-30 Applied Materials, Inc. Method and apparatus for local polishing control
US7998335B2 (en) 2005-06-13 2011-08-16 Cabot Microelectronics Corporation Controlled electrochemical polishing method

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01241129A (ja) * 1988-03-23 1989-09-26 Toshiba Corp 半導体装置の製造方法
KR960006714B1 (ko) * 1990-05-28 1996-05-22 가부시끼가이샤 도시바 반도체 장치의 제조 방법
JPH10189909A (ja) * 1996-12-27 1998-07-21 Texas Instr Japan Ltd 誘電体キャパシタ及び誘電体メモリ装置と、これらの製造方法
US5911619A (en) * 1997-03-26 1999-06-15 International Business Machines Corporation Apparatus for electrochemical mechanical planarization
US6171467B1 (en) * 1997-11-25 2001-01-09 The John Hopkins University Electrochemical-control of abrasive polishing and machining rates
KR100280107B1 (ko) * 1998-05-07 2001-03-02 윤종용 트렌치 격리 형성 방법
US6121152A (en) * 1998-06-11 2000-09-19 Integrated Process Equipment Corporation Method and apparatus for planarization of metallized semiconductor wafers using a bipolar electrode assembly
US6143155A (en) * 1998-06-11 2000-11-07 Speedfam Ipec Corp. Method for simultaneous non-contact electrochemical plating and planarizing of semiconductor wafers using a bipiolar electrode assembly
JP4513145B2 (ja) * 1999-09-07 2010-07-28 ソニー株式会社 半導体装置の製造方法および研磨方法
US6797623B2 (en) * 2000-03-09 2004-09-28 Sony Corporation Methods of producing and polishing semiconductor device and polishing apparatus
US6867448B1 (en) * 2000-08-31 2005-03-15 Micron Technology, Inc. Electro-mechanically polished structure
JP2002093761A (ja) * 2000-09-19 2002-03-29 Sony Corp 研磨方法、研磨装置、メッキ方法およびメッキ装置
US6736952B2 (en) * 2001-02-12 2004-05-18 Speedfam-Ipec Corporation Method and apparatus for electrochemical planarization of a workpiece

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03001582A2 *

Also Published As

Publication number Publication date
WO2003001581A2 (fr) 2003-01-03
WO2003001582A2 (fr) 2003-01-03
WO2003001581A3 (fr) 2003-10-30
WO2003001582A3 (fr) 2003-10-30
KR20040010773A (ko) 2004-01-31
KR100598477B1 (ko) 2006-07-11
CN1516894A (zh) 2004-07-28
KR20040021616A (ko) 2004-03-10
JP2004531649A (ja) 2004-10-14
KR100663662B1 (ko) 2007-01-03
EP1399956A2 (fr) 2004-03-24
CN100356523C (zh) 2007-12-19
JP2004531899A (ja) 2004-10-14
AU2002316303A1 (en) 2003-01-08
JP4446271B2 (ja) 2010-04-07

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Legal Events

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Effective date: 20040112

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AX Request for extension of the european patent

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RIN1 Information on inventor provided before grant (corrected)

Inventor name: MOORE, SCOTT, E.

Inventor name: MEIKLE, SCOTT, G.

Inventor name: LEE, WHONCHEE

STAA Information on the status of an ep patent application or granted ep patent

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Effective date: 20100518