Classifications

• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07F—COIN-FREED OR LIKE APPARATUS
  • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
  • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
  • G07F7/12—Card verification
  • G07F7/127—Card verification in which both online and offline card verification can take place
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
  • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
  • G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
  • G06Q20/00—Payment architectures, schemes or protocols
  • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
  • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
  • G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
  • G06Q20/00—Payment architectures, schemes or protocols
  • G06Q20/38—Payment protocols; Details thereof
  • G06Q20/40—Authorisation, e.g. identification of payer or payee, verification of customer or shop credentials; Review and approval of payers, e.g. check credit lines or negative lists
  • G06Q20/409—Device specific authentication in transaction processing
  • G06Q20/4097—Device specific authentication in transaction processing using mutual authentication between devices and transaction partners
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07F—COIN-FREED OR LIKE APPARATUS
  • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
  • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07F—COIN-FREED OR LIKE APPARATUS
  • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
  • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
  • G07F7/0806—Details of the card
  • G07F7/0813—Specific details related to card security
  • G07F7/082—Features insuring the integrity of the data on or in the card
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07F—COIN-FREED OR LIKE APPARATUS
  • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
  • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
  • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
  • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07F—COIN-FREED OR LIKE APPARATUS
  • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
  • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
  • G07F7/12—Card verification
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/57—Protection from inspection, reverse engineering or tampering
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
  • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
  • H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
  • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
  • H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
  • H01L2223/544—Marks applied to semiconductor devices or parts
  • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
  • H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
  • H01L2223/544—Marks applied to semiconductor devices or parts
  • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to the authentication of an integrated circuit or of an electronic element or sub-assembly containing such a circuit by means of an authentication procedure using a secret datum contained in the integrated circuit.
• the invention relates more particularly to authentication procedures based on the use of a private data or key (also called secret) by means of an external device.
• An example of application of the present invention is the field of smart cards whether or not with prepaid account units.
• the various authentication methods of a smart card or the like are intended to prevent piracy or falsification of a card either by using a discrete device reproducing the card, or by pirating a reading terminal. or by large-scale reproduction of falsified smart cards.
• the private data itself is not sent, but a calculation result taking this private data into account, a number depending on a random number chosen by the integrated circuit and communicated to the external device, and a random number chosen by the external device and communicated to the card.
• the result is then verified by the external device to authenticate the card.
• the present invention aims to improve the procedures and systems for authenticating integrated circuits using private data originating from the integrated circuit.
• the invention aims, more particularly, to optimize the anti-fraud security of electronic devices using an integrated circuit provided with private data by preventing the extraction of this private data by various attacks of the integrated circuit.
• the present invention provides a method of extracting private data in an integrated circuit participating in an authentication procedure by means of an external device taking this private data into account, the private data being generated on demanded and made ephemeral.
• a lifetime of this private data is initialized and this data is erased from at least one first storage element containing it, at the end of this lifespan.
• the generation of the private data and the initialization of its lifetime are triggered by the same signal.
• the lifetime of the private data is reduced as it is generated.
• the lifetime is variable.
• the private data is obtained at least partially from a network of physical parameters.
• the network of physical parameters is programmable.
• the network of physical parameters is programmed, at least partially, by a word supplied by a storage element.
• the network of physical parameters is programmed, at least partially, by noise.
• the network of physical parameters is also controlled outside the periods of generation of the private data.
• the private data is obtained at least from a first data stored in the integrated circuit and from a second data generated on request by the network of physical parameters.
• the second datum is made ephemeral.
• the numbers of bits of the first and second data are close to each other, preferably equal.
• the present invention also provides an integrated circuit, comprising means for implementing the method.
• the circuit includes a reset circuit of at least one storage element.
• the reset circuit consists of one or more delay elements initialized by a command to generate the private data.
• FIG. 1 illustrates, in the form of a flowchart, a method of authenticating an integrated circuit using private data to which the present invention applies
• FIG. 2 represents, in the form of a block diagram and very schematically, a circuit for extracting private data according to an embodiment of the present invention
• FIG. 3 represents an embodiment of a network of physical parameters of an extraction circuit according to the present invention
• FIGS. 4A and 4B illustrate, in the form of timing diagrams, the operation of the network of FIG. 3
• Figures 5, 6 and 7 show three embodiments of a reset circuit of an extraction circuit according to the present invention.
• a characteristic of the present invention is not to permanently store the private or secret data in binary form in the integrated circuit but to generate this private data on request, that is to say during a procedure of 'authentication.
• the invention further provides that this private data is ephemeral, that is to say that it is no longer detectable in the integrated circuit after a predetermined time following its generation.
• FIG. 1 represents, in the form of a simplified flowchart, an embodiment of a procedure authentication of the type to which the present invention applies. This example relates to the authentication of a smart card by an external device. In FIG. 1, the steps of the authentication procedure taking place on the card C side or on the reader R side have been highlighted.
• An authentication phase naturally follows the introduction of a card into the reader, the sending of an identifier by the card to the reader or to a central, its verification by the central, then the extraction by the central of 'a data or public key v from the identifier communicated by the card.
• This public key most often comes from a key table.
• a number r (block 10). This number r is stored (block 11, MEM (r)) in the integrated circuit of the card. Then, we apply (block 12) to this number r a first algorithm ALG01 providing a result X. The result X is transmitted to the reader R which stores it (block 13, MEM (X)). On the reader side, we draw a random number e (block 14) which we memorize (block 15, MEM (e)). This number e is sent to the card C which itself stores it (block 16, MEM (e)).
• the card then extracts its private data s (block 17) according to the method of the present invention.
• This private data is taken into account in a second algorithm ALG02 (block 18) with the data r and e to provide a result Y.
• the number r is erased after having been used for the calculation of the number Y and before 1 sending of the latter.
• the result Y is sent to the reader R which verifies (block 19) by means of a third algorithm ALG03 that the quantity X is indeed equal to the application of this algorithm to the quantities Y, e and v.
• the public key v is of course a function of the data or private key s of the card.
• the reader supplies an authentication (T) or absence of authentication (F) indicator to the card (block 20).
• T authentication
• F absence of authentication
• the authentication procedure is then completed.
• An authentication method as described in FIG. 1 is known.
• the invention intervenes only to provide the private data s in a characteristic manner.
• the sizes of different data are generally important to improve security against hacking.
• the different data taken into account can have the following sizes: n, g and X each represent approximately 1000 bits; r, s and Y each represent about 220 bits; and e represents about 30 bits.
• the public key v can be calculated by the reader or the central office from the identifier of the card and from data sent by the latter.
• FIG. 2 represents an embodiment of a cell 1 for extracting private data in an integrated circuit according to the present invention.
• Cell 1 comprises a network of physical parameters (PPN) linked to the manufacture of the integrated circuit chip.
• PPN physical parameters
• This network of physical parameters 2 provides a large number of signals and participates in the generation of the private data s according to the invention.
• a preferred embodiment of a network of physical parameters will be illustrated below in relation to FIG. 3.
• a network classic of physical parameters consisting, for example in measuring electrical parameters. It may, for example, be a measurement of a threshold voltage of a transistor, a measurement of a resistance or a measurement of stray capacitance, a measurement of current produced by a source of current, a time constant measurement (for example, an RC circuit), a measurement of an oscillation frequency, etc.
• a network classic of physical parameters consisting, for example in measuring electrical parameters. It may, for example, be a measurement of a threshold voltage of a transistor, a measurement of a resistance or a measurement of stray capacitance, a measurement of current produced by a source of current, a time constant measurement (for example, an RC circuit), a measurement of an oscillation frequency, etc.
• the electrical parameter or parameters taken into account are specific to a manufacturing and constitute a signature of the integrated circuits resulting from this manufacturing.
• these signals are converted into digital signals by means of an analog-to-digital converter 24 (ADC) and, where appropriate, multiplexed by a multiplexer 4 (MUX) to constitute a binary word SP2, stored in a register 25.
• ADC analog-to-digital converter 24
• MUX multiplexer 4
• the word SP2 is therefore sensitive to technological and manufacturing process dispersions.
• the converter 24 and the multiplexer 4 have been shown in dotted lines because they are optional elements.
• the converter 24 can be omitted in the preferred embodiment of the network of physical parameters described later with reference to FIG. 3.
• the electrical parameters measured by means of the network 2 are not always the same.
• Network 2 is then programmable. It is parameterized or configured at each measurement from a binary word MP, stored in a register 26.
• the word MP is specific to the integrated circuit chip and can be individualized from one card to another.
• the measurement of physical parameters is triggered by a MES signal from a control unit 7 of cell 1.
• Cell 1 preferably receives a single control signal St, triggering an extraction of the parameter s delivered on a single output terminal of cell 1.
• the word SP2 is supplied to a combiner 8 also receiving a binary word SP1 stored in a register 9.
• the role of the circuit 8 is to combine the words SP1 and SP2 to provide the private data s stored in a register 10.
• the number s is then a k bit word obtained from the words SP1 and SP2 respectively on kl and k2 bits.
• the numbers k1 and k2 of bits of the words SP1 and SP2 are equal. This keeps equality of difficulty to a possible pirate in case a part (SP1 or SP2) of the word s comes to be discovered.
• the SP1 number differs from one card to another.
• the combiner 8 guarantees the size of the data s and a non-zero value.
• the use of a data SP1 specific to the card guarantees that the private key is unique whatever the data MP supplied to the network of physical parameters to configure it. According to a simplified embodiment, for example for a circuit of reduced size, it will be possible to seek, for a given size of private key, to limit the size of the network of physical parameters by increasing the size of the data item SP1.
• cell 1 also includes a circuit 22 for resetting (resetting to one or one) of some of its registers.
• the role of circuit 22 is in particular to make the presence of private data s in the register temporary.
• the circuit 22 commands the reinitialization not only of the register 21 but also of the register 25 containing the data. SP2 extracted from the network 2. In other words, the lifetime of the private data and / or of its constituents is fixed from its generation.
• An advantage of the present invention is that by combining the use of a network of physical parameters for condition at least part of the private data and a timed reset of the storage elements (for example, registers) storing this private data, a possible hacker is prevented from discovering the private data of the card by a visual examination, for example .
• the combinations of the MP and SPl parameters conditioning the obtaining of the private data increase the difficulty of hacking.
• the use of a combination of the words SP1 and SP2 is optional.
• the data MP and SP1 are merged. In this case, only one register 9 or 26 is used.
• the circuit 22 is for example controlled by a clock CLK triggered by the control unit 7 on arrival of a signal St for triggering the extraction of the parameter s.
• this code can be stored directly or modified in the register 9 to constitute the code SP1.
• circuit 22 can also reset register 9 to prevent the permanent presence of the SP1 code on the card. This function is illustrated by a dotted line in Figure 2.
• a noise source (dotted lines 23). This involves providing the physical parameters network with random orders outside of periods authentication. This then makes pirating more difficult by observing the consumption of the circuit. By operating network 2 continuously, it will be more difficult for a hacker to identify when it is used to generate a key.
• a hacker may consider network 2 as a simple source of analog noise used to interfere with consumption, which is known per se, and consequently eliminate the contribution to consumption in its attack, including when the network is used to generate a key.
• the measurement signal then commands a multiplexer responsible for selecting or combining the configuration signals represented by the word MP and the bits M23 arriving on the link 23.
• the signal MES is, for example, a trigger bit of a multiplexer 2 '' MP and M23 signals.
• the noise source 23 can replace all or part of the word MP in the configuration or programming of the network 2.
• the word MP is permanently supplied to the network 2 which then spends its time generating the data SP2.
• the private key s remains however ephemeral when combined with the data SP1. There is then even more chance that the hacker filters the response in consumption of network 2 during an attack consisting in examining the consumption of the circuit.
• a network of physical parameters consisting in measuring electrical parameters present in the network in the form of resistances, stray capacitances or the like is not the subject of the present invention.
• Such an embodiment is perfectly conventional. It could be, for example, a network of resistors and / or switchable capacitors associated in parallel and / or in series, the switches being controlled as a function of the configuration signals MP and possibly M23 arriving on the network 2.
• FIG. 3 represents the electrical diagram of a preferred embodiment of a network of physical parameters according to the present invention.
• circuit 2 comprises a single input terminal 42 intended to receive a digital signal E for triggering a generation.
• the signal E must include, as will be seen below in relation to FIGS. 4A and 4B, at least one edge per identification. It could be directly the signal St.
• Circuit 2 directly delivers a binary code B ⁇ , B2, ..., Bi- ⁇ # Bi, ..., Bn-i, Bn on a predetermined number of bits, this code being sensitive to technological and process dispersions. circuit manufacturing.
• Each bit B ⁇ is delivered on a terminal 3 ⁇ , 32, • -., 3 ⁇ - ⁇ , 3 ⁇ ⁇ • • -,, 3 nl » 3 n ⁇ u circuit 2 which is specific to it. Circuit 2 therefore delivers the identification code in parallel form.
• Each bit B ⁇ of the identification code is associated with an electrical path Pi, P2, ..., Pi, ..., P n connecting the common input terminal 42 to a terminal 3i of the same rank.
• the delays brought by the different electrical paths Pi are chosen to be slightly different from each other so as to guarantee sensitivity to the technological dispersions of the manufacturing process.
• an average electrical path 44 (CO) is provided for fixing the instant of reading from the appearance of the trigger edge of the input signal E
• the path 44 connects the entrance 42 of the circuit
• each electric path Pi includes a delay element 6 ⁇ (Cl), 62 (C2 ) ..., 6i (Ci) ..., 6 n (Cn) connecting input 42 of the circuit to input D of the corresponding flip-flop on the path.
• the delay elements 6i are the elements which, according to the present invention, have different delays with respect to each other.
• the flip-flops 5i preferably have the same constitution. However, they participate in the delay brought to the input signal to the respective output terminals of circuit 2 with respect to the average delay CO brought by the element 44.
• this edge arrives on the respective entries D of the rockers at different times.
• the reading of the input state of the different flip-flops is synchronized by the edge of the signal E delayed, this time by the element 44. It is in particular for this reason that a CO delay corresponding approximately to the average delay of the different elements 6i.
• the different outputs 3i of circuit 2 are connected individually at the input of a register for storing the binary code obtained, each bit Bi corresponding to one of the outputs of the circuit.
• this register is the register 25 in FIG. 2.
• FIGS. 4A and 4B illustrate, in the form of timing diagrams and without respect for scale, the operation of the network 2 of FIG. 3.
• FIGS. 4A and 4B represent examples of patterns of signal E, and of signals at the output of the different delay elements.
• the chronograms have been designated by the references CO, Cl, C2, C3 and C4.
• FIGS. 4A and 4B represents the difference between two circuits 1 integrated on chips from different manufacturers.
• FIG. 4B illustrates the same circuit resulting from a different manufacturing process therefore giving a different chip.
• the code obtained is different. For example, it is the code 0010.
• an instant t5 has been made arbitrarily identical to the case in FIG. 4A.
• the instants t'0, t'1, t'2, t'3 and t'4 at which the edge of the signal E has finished traversing the respective paths C0, Cl, C2, C3 and C4 are different from the case of Figure 4A.
• the retarding element C0 is itself sensitive to technological and manufacturing process dispersions. This does not, however, affect the implementation of the invention since this delay represents a average delay and where the code sought is arbitrary. Indeed, for the generation of a private key, what is important is that integrated circuits originating from the same manufacturing process provide the same code. As the retarding elements are sensitive to dispersions in the manufacturing process, this will be the case with the implementation of the preferred embodiment of the network 2 of physical parameters.
• An advantage of this embodiment is that the network 2 is particularly sensitive.
• the detectable difference of the delays brought by the different paths is of the order of a picosecond.
• the dispersions of the manufacturing or technological processes most often bring differences of the order of at least ten picoseconds.
• Another advantage is that in case of drift in time of one of the delays brought by the elements, this does not affect the results of the circuit. Indeed, all the delay elements preferably being of similar constitution, the dispersion will be in the same direction for all the elements (paths).
• any integrated elements sensitive to technological dispersions or influenced by the manufacturing process can be used. It could be, for example, series of resistors and / or capacitors.
• resistors it will be possible to use resistors in the thickness of the integrated circuit, but it will be preferable to use resistors in polycrystalline silicon whose value is linked to the geometry and which have the advantage of being less dependent on the temperature.
• the retarding elements may take other forms, provided that they are sensitive to technological dispersions and / or manufacturing processes.
• the choice of the range of variation of the delays brought by the different elements depends on the application and the desired sensitivity.
• An advantage of the network of physical parameters illustrated in FIG. 3 is that it avoids the use of an analog / digital converter 24 insofar as the binary word is directly delivered by the respective outputs of the flip-flops.
• Figures 5 to 7 show, schematically and partially, different embodiments of the reset circuit 22.
• the circuit 22 consists of several delay elements 71 ( ⁇ ), 72 ( ⁇ ') f 73 ( ⁇ ") to differentiate the instants of reinitialization of the registers 25, 9 and 21
• the element 71 brings the delay ⁇ for resetting the register 25.
• the element 72 and the element 71 with which it is in series bring the delay ⁇ + ⁇ ′ for resetting the register 9.
• the element 73 and the element 71 with which it is in series provide the delay ⁇ + ⁇ "for resetting the register 21.
• the signal applied to the delay element 71 constituting the first element of circuit 22 can be directly the signal bit St which can also constitute the MES bit for controlling the network of physical parameters.
• the signal MES is used to trigger a delay element 74 providing a delay minimal ⁇ m.
• FIG. 6 also illustrates a more detailed example of controlling the network of physical parameters. as in FIG. 2.
• a multiplexer 76 has been shown therein for combining the MP signals and the noise 23 or for selecting the MP signal or the noise 23.
• the reading of this multiplexer is controlled by the signal MES.
• the output of the multiplexer delivers a configuration word in register 77 (REG). This configuration word is used for the physical parameter network 2 "proper and, according to this embodiment, for configuring the variable delay ⁇ v.
• a fixed delay ⁇ is used, provided by an element 71.
• the delay ⁇ is triggered by setting network of physical parameters, that is to say by the multiplexer 76 or by the register 77 (not shown in FIG. 7), or by a signal produced by the network itself.
• the retarding element 71 can of course be associated with the elements 72 and 73 of FIG. 5.
• the various exemplary embodiments as well as others can be provided individually or in combination.
• the present invention is susceptible of various variants and modifications which will appear to those skilled in the art.
• the invention has been described in relation to a particular authentication method, it applies regardless of the authentication procedure envisaged, provided that it uses private data on the part of the circuit to be identified.
• storage registers which may be replaced by any suitable storage element, for example memories or parts of memory which may or may not be volatile depending on the type of data stored.
• the writing and reading of the data in these storage elements may be serial or parallel.
• provision may be made to reduce the time of presence of the private key as it is generated during the same authentication, for example during successive generations required by unsuccessful authentication. This further improves reliability by reducing the presence of the private key in the event that it is an attack aimed at detecting this key.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Security & Cryptography (AREA)
• Business, Economics & Management (AREA)
• Computer Hardware Design (AREA)
• Theoretical Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Accounting & Taxation (AREA)
• General Business, Economics & Management (AREA)
• Strategic Management (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Signal Processing (AREA)
• Power Engineering (AREA)
• Finance (AREA)
• Mathematical Physics (AREA)
• Software Systems (AREA)
• General Engineering & Computer Science (AREA)
• Storage Device Security (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=8861937

Family Applications (1)

Country Status (5)

Families Citing this family (15)

Family Cites Families (34)

• 2001
  • 2001-04-04 FR FR0104586A patent/FR2823398B1/fr not_active Expired - Lifetime
• 2002
  • 2002-04-04 WO PCT/FR2002/001190 patent/WO2002082389A2/fr active Application Filing
  • 2002-04-04 EP EP02730352A patent/EP1374191A2/fr not_active Withdrawn
  • 2002-04-04 US US10/473,903 patent/US7827413B2/en not_active Expired - Fee Related
  • 2002-04-04 JP JP2002580278A patent/JP2004534992A/ja active Pending

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events