EP1347383A1 - Data recorder and method for recording data in flash memory - Google Patents

Data recorder and method for recording data in flash memory Download PDF

Info

Publication number
EP1347383A1
EP1347383A1 EP01272924A EP01272924A EP1347383A1 EP 1347383 A1 EP1347383 A1 EP 1347383A1 EP 01272924 A EP01272924 A EP 01272924A EP 01272924 A EP01272924 A EP 01272924A EP 1347383 A1 EP1347383 A1 EP 1347383A1
Authority
EP
European Patent Office
Prior art keywords
management information
block
page
flash memory
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01272924A
Other languages
German (de)
French (fr)
Other versions
EP1347383A4 (en
Inventor
Kenichi c/o Sony Corporation Nakanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of EP1347383A1 publication Critical patent/EP1347383A1/en
Publication of EP1347383A4 publication Critical patent/EP1347383A4/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7207—Details relating to flash memory management management of metadata or control data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Definitions

  • the present invention relates to management information written in a flash memory, and in particular, to an apparatus for recording data and a method for writing data to a flash memory which protect the management information from a writing error raised when updating the management information.
  • a flash memory being a nonvolatile PROM (Programmable Read-Only Memory) to which data can be electrically written many times and data stored therein can be electrically deleted at a time has been used, since it is small and light, and enables high speed processing and low power consumption.
  • HDD Hard Disc Drive
  • PC Personal Computer
  • the memory card which is a removable flash memory.
  • the memory card is installed to a data recording apparatus for recording data, to which picture data and music data is recorded.
  • Picture data and music data recorded in the memory card can be reproduced by means of a PC, a digital camera, or a music playback apparatus, etc.
  • the flash memory is composed of a plurality of blocks, each having data of a predetermined amount and being a unit in deleting data. Also, each block is composed of a plurality of pages, each having data of a predetermined amount and being a unit in writing and reading out data. Each page has a data area of e.g. 512 Bytes to which data is to be written, and an extra area of e.g. 16 Bytes to which parity data, etc. is to be written.
  • the flash memory has important information such as information for initiating the data recording apparatus, information for managing the data recording apparatus, etc., which will be referred to as management information, stored in the data area thereof, besides picture data and music data recorded by the data recording apparatus.
  • the management information is read out and stored to a RAM (Random Access Memory) of the data recording apparatus, and is managed, when using the flash memory.
  • Stored management information is updated under the control of a CPU of the data recording apparatus, if necessary, in accordance with change of stored data when picture data and music data is written, and updated management information is rewritten to the data area of the flash memory.
  • step S21 a CPU retrieves a predetermined block of the flash memory to determine whether there is a vacant page in the block or not. Then, in case there is a vacant page, the process proceeds to step S22, while in case there is no vacant page, the process proceeds to step S23.
  • step S22 the CPU reserves the vacant page in the block, in which also management information just before updating is written, as a new page for writing the updated management information.
  • the page in which the management information just before updating is written is the last page of the block, the updated management information is written to the leading page of the next block.
  • step S23 since there is no vacant page in all blocks of the flash memory, the CPU deletes all the management information before updating written in the leading block so as to prepare a block for writing the updated management information. Then, the CPU reserves the leading page of the block whose management information before updating is deleted as a new page for writing the updated management information.
  • step S24 the CPU writes the updated management information to the new page reserved in step S22 or step S23.
  • step S24 ends the processing of updating the management information is terminated.
  • the management information in the block of the flash memory is updated as shown in FIG.3.
  • the CPU updates the management information again using the management information just before updating.
  • each of memory cells of a conventional flash memory can store information of only 1 bit, while, so as to cut costs and enlarge the capacity, there is also used a flash memory each of whose memory cells can store information of 2 bits and 4 bits. In this case, area of damaged data spreads over a wide range of bits, which cannot be coped with by error correction codes.
  • the present invention has an object to overcome the above-mentioned drawbacks of the prior art by providing an apparatus for recording data and a method for writing data to a flash memory which protect management information from a writing error raised when updating the management information.
  • the above object can be attained by providing an apparatus for recording data which writes data to a flash memory, the flash memory having data written therein in a unit of a page having data of a predetermined amount, which written data can be deleted at a time in a unit of a block composed of a plurality of pages, including:
  • management information just before updating which is necessary in updating management information can be surely protected.
  • the above object can be attained by providing a method for writing data to a flash memory, the flash memory having data written therein in a unit of a page having data of a predetermined amount, which written data can be deleted at a time in a unit of a block composed of a plurality of pages, including the steps of:
  • management information just before updating which is necessary in updating management information can be surely protected.
  • the present invention is applicable to a data recording apparatus 1 for recording data shown in FIG.5.
  • the data recording apparatus 1 includes a flash memory 2, an interface (IF) 3, a memory 4, a display 5, an I/O (Input/Output) 6, a CPU (Central Processing Unit) 7, and a bus 8.
  • IF interface
  • IF interface
  • I/O Input/Output
  • CPU Central Processing Unit
  • the flash memory 2 is a nonvolatile PROM (Programmable Read-Only Memory) to which data can be electrically written many times and data stored therein can be electrically deleted at a time.
  • the data recording apparatus 1 writes picture data and music data to the flash memory 2 in accordance with instructions of the user.
  • the flash memory 2 may be fixed to the data recording apparatus 1, or may be removable from the data recording apparatus 1.
  • the interface 3 connects the flash memory 2 to the bus 8, which reads out data stored in the flash memory 2 as well as writes data to the flash memory 2.
  • the memory 4 is a RAM (Random Access Memory) to/from which data can be written/read out, which is the main memory of the data recording apparatus 1.
  • the memory 4 stores management information read out from the flash memory 2 under the control of the CPU 7.
  • the display 5 displays programs used in writing data to the flash memory 2, free space of the flash memory 2, etc.
  • the I/O 6 is an input/output interface which receives instructions to the data recording apparatus 1 from the user, and outputs picture data and music data stored in the flash memory 2.
  • the CPU 7 controls respective units of the data recording apparatus 1 wholly. Also, the CPU 7 reads out the management information stored in the flash memory 2 to make the memory 4 store the read out management information thereto, and updates and manages the management information stored in the memory 4.
  • the CPU 7 controls the operation of writing picture data and music data to the flash memory 2 based on the management information stored in the memory 4.
  • the bus 8 connects above described respective units, which consists of a control bus for sending control signals from the CPU 7 to the respective units and a data bus for sending various data to the respective units.
  • step S1 when the operation of updating the management information is started, the CPU 7 retrieves the inside of the flash memory 2 to obtain a new page for writing updated management information.
  • step S2 the CPU 7 writes the updated management information to the new page of the flash memory 2 obtained in step S1.
  • step S3 the CPU 7 determines whether there is an error in the written management information or not. In case there is no error, the processing of updating the management information is terminated, while, in case there is an error, the process proceeds to step S4.
  • step S4 the CPU 7 retrieves the inside of the flash memory 2 to obtain a new block which is different from the block including the page in which the management information is written in step S2.
  • step S4 ends the process returns to step S1, and this processing is continued until the updated management information is written without an error.
  • the data recording apparatus 1 reserves a page of a new block which is different from the block including the page in which the management information just before updating is written. So, even though a writing error is raised when updating the management information, the management information just before updating can be surely protected.
  • step S1 and step S2 shown in the above described flow chart of FIG.6 will be explained with reference to a flow chart of FIG.7.
  • step S1 and step S2 Before explaining the operations of the step S1 and step S2 using a flow chart of FIG.7, the block configuration of the flash memory 2 will be explained with reference to FIG.8.
  • the flash memory 2 is composed of a plurality of blocks, each of whose block size is 16 KB (kilobytes).
  • a group of 512 blocks is defined as a segment, and logical addresses and preliminary blocks are managed every segment.
  • the flash memory 2 is composed of a segment number 0 and a segment number 1 in case the memory size thereof is 16 MB (megabytes), while being composed of from a segment number 0 to a segment number 3 in case the memory size thereof is 32 MB.
  • the flash memory 2 is composed of from a segment number 0 to a segment number 7 in case the memory size thereof is 64 MB, and is composed of from a segment number 0 to a segment number 15 in case the memory size thereof is 128 MB, as shown in FIG.8.
  • the range of physical block numbers corresponding to which the logical addresses are set up is determined.
  • a segment which is composed of from a physical block number 0 to a physical block number 511 (the number or sum of the blocks is 512) is defined as a segment number 0. It is determined in advance that logical addresses set up in the segment number 0 are from 0 to 493, as shown in parentheses, and the rest of the blocks are managed as the preliminary blocks.
  • the preliminary blocks be blocks for writing management information. This is because there is no access by real data to the preliminary blocks, and the preliminary blocks are not caused to correspond to logical addresses and physical block numbers. That is, the preliminary blocks can be managed independently as management data area, and corresponding operation can be performed easily even though complicated updating processing which spreads over even blocks and odd blocks is performed.
  • the management information there are conversion table data of logical/physical, directory entry of real data, etc.
  • serial numbers beginning from 0 are given to pages of the even block and the odd block.
  • the updated management information is stored in the flash memory 2 in order of the serial numbers. For example, serial numbers of 0, 2, 4, 6, are given to an even block 10a, while serial numbers of 1,3,5,7, ⁇ being given to an odd block 10b, as shown in FIG.9.
  • the updated management information is written to the pages of the blocks in order of the serial numbers of 0, 1, 2, 3, 4, 5, 6, 7
  • Each page of the even block 10a and the odd block 10b has a page number given thereto, respectively.
  • the page number for the serial number 0 and 1 is 1, while the page number for the serial number 2 and 3 being 2.
  • the page numbers are given to the respective pages of the even block 10a and the odd block 10b for the convenience of explanation.
  • the CPU 7 when writing the management information in actual processing, the CPU 7 does not designate the serial number directly, but instructs the flash memory 2 to write desired management information to the N-th page from a predetermined reference page of the blocks.
  • step S11 when the operation of updating management information is started, the CPU 7 retrieves a page of the flash memory 2 in which the management information just before updating is written. In case the management information just before updating is written in a page of the odd block 10b, the process proceeds to step S12. On the other hand, in case the management information just before updating is not written in a page of the odd block 10b, but written in a page of the even block 10a, the process proceeds to step S15.
  • the updated management information is written to a page whose serial number comes after that of a page in which the management information just before updating is written.
  • step S12 since the management information just before updating is written in a page of the odd block 10b, the updated management information is to be written to a page of the even block 10a.
  • the CPU 7 reserves a page of the even block 10a, whose page number is larger by one than that of the page of the odd block 10b in which the management information just before updating is written, as a page for writing the updated management information.
  • step S13 the CPU 7 determines whether there is a vacant page in the even block 10a or not. Then, in case there is no vacant page, the process proceeds to step S14, while in case there is a vacant page, the process proceeds to step S18.
  • the steps are for determining whether the page of the odd block 10b in which the management information just before updating is written is the last page of the odd block 10b or not. That is, in case the management information just before updating is written in the last page of the odd block 10b, the page of the even block 10a whose page number is larger by one than that of the last page of the odd block 10b cannot be found in step S12. Thus, the state in which there is no page for writing the updated management information is prevented from occurring by determining whether there is a vacant page in step S13.
  • step S14 since there is no vacant page in the even block 10a, the CPU 7 deletes old management information written in the even block 10a, and reserves the leading page thereof whose page number is 0 and serial number is 0 as a page for writing the updated management information.
  • step S14 ends, the process proceeds to step S18.
  • step S15 the CPU 7 determines whether the page in which the management information just before updating is the leading page of the even block 10a, that is, the page number is 0 and the serial number is 0, or not. In case the page in which the management information just before updating is written in the leading page of the even block 10a, the process proceeds to step S16, while in case not, the process proceeds to step S17.
  • step S16 since the management information just before updating is written in the leading page of the even block 10a whose page number is 0 and serial number is 0, the CPU 7 deletes all information written in the odd block 10b, and reserves the leading page thereof whose page number is 0 and serial number is 1 as a page for writing the updated management information.
  • step S17 since the management information just before updating is written in a page other than the leading page of the even block 10a whose page number is 0 and serial number is 0, the CPU 7 reserves a page of the odd block 10b, whose page number is equal to that of the page of the even block 10a in which the management information just before updating is written, as a page for writing the updated management information.
  • step S18 the CPU 7 controls the interface 3 so that the updated management information is written to the reserved page.
  • the data recording apparatus 1 secures a page of a block of the flash memory 2 for writing the updated management information, which block is different from a block including a page in which management information just before updating is written, the management information just before updating, which is necessary in case updating processing is unsuccessfully performed and a writing error is raised, can be surely protected.
  • the memory 4 and the CPU 7 of the data recording apparatus 1 updates and manages management information of the flash memory 2.
  • the management information may be updated and managed using a control IC which controls writing of data to a flash memory, in which case the flash memory and the control IC form a removable media.
  • a control IC which controls writing of data to a flash memory
  • the flash memory and the control IC form a removable media.
  • a memory card as such a removable media for updating and managing management information, which includes a flash memory and a control IC.
  • the memory card 20 includes a flash memory 30, a control IC 40.
  • the memory card 20 has a VCC 21 being a terminal for power supply, and a VSS 22 being a terminal for ground. Thus, when connected to a data recording apparatus, power is supplied to the memory card 20.
  • the configuration of the flash memory 30 is similar to that of the above-described flash memory 2. That is, the flash memory 30 is composed of a plurality of blocks, each having data of a predetermined amount and being a unit in deleting data. Also, each block is composed of a plurality of pages, each having data of a predetermined amount and being a unit in writing and reading out data. Each page has a data area of e.g. 512 Bytes to which data is to be written, and an extra area of e.g. 16 Bytes to which parity data, etc. is to be written.
  • the control IC 40 includes a register 41, a page buffer 42, an attribute ROM 43, a flash memory I/F 44, an OSC controller 45, and an IF 46.
  • the register 41 is a parameter register for storing parameters of data read out from the flash memory 30, such as the above-described serial numbers, to read out corresponding data from the flash memory 30 in accordance with commands, and for sending read out data to the page buffer 42.
  • the page buffer 42 temporarily stores data read out in accordance with the parameters stored in the register 41.
  • the register 41 works as the memory 4 of the above-described data recording apparatus 1.
  • the attribute ROM 43 is a read-only memory which stores memory information of the memory card 20.
  • the flash memory I/F 44 is an interface which connects the control IC 40 to the flash memory 30, and writes data to the flash memory 30 and reads out data from the flash memory 30 in accordance with commands sent from the register 41.
  • the OSC controller 45 generates clocks of the control IC 40 to control operation timing of the control IC 40.
  • the IF 46 is an interface which connects the control IC 40 to the data recording apparatus, and the control IC 40 receives control signals from the data recording apparatus, to which the memory card 20 is installed, and receives/sends data from/to the data recording apparatus via the IF 46.
  • the IF 46 includes a BS (bus state) 47, a DIO (DATE I/O) 48, and an SCLK (Serial Clock) 49.
  • BS bus state
  • DIO DATE I/O
  • SCLK Serial Clock
  • the BS 47 transmits control signals sent from the CPU 7 which controls input/output operation of data to/from the memory card 20.
  • the DIO 48 transmits data sent from the data recording apparatus to the flash memory 30 and data sent from the flash memory 30 to the data recording apparatus.
  • the SCLK 49 transmits clocks which control the control IC 40.
  • the memory card 20 can perform operations shown in the flow charts of FIG.6 and FIG.7 when updating management information.
  • a control unit controls a management information writing unit so that a block which is different from a block including a page in which management information just before updating is written is selected, and updated management information is written to a vacant page of thus selected block.
  • management information just before updating can be protected from damage of all management information in a block due to a writing error raised when updating management information. So, even though a writing error is raised, management information can be updated using protected management information just before updating.
  • a block which is different from a block including a page in which management information just before updating is written is selected, and updated management information is written to a vacant page of thus selected block.
  • management information just before updating can be protected from damage of all management information in a block due to a writing error raised when updating management information. So, even though a writing error is raised, management information can be updated using protected management information just before updating.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

The present invention provides an apparatus for recording data, including a storage unit (4) for reading out management information stored in the flash memory (2) to store read out management information, an updating unit (7) for updating management information stored in the storage unit (4), a management information writing unit (3) for writing management information updated by the updating unit (7) to the page being a unit in writing data to the flash memory (2), and a control unit (7) for controlling the management information writing unit (3) so that, when the management information writing unit (3) writes updated management information to a page of the flash memory (2), a block which is different from a block including a page in which management information just before updating is written is selected, and updated management information is written to a vacant page of thus selected block. <IMAGE>

Description

Technical Field
The present invention relates to management information written in a flash memory, and in particular, to an apparatus for recording data and a method for writing data to a flash memory which protect the management information from a writing error raised when updating the management information.
Background Art
As an auxiliary storage medium replacing an HDD (Hard Disc Drive) of a portable PC (Personal Computer), a flash memory being a nonvolatile PROM (Programmable Read-Only Memory) to which data can be electrically written many times and data stored therein can be electrically deleted at a time has been used, since it is small and light, and enables high speed processing and low power consumption.
There is also used a memory card which is a removable flash memory. The memory card is installed to a data recording apparatus for recording data, to which picture data and music data is recorded.
Picture data and music data recorded in the memory card can be reproduced by means of a PC, a digital camera, or a music playback apparatus, etc.
Next, the configuration of the flash memory will be explained with reference to FIG.1. The flash memory is composed of a plurality of blocks, each having data of a predetermined amount and being a unit in deleting data. Also, each block is composed of a plurality of pages, each having data of a predetermined amount and being a unit in writing and reading out data. Each page has a data area of e.g. 512 Bytes to which data is to be written, and an extra area of e.g. 16 Bytes to which parity data, etc. is to be written.
The flash memory has important information such as information for initiating the data recording apparatus, information for managing the data recording apparatus, etc., which will be referred to as management information, stored in the data area thereof, besides picture data and music data recorded by the data recording apparatus.
The management information is read out and stored to a RAM (Random Access Memory) of the data recording apparatus, and is managed, when using the flash memory. Stored management information is updated under the control of a CPU of the data recording apparatus, if necessary, in accordance with change of stored data when picture data and music data is written, and updated management information is rewritten to the data area of the flash memory.
Next, the operation of updating management information stored in a flash memory will be explained with reference to FIG.2. It is assumed that the management information is written in a predetermined block of a flash memory.
Firstly, in step S21, a CPU retrieves a predetermined block of the flash memory to determine whether there is a vacant page in the block or not. Then, in case there is a vacant page, the process proceeds to step S22, while in case there is no vacant page, the process proceeds to step S23.
In step S22, the CPU reserves the vacant page in the block, in which also management information just before updating is written, as a new page for writing the updated management information. In case the page in which the management information just before updating is written is the last page of the block, the updated management information is written to the leading page of the next block.
In step S23, since there is no vacant page in all blocks of the flash memory, the CPU deletes all the management information before updating written in the leading block so as to prepare a block for writing the updated management information. Then, the CPU reserves the leading page of the block whose management information before updating is deleted as a new page for writing the updated management information.
In step S24, the CPU writes the updated management information to the new page reserved in step S22 or step S23. When step S24 ends, the processing of updating the management information is terminated.
When updating the management information under the steps shown in the flow chart of FIG.2, the management information in the block of the flash memory is updated as shown in FIG.3.
When blocks to which the management information is written are 100a and 100b, firstly, the management information is written to the block 100a from a page number 0 to a page number n. Then, the management information is written to the block 100b from a page number 0. Thus, in the block of the flash memory, the management information is updated for each block sequentially.
When updating the management information of the flash memory, in case updating processing is unsuccessfully performed, the CPU updates the management information again using the management information just before updating.
In writing data to a page of the flash memory, when there is raised an error, the error affects all data in a block to which the page belongs.
That is, as shown in FIG.4, when there is raised an error in a bit of a page of a block, there are also raised errors in similar bits of all the other pages of the block, which damages all data in the block.
In updating the management information of the flash memory shown in the flow chart, since the management information is written to a vacant page which is next to a page of the block in which the management information before updating is written, when there is raised an error due to unsuccessful updating processing, all the management information in the block including the page with the error is damaged. Thus, the management information just before updating, which is necessary in case updating processing is unsuccessfully performed, is also damaged. So, the CPU cannot update the management information again since the management information just before updating cannot be used.
Furthermore, each of memory cells of a conventional flash memory can store information of only 1 bit, while, so as to cut costs and enlarge the capacity, there is also used a flash memory each of whose memory cells can store information of 2 bits and 4 bits. In this case, area of damaged data spreads over a wide range of bits, which cannot be coped with by error correction codes.
Disclosure of the Invention
Accordingly, the present invention has an object to overcome the above-mentioned drawbacks of the prior art by providing an apparatus for recording data and a method for writing data to a flash memory which protect management information from a writing error raised when updating the management information.
The above object can be attained by providing an apparatus for recording data which writes data to a flash memory, the flash memory having data written therein in a unit of a page having data of a predetermined amount, which written data can be deleted at a time in a unit of a block composed of a plurality of pages, including:
  • storage means for reading out management information stored in the flash memory to store read out management information;
  • updating means for updating management information stored in the storage means;
  • management information writing means for writing management information updated by the updating means to the page being a unit in writing data to the flash memory; and
  • control means for controlling the management information writing means so that, when the management information writing means writes updated management information to a page of the flash memory, a block which is different from a block including a page in which management information just before updating is written is selected, and updated management information is written to a vacant page of thus selected block.
    • According to the apparatus for recording data of the present invention, management information just before updating, which is necessary in updating management information can be surely protected.
    Also, the above object can be attained by providing a method for writing data to a flash memory, the flash memory having data written therein in a unit of a page having data of a predetermined amount, which written data can be deleted at a time in a unit of a block composed of a plurality of pages, including the steps of:
  • reading out management information stored in the flash memory;
  • having read out management information stored to a predetermined storage means;
  • updating management information stored in the storage means;
  • when writing updated management information to a page of the flash memory, selecting a block which is different from a block including a page in which management information just before updating is written; and
  • writing updated management information to a vacant page of thus selected block.
    • According to the method for writing data to a flash memory of the present invention, management information just before updating, which is necessary in updating management information can be surely protected.
    Brief Description of the Drawings
  • FIG.1 shows the configuration of a flash memory.
  • FIG.2 shows a flow chart of the conventional operation of updating management information stored in the flash memory of a data recording apparatus.
  • FIG.3 shows the configuration of a block of the flash memory of the data recording apparatus to which management information is to be written.
  • FIG.4 shows an error which affects all data in the block, which is raised in writing data to a page of the flash memory of the data recording apparatus.
  • FIG.5 shows a block diagram of a data recording apparatus according to the present invention.
  • FIG.6 shows a flow chart of the operation of updating management information stored in a flash memory of the data recording apparatus.
  • FIG.7 shows a flow chart of the specific operation of updating management information stored in a flash memory of the data recording apparatus.
  • FIG.8 shows the specific configuration of a block of the flash memory of the data recording apparatus.
  • FIG.9 shows the configuration of an even block and an odd block of the flash memory of the data recording apparatus to which management information is to be written.
  • FIG.10 shows a block diagram of a memory card according to the present invention.
    • Best Mode for Carrying Out the Invention
    The apparatus for recording data and the method for writing data to a flash memory of the present invention will further be described below concerning the best modes with reference to the accompanying drawings.
    The present invention is applicable to a data recording apparatus 1 for recording data shown in FIG.5.
    The data recording apparatus 1 includes a flash memory 2, an interface (IF) 3, a memory 4, a display 5, an I/O (Input/Output) 6, a CPU (Central Processing Unit) 7, and a bus 8.
    The flash memory 2 is a nonvolatile PROM (Programmable Read-Only Memory) to which data can be electrically written many times and data stored therein can be electrically deleted at a time. The data recording apparatus 1 writes picture data and music data to the flash memory 2 in accordance with instructions of the user.
    The flash memory 2 may be fixed to the data recording apparatus 1, or may be removable from the data recording apparatus 1.
    The interface 3 connects the flash memory 2 to the bus 8, which reads out data stored in the flash memory 2 as well as writes data to the flash memory 2.
    The memory 4 is a RAM (Random Access Memory) to/from which data can be written/read out, which is the main memory of the data recording apparatus 1. The memory 4 stores management information read out from the flash memory 2 under the control of the CPU 7.
    The display 5 displays programs used in writing data to the flash memory 2, free space of the flash memory 2, etc.
    The I/O 6 is an input/output interface which receives instructions to the data recording apparatus 1 from the user, and outputs picture data and music data stored in the flash memory 2.
    The CPU 7 controls respective units of the data recording apparatus 1 wholly. Also, the CPU 7 reads out the management information stored in the flash memory 2 to make the memory 4 store the read out management information thereto, and updates and manages the management information stored in the memory 4.
    Also, the CPU 7 controls the operation of writing picture data and music data to the flash memory 2 based on the management information stored in the memory 4.
    The bus 8 connects above described respective units, which consists of a control bus for sending control signals from the CPU 7 to the respective units and a data bus for sending various data to the respective units.
    Next, the operation of updating the management information stored in the flash memory 2 will be explained with reference to a flow chart of FIG.6.
    Firstly, in step S1, when the operation of updating the management information is started, the CPU 7 retrieves the inside of the flash memory 2 to obtain a new page for writing updated management information.
    In step S2, the CPU 7 writes the updated management information to the new page of the flash memory 2 obtained in step S1.
    In step S3, the CPU 7 determines whether there is an error in the written management information or not. In case there is no error, the processing of updating the management information is terminated, while, in case there is an error, the process proceeds to step S4.
    In step S4, the CPU 7 retrieves the inside of the flash memory 2 to obtain a new block which is different from the block including the page in which the management information is written in step S2. When step S4 ends, the process returns to step S1, and this processing is continued until the updated management information is written without an error.
    Thus, when writing the updated management information, the data recording apparatus 1 reserves a page of a new block which is different from the block including the page in which the management information just before updating is written. So, even though a writing error is raised when updating the management information, the management information just before updating can be surely protected.
    Next, specific operations of the step S1 and step S2 shown in the above described flow chart of FIG.6 will be explained with reference to a flow chart of FIG.7.
    Before explaining the operations of the step S1 and step S2 using a flow chart of FIG.7, the block configuration of the flash memory 2 will be explained with reference to FIG.8.
    The flash memory 2 is composed of a plurality of blocks, each of whose block size is 16 KB (kilobytes). A group of 512 blocks is defined as a segment, and logical addresses and preliminary blocks are managed every segment.
    That is, for example, the flash memory 2 is composed of a segment number 0 and a segment number 1 in case the memory size thereof is 16 MB (megabytes), while being composed of from a segment number 0 to a segment number 3 in case the memory size thereof is 32 MB. Similarly, the flash memory 2 is composed of from a segment number 0 to a segment number 7 in case the memory size thereof is 64 MB, and is composed of from a segment number 0 to a segment number 15 in case the memory size thereof is 128 MB, as shown in FIG.8.
    Also, by thus using the segment, the range of physical block numbers corresponding to which the logical addresses are set up is determined.
    For example, as shown in FIG.8, a segment which is composed of from a physical block number 0 to a physical block number 511 (the number or sum of the blocks is 512) is defined as a segment number 0. It is determined in advance that logical addresses set up in the segment number 0 are from 0 to 493, as shown in parentheses, and the rest of the blocks are managed as the preliminary blocks.
    Similarly, as for the respective segments defined as the segment number 0 to the segment number 15, logical addresses corresponding to physical block numbers are set up, and blocks which do not correspond to logical addresses are managed as the preliminary blocks.
    It is desired that the preliminary blocks be blocks for writing management information. This is because there is no access by real data to the preliminary blocks, and the preliminary blocks are not caused to correspond to logical addresses and physical block numbers. That is, the preliminary blocks can be managed independently as management data area, and corresponding operation can be performed easily even though complicated updating processing which spreads over even blocks and odd blocks is performed. As the management information, there are conversion table data of logical/physical, directory entry of real data, etc.
    In the following explanation, it is assumed that two blocks for writing the updated management information are prepared, which are referred to as an even block and an odd block, respectively.
    Also, serial numbers beginning from 0 are given to pages of the even block and the odd block. The updated management information is stored in the flash memory 2 in order of the serial numbers. For example, serial numbers of 0, 2, 4, 6, are given to an even block 10a, while serial numbers of 1,3,5,7,··· being given to an odd block 10b, as shown in FIG.9. The updated management information is written to the pages of the blocks in order of the serial numbers of 0, 1, 2, 3, 4, 5, 6, 7
    Each page of the even block 10a and the odd block 10b has a page number given thereto, respectively. As for correspondence between the page numbers and the serial numbers, the page number for the serial number 0 and 1 is 1, while the page number for the serial number 2 and 3 being 2.
    The page numbers are given to the respective pages of the even block 10a and the odd block 10b for the convenience of explanation. Thus, when writing the management information in actual processing, the CPU 7 does not designate the serial number directly, but instructs the flash memory 2 to write desired management information to the N-th page from a predetermined reference page of the blocks.
    Firstly, in step S11, when the operation of updating management information is started, the CPU 7 retrieves a page of the flash memory 2 in which the management information just before updating is written. In case the management information just before updating is written in a page of the odd block 10b, the process proceeds to step S12. On the other hand, in case the management information just before updating is not written in a page of the odd block 10b, but written in a page of the even block 10a, the process proceeds to step S15.
    The updated management information is written to a page whose serial number comes after that of a page in which the management information just before updating is written.
    In step S12, since the management information just before updating is written in a page of the odd block 10b, the updated management information is to be written to a page of the even block 10a. Thus, the CPU 7 reserves a page of the even block 10a, whose page number is larger by one than that of the page of the odd block 10b in which the management information just before updating is written, as a page for writing the updated management information.
    In step S13, the CPU 7 determines whether there is a vacant page in the even block 10a or not. Then, in case there is no vacant page, the process proceeds to step S14, while in case there is a vacant page, the process proceeds to step S18.
    This is, the steps are for determining whether the page of the odd block 10b in which the management information just before updating is written is the last page of the odd block 10b or not. That is, in case the management information just before updating is written in the last page of the odd block 10b, the page of the even block 10a whose page number is larger by one than that of the last page of the odd block 10b cannot be found in step S12. Thus, the state in which there is no page for writing the updated management information is prevented from occurring by determining whether there is a vacant page in step S13.
    In step S14, since there is no vacant page in the even block 10a, the CPU 7 deletes old management information written in the even block 10a, and reserves the leading page thereof whose page number is 0 and serial number is 0 as a page for writing the updated management information. When step S14 ends, the process proceeds to step S18.
    In step S15, the CPU 7 determines whether the page in which the management information just before updating is the leading page of the even block 10a, that is, the page number is 0 and the serial number is 0, or not. In case the page in which the management information just before updating is written in the leading page of the even block 10a, the process proceeds to step S16, while in case not, the process proceeds to step S17.
    In step S16, since the management information just before updating is written in the leading page of the even block 10a whose page number is 0 and serial number is 0, the CPU 7 deletes all information written in the odd block 10b, and reserves the leading page thereof whose page number is 0 and serial number is 1 as a page for writing the updated management information.
    In step S17, since the management information just before updating is written in a page other than the leading page of the even block 10a whose page number is 0 and serial number is 0, the CPU 7 reserves a page of the odd block 10b, whose page number is equal to that of the page of the even block 10a in which the management information just before updating is written, as a page for writing the updated management information.
    In step S18, the CPU 7 controls the interface 3 so that the updated management information is written to the reserved page.
    Thus, since the data recording apparatus 1 secures a page of a block of the flash memory 2 for writing the updated management information, which block is different from a block including a page in which management information just before updating is written, the management information just before updating, which is necessary in case updating processing is unsuccessfully performed and a writing error is raised, can be surely protected.
    As has been described above, the memory 4 and the CPU 7 of the data recording apparatus 1 updates and manages management information of the flash memory 2. On the other hand, according to the present invention, the management information may be updated and managed using a control IC which controls writing of data to a flash memory, in which case the flash memory and the control IC form a removable media. For example, there may be employed a memory card as such a removable media for updating and managing management information, which includes a flash memory and a control IC.
    Next, the configuration of a memory card 20 which includes a flash memory and a control IC will be explained with reference to FIG.10.
    The memory card 20 includes a flash memory 30, a control IC 40. The memory card 20 has a VCC 21 being a terminal for power supply, and a VSS 22 being a terminal for ground. Thus, when connected to a data recording apparatus, power is supplied to the memory card 20.
    The configuration of the flash memory 30 is similar to that of the above-described flash memory 2. That is, the flash memory 30 is composed of a plurality of blocks, each having data of a predetermined amount and being a unit in deleting data. Also, each block is composed of a plurality of pages, each having data of a predetermined amount and being a unit in writing and reading out data. Each page has a data area of e.g. 512 Bytes to which data is to be written, and an extra area of e.g. 16 Bytes to which parity data, etc. is to be written.
    The control IC 40 includes a register 41, a page buffer 42, an attribute ROM 43, a flash memory I/F 44, an OSC controller 45, and an IF 46.
    The register 41 is a parameter register for storing parameters of data read out from the flash memory 30, such as the above-described serial numbers, to read out corresponding data from the flash memory 30 in accordance with commands, and for sending read out data to the page buffer 42.
    The page buffer 42 temporarily stores data read out in accordance with the parameters stored in the register 41. The register 41 works as the memory 4 of the above-described data recording apparatus 1.
    The attribute ROM 43 is a read-only memory which stores memory information of the memory card 20.
    The flash memory I/F 44 is an interface which connects the control IC 40 to the flash memory 30, and writes data to the flash memory 30 and reads out data from the flash memory 30 in accordance with commands sent from the register 41.
    The OSC controller 45 generates clocks of the control IC 40 to control operation timing of the control IC 40.
    The IF 46 is an interface which connects the control IC 40 to the data recording apparatus, and the control IC 40 receives control signals from the data recording apparatus, to which the memory card 20 is installed, and receives/sends data from/to the data recording apparatus via the IF 46.
    The IF 46 includes a BS (bus state) 47, a DIO (DATE I/O) 48, and an SCLK (Serial Clock) 49.
    The BS 47 transmits control signals sent from the CPU 7 which controls input/output operation of data to/from the memory card 20.
    The DIO 48 transmits data sent from the data recording apparatus to the flash memory 30 and data sent from the flash memory 30 to the data recording apparatus.
    The SCLK 49 transmits clocks which control the control IC 40.
    Thus, including the flash memory 30 and the control IC 40, the memory card 20 can perform operations shown in the flow charts of FIG.6 and FIG.7 when updating management information.
    So, even though a writing error is raised at the flash memory 30 of the memory card 20 when updating management information, management information just before updating, which is necessary in updating the management information, can be surely protected.
    Industrial Applicability
    As in the above, according to the apparatus for recording data of the present invention, in updating management information stored in a flash memory, a control unit controls a management information writing unit so that a block which is different from a block including a page in which management information just before updating is written is selected, and updated management information is written to a vacant page of thus selected block. Thus, management information just before updating can be protected from damage of all management information in a block due to a writing error raised when updating management information. So, even though a writing error is raised, management information can be updated using protected management information just before updating.
    Furthermore, according to the method for writing data to a flash memory of the present invention, in updating management information stored in a flash memory, a block which is different from a block including a page in which management information just before updating is written is selected, and updated management information is written to a vacant page of thus selected block. Thus, management information just before updating can be protected from damage of all management information in a block due to a writing error raised when updating management information. So, even though a writing error is raised, management information can be updated using protected management information just before updating.

    Claims (4)

    1. An apparatus for recording data which writes data to a flash memory, the flash memory having data written therein in a unit of a page having data of a predetermined amount, which written data can be deleted at a time in a unit of a block composed of a plurality of pages, comprising:
      storage means for reading out management information stored in the flash memory to store read out management information;
      updating means for updating management information stored in the storage means;
      management information writing means for writing management information updated by the updating means to the page being a unit in writing data to the flash memory; and
      control means for controlling the management information writing means so that, when the management information writing means writes updated management information to a page of the flash memory, a block which is different from a block including a page in which management information just before updating is written is selected, and updated management information is written to a vacant page of thus selected block.
    2. The apparatus for recording data as set forth in Claim 1, wherein,
         the block being a unit in deleting data written in the flash memory is composed of an even block and an odd block, and
         the control means controls the management information writing means so that, when the management information writing means writes updated management information to a page of the flash memory, the odd block is selected and updated management information is written to a vacant page of thus selected odd block in case management information just before updating is written to the even block, while the even block is selected and updated management information is written to a vacant page of thus selected even block in case management information just before updating is written to the odd block.
    3. A method for writing data to a flash memory, the flash memory having data written therein in a unit of a page having data of a predetermined amount, which written data can be deleted at a time in a unit of a block composed of a plurality of pages, comprising the steps of:
      reading out management information stored in the flash memory;
      having read out management information stored to a predetermined storage means;
      updating management information stored in the storage means;
      when writing updated management information to a page of the flash memory, selecting a block which is different from a block including a page in which management information just before updating is written; and
      writing updated management information to a vacant page of thus selected block.
    4. The method for writing data to a flash memory as set forth in Claim 3, wherein,
         the block being a unit in deleting data written in the flash memory is composed of an even block and an odd block, and
         when writing updated management information to a page of the flash memory, selecting the odd block in case management information just before updating is written to the even block,
         writing updated management information to a vacant page of thus selected odd block,
         selecting the even block in case management information just before updating is written to the odd block,
         writing updated management information to a vacant page of thus selected even block.
    EP01272924A 2000-12-28 2001-12-28 DATA RECORDER AND METHOD FOR RECORDING DATA IN A FLASH MEMORY Withdrawn EP1347383A4 (en)

    Applications Claiming Priority (3)

    Application Number Priority Date Filing Date Title
    JP2000403461 2000-12-28
    JP2000403461 2000-12-28
    PCT/JP2001/011678 WO2002054247A1 (en) 2000-12-28 2001-12-28 Data recorder and method for recording data in flash memory

    Publications (2)

    Publication Number Publication Date
    EP1347383A1 true EP1347383A1 (en) 2003-09-24
    EP1347383A4 EP1347383A4 (en) 2007-06-27

    Family

    ID=18867581

    Family Applications (1)

    Application Number Title Priority Date Filing Date
    EP01272924A Withdrawn EP1347383A4 (en) 2000-12-28 2001-12-28 DATA RECORDER AND METHOD FOR RECORDING DATA IN A FLASH MEMORY

    Country Status (7)

    Country Link
    US (1) US7065608B2 (en)
    EP (1) EP1347383A4 (en)
    JP (1) JP4122972B2 (en)
    KR (1) KR100871027B1 (en)
    CN (1) CN1307554C (en)
    TW (1) TW539950B (en)
    WO (1) WO2002054247A1 (en)

    Families Citing this family (69)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    JP2004280752A (en) * 2003-03-19 2004-10-07 Sony Corp Data storage device, management information updating method in data storage device, and computer program
    JP4218406B2 (en) * 2003-04-25 2009-02-04 富士フイルム株式会社 Information recording and playback method
    KR100546348B1 (en) * 2003-07-23 2006-01-26 삼성전자주식회사 Flash memory system and its data storage method
    JP2005222201A (en) * 2004-02-04 2005-08-18 Matsushita Electric Ind Co Ltd Memory access device and semiconductor memory card
    JP4460967B2 (en) * 2004-07-23 2010-05-12 株式会社東芝 MEMORY CARD, NONVOLATILE SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR MEMORY CONTROL METHOD
    CN100481267C (en) * 2004-08-09 2009-04-22 凌阳科技股份有限公司 Method for using nonvolatile memory and electronic device thereof
    JP4843222B2 (en) * 2005-01-11 2011-12-21 株式会社東芝 Semiconductor memory device control method, memory card, and host device
    KR100703727B1 (en) * 2005-01-12 2007-04-05 삼성전자주식회사 Non-volatile memory, mapping control device and method therefor
    JP4182952B2 (en) 2005-02-22 2008-11-19 ブラザー工業株式会社 Paper conveying apparatus and image forming apparatus
    JP2007011872A (en) * 2005-07-01 2007-01-18 Toshiba Corp Memory card and its control method
    KR100746289B1 (en) 2005-07-11 2007-08-03 삼성전자주식회사 Nonvolatile memory card device and method for updating memory capacity information
    JP4356686B2 (en) 2005-12-01 2009-11-04 ソニー株式会社 Memory device and memory control method
    KR100825802B1 (en) * 2007-02-13 2008-04-29 삼성전자주식회사 A data writing method of a nonvolatile memory device which copies data having logical pages earlier than a logical page of write data from a data block.
    US8365040B2 (en) 2007-09-20 2013-01-29 Densbits Technologies Ltd. Systems and methods for handling immediate data errors in flash memory
    US8694715B2 (en) 2007-10-22 2014-04-08 Densbits Technologies Ltd. Methods for adaptively programming flash memory devices and flash memory systems incorporating same
    US8751726B2 (en) * 2007-12-05 2014-06-10 Densbits Technologies Ltd. System and methods employing mock thresholds to generate actual reading thresholds in flash memory devices
    US8359516B2 (en) 2007-12-12 2013-01-22 Densbits Technologies Ltd. Systems and methods for error correction and decoding on multi-level physical media
    WO2009098777A1 (en) * 2008-02-08 2009-08-13 Fujitsu Limited Backup method, storage method, and disc array device
    US8972472B2 (en) 2008-03-25 2015-03-03 Densbits Technologies Ltd. Apparatus and methods for hardware-efficient unbiased rounding
    TWI383399B (en) * 2009-03-03 2013-01-21 Wistron Corp Embedded electronic device and method for storing data
    US8819385B2 (en) 2009-04-06 2014-08-26 Densbits Technologies Ltd. Device and method for managing a flash memory
    US8458574B2 (en) * 2009-04-06 2013-06-04 Densbits Technologies Ltd. Compact chien-search based decoding apparatus and method
    US8566510B2 (en) * 2009-05-12 2013-10-22 Densbits Technologies Ltd. Systems and method for flash memory management
    US8995197B1 (en) 2009-08-26 2015-03-31 Densbits Technologies Ltd. System and methods for dynamic erase and program control for flash memory device memories
    US9330767B1 (en) 2009-08-26 2016-05-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Flash memory module and method for programming a page of flash memory cells
    US8730729B2 (en) 2009-10-15 2014-05-20 Densbits Technologies Ltd. Systems and methods for averaging error rates in non-volatile devices and storage systems
    US8724387B2 (en) 2009-10-22 2014-05-13 Densbits Technologies Ltd. Method, system, and computer readable medium for reading and programming flash memory cells using multiple bias voltages
    US9037777B2 (en) * 2009-12-22 2015-05-19 Densbits Technologies Ltd. Device, system, and method for reducing program/read disturb in flash arrays
    US8745317B2 (en) 2010-04-07 2014-06-03 Densbits Technologies Ltd. System and method for storing information in a multi-level cell memory
    US8621321B2 (en) 2010-07-01 2013-12-31 Densbits Technologies Ltd. System and method for multi-dimensional encoding and decoding
    US8964464B2 (en) 2010-08-24 2015-02-24 Densbits Technologies Ltd. System and method for accelerated sampling
    US9063878B2 (en) 2010-11-03 2015-06-23 Densbits Technologies Ltd. Method, system and computer readable medium for copy back
    US8850100B2 (en) 2010-12-07 2014-09-30 Densbits Technologies Ltd. Interleaving codeword portions between multiple planes and/or dies of a flash memory device
    US8990665B1 (en) 2011-04-06 2015-03-24 Densbits Technologies Ltd. System, method and computer program product for joint search of a read threshold and soft decoding
    US9372792B1 (en) 2011-05-12 2016-06-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Advanced management of a non-volatile memory
    US9110785B1 (en) 2011-05-12 2015-08-18 Densbits Technologies Ltd. Ordered merge of data sectors that belong to memory space portions
    US9396106B2 (en) 2011-05-12 2016-07-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Advanced management of a non-volatile memory
    US9195592B1 (en) 2011-05-12 2015-11-24 Densbits Technologies Ltd. Advanced management of a non-volatile memory
    US8996790B1 (en) 2011-05-12 2015-03-31 Densbits Technologies Ltd. System and method for flash memory management
    US9501392B1 (en) 2011-05-12 2016-11-22 Avago Technologies General Ip (Singapore) Pte. Ltd. Management of a non-volatile memory module
    US8423722B1 (en) * 2011-08-26 2013-04-16 Western Digital Technologies, Inc. System and method for high performance command processing in solid state drives
    US8947941B2 (en) 2012-02-09 2015-02-03 Densbits Technologies Ltd. State responsive operations relating to flash memory cells
    US8996788B2 (en) 2012-02-09 2015-03-31 Densbits Technologies Ltd. Configurable flash interface
    US8996793B1 (en) 2012-04-24 2015-03-31 Densbits Technologies Ltd. System, method and computer readable medium for generating soft information
    US8838937B1 (en) 2012-05-23 2014-09-16 Densbits Technologies Ltd. Methods, systems and computer readable medium for writing and reading data
    US8879325B1 (en) 2012-05-30 2014-11-04 Densbits Technologies Ltd. System, method and computer program product for processing read threshold information and for reading a flash memory module
    US9921954B1 (en) 2012-08-27 2018-03-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for split flash memory management between host and storage controller
    JP5360287B2 (en) * 2012-10-31 2013-12-04 富士通株式会社 Data control method and system
    US9368225B1 (en) 2012-11-21 2016-06-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Determining read thresholds based upon read error direction statistics
    US9069659B1 (en) 2013-01-03 2015-06-30 Densbits Technologies Ltd. Read threshold determination using reference read threshold
    US9136876B1 (en) 2013-06-13 2015-09-15 Densbits Technologies Ltd. Size limited multi-dimensional decoding
    US9413491B1 (en) 2013-10-08 2016-08-09 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for multiple dimension decoding and encoding a message
    US9786388B1 (en) 2013-10-09 2017-10-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Detecting and managing bad columns
    US9348694B1 (en) 2013-10-09 2016-05-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Detecting and managing bad columns
    US9397706B1 (en) 2013-10-09 2016-07-19 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for irregular multiple dimension decoding and encoding
    US9536612B1 (en) 2014-01-23 2017-01-03 Avago Technologies General Ip (Singapore) Pte. Ltd Digital signaling processing for three dimensional flash memory arrays
    US10120792B1 (en) 2014-01-29 2018-11-06 Avago Technologies General Ip (Singapore) Pte. Ltd. Programming an embedded flash storage device
    US9542262B1 (en) 2014-05-29 2017-01-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Error correction
    US9892033B1 (en) 2014-06-24 2018-02-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Management of memory units
    US9584159B1 (en) 2014-07-03 2017-02-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Interleaved encoding
    US9972393B1 (en) 2014-07-03 2018-05-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Accelerating programming of a flash memory module
    US9449702B1 (en) 2014-07-08 2016-09-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Power management
    US9524211B1 (en) 2014-11-18 2016-12-20 Avago Technologies General Ip (Singapore) Pte. Ltd. Codeword management
    US10305515B1 (en) 2015-02-02 2019-05-28 Avago Technologies International Sales Pte. Limited System and method for encoding using multiple linear feedback shift registers
    US10628255B1 (en) 2015-06-11 2020-04-21 Avago Technologies International Sales Pte. Limited Multi-dimensional decoding
    US9851921B1 (en) 2015-07-05 2017-12-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Flash memory chip processing
    US9954558B1 (en) 2016-03-03 2018-04-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Fast decoding of data stored in a flash memory
    CN106569747B (en) * 2016-10-27 2019-01-11 宁波迦南智能电气股份有限公司 A kind of the Data Position storage and search method of large capacity acquisition terminal
    CN112764683B (en) * 2021-01-22 2023-01-10 苏州浪潮智能科技有限公司 Storage block management information synchronous recording method, system, terminal and storage medium

    Family Cites Families (13)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    GB2251324B (en) 1990-12-31 1995-05-10 Intel Corp File structure for a non-volatile semiconductor memory
    FR2701578B1 (en) * 1993-02-16 1995-03-31 Gemplus Card Int Method for writing to a non-volatile memory, in particular to a memory card.
    US5485595A (en) * 1993-03-26 1996-01-16 Cirrus Logic, Inc. Flash memory mass storage architecture incorporating wear leveling technique without using cam cells
    US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
    US6081878A (en) * 1997-03-31 2000-06-27 Lexar Media, Inc. Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
    US5978812A (en) * 1995-11-10 1999-11-02 Sony Corporation Information processor and method of information processing
    US5761732A (en) * 1996-06-28 1998-06-02 Intel Corporation Interleaving for memory cards
    US6000006A (en) * 1997-08-25 1999-12-07 Bit Microsystems, Inc. Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage
    JPH11144478A (en) * 1997-11-10 1999-05-28 Hitachi Device Eng Co Ltd Information storage method for nonvolatile semiconductor memory and electronic device
    JPH11249968A (en) * 1998-03-05 1999-09-17 Sanyo Electric Co Ltd File recording method and file system
    US6148354A (en) * 1999-04-05 2000-11-14 M-Systems Flash Disk Pioneers Ltd. Architecture for a universal serial bus-based PC flash disk
    DE60037417D1 (en) * 1999-07-28 2008-01-24 Sony Corp RECORDING SYSTEM, DATA RECORDING DEVICE, MEMORY DEVICE, AND DATA RECORDING METHOD
    JP4037605B2 (en) * 2000-12-04 2008-01-23 株式会社東芝 Nonvolatile memory unit controller, memory system having the controller, and nonvolatile memory unit control method

    Also Published As

    Publication number Publication date
    KR20020079917A (en) 2002-10-19
    US20030014582A1 (en) 2003-01-16
    TW539950B (en) 2003-07-01
    JP4122972B2 (en) 2008-07-23
    KR100871027B1 (en) 2008-11-27
    EP1347383A4 (en) 2007-06-27
    WO2002054247A1 (en) 2002-07-11
    CN1426557A (en) 2003-06-25
    CN1307554C (en) 2007-03-28
    JPWO2002054247A1 (en) 2004-05-13
    US7065608B2 (en) 2006-06-20

    Similar Documents

    Publication Publication Date Title
    US7065608B2 (en) Apparatus for recording data and method for writing data to flash memory
    US6388908B1 (en) Recording system, data recording device, memory device, and data recording method
    RU2242805C2 (en) Recording method, control device and recording device
    US8161225B2 (en) Semiconductor memory card, access device and method
    US6865658B2 (en) Nonvolatile data management system using data segments and link information
    US8185705B2 (en) Information recording medium, information recording medium accessing apparatus and accessing method
    JP4315488B2 (en) Data storage device, data processing device, data processing system and data processing method
    US6345333B1 (en) Method and apparatus for reverse rewriting
    JPWO2009001519A1 (en) MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, ACCESS DEVICE, AND NONVOLATILE STORAGE SYSTEM
    CN102737715A (en) Data brown-out protection method for NOR flash memory
    CN102473141B (en) Nonvolatile memory devices and memory controller
    JPH09265427A (en) Storing method and storage device for rewritable rom
    JP2005078378A (en) Data storage device and data writing method for nonvolatile memory
    JP2008251063A (en) Storage device
    JP4308780B2 (en) Semiconductor memory device, memory controller, and data recording method
    KR100206186B1 (en) Data recovering equipment of rewritable nonvolatile memory and method thereof
    US20030210489A1 (en) Data eraser and data erasing program
    JPH0773098A (en) Data writing method
    US20050204115A1 (en) Semiconductor memory device, memory controller and data recording method
    JPH06332795A (en) Electrically erasable nonvolatile memory controlling method and system therefor
    JPH04307647A (en) Memory card storage control system
    JP3166659B2 (en) Storage device
    JP4661086B2 (en) Nonvolatile memory device and nonvolatile memory erasing and writing method
    JP2000222291A (en) Method for accessing flash memory and flash memory storing data to be accessed by the same
    JP2006048746A (en) Memory card

    Legal Events

    Date Code Title Description
    PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

    Free format text: ORIGINAL CODE: 0009012

    17P Request for examination filed

    Effective date: 20020812

    AK Designated contracting states

    Kind code of ref document: A1

    Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

    RBV Designated contracting states (corrected)

    Designated state(s): DE FR GB

    A4 Supplementary search report drawn up and despatched

    Effective date: 20070529

    17Q First examination report despatched

    Effective date: 20071113

    STAA Information on the status of an ep patent application or granted ep patent

    Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

    18D Application deemed to be withdrawn

    Effective date: 20140701