EP1346318A2 - Procede de commande a couleur binaire equilibree et procedes de commande a forme d'onde regulee numeriquement pour des affichages graphiques et systeme mettant en oeuvre de tels procedes - Google Patents

Procede de commande a couleur binaire equilibree et procedes de commande a forme d'onde regulee numeriquement pour des affichages graphiques et systeme mettant en oeuvre de tels procedes

Info

Publication number
EP1346318A2
EP1346318A2 EP01996011A EP01996011A EP1346318A2 EP 1346318 A2 EP1346318 A2 EP 1346318A2 EP 01996011 A EP01996011 A EP 01996011A EP 01996011 A EP01996011 A EP 01996011A EP 1346318 A2 EP1346318 A2 EP 1346318A2
Authority
EP
European Patent Office
Prior art keywords
display
image
color
ofthe
recited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01996011A
Other languages
German (de)
English (en)
Inventor
James Huston
Neil Bergstrom
Gang Xu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Three Five Systems Inc
Original Assignee
Three Five Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/727,095 external-priority patent/US20020101396A1/en
Priority claimed from US09/727,132 external-priority patent/US20020000967A1/en
Application filed by Three Five Systems Inc filed Critical Three Five Systems Inc
Publication of EP1346318A2 publication Critical patent/EP1346318A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0235—Field-sequential colour display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/065—Waveforms comprising zero voltage phase or pause
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0686—Adjustment of display parameters with two or more screen areas displaying information with different brightness or colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G09G3/2033—Display of intermediate tones by time modulation using two or more time intervals using sub-frames with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/34—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
    • G09G5/346—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a bit-mapped display memory

Definitions

  • the present invention relates to a display system for producing an image and more specifically to methods for applying digital information to generate color and grayscale.
  • a continuing objective in the field of electronics is the miniaturization of electronic devices.
  • Most electronic devices include an electronic display.
  • the miniaturization of electronic displays is critical to the production of a wide variety of compact electronic devices.
  • electronic devices such as personal digital assistants, cell phones, digital still cameras, DVD players and internet appliances become ever smaller and more portable, the demands on the electronic displays for these products must meet difficult and seemingly contradictory requirements.
  • the displays must provide increasing amounts of high quality visual information, sometimes approaching that of a desktop monitor. Yet these displays must still be very compact and lightweight, consume little power, and be produced at low cost. Until recently, displays were not able to meet all of these requirements.
  • an electronic display is to provide the eye with a visual image of certain information.
  • This image may be provided by constructing an image plane composed of an array of picture elements (or pixels) which are independently controlled as to the color and intensity ofthe light emanating from each pixel.
  • the electronic display is generally distinguished by the characteristic that an electronic signal is transmitted to each pixel to control the light characteristics which determine the pattern of light from the pixel array which forms the image.
  • CTR cathode ray tube
  • AMLCD active-matrix liquid crystal display
  • the CRT is an emissive display in which light is created through an electron beam exciting a phosphor which in turn emits light visible to the eye.
  • Electric fields are used to scan the electron beam in a raster fashion over the array of pixels formed by the phosphors on the face plate ofthe electron tube.
  • the intensity ofthe electron beam is varied in an analog (continuous) fashion as the beam is swept across the image plane, thus creating the pattern of light intensity which forms the visible image.
  • three electron beams are simultaneously scanned to independently excite three different color phosphors respectively which are grouped into a triad at each pixel location.
  • an AMLCD display utilizes a lamp to uniformly illuminate the image plane which is formed by a thin layer of liquid crystal material laminated between two transparent conductive surfaces which are comprised of a pattern of individual capacitors to create the pixel array.
  • the intensity ofthe illumination light transmitted through each pixel is controlled by the voltage across the capacitor, which is in turn controlled by an active transistor circuit connected to each pixel.
  • This matrix of transistors (the active matrix) distinguish the AMLCD from the passive matrix liquid crystal devices which are strictly an array of conductors controlled by transistors external to the image area usually in the periphery ofthe matrix. The ability of each transistor to control the characteristics of just one pixel allows for the higher performance found in AMLCD displays in contrast to the passive arrays.
  • the electronic signals which control the images are transmitted to the pixel from driver circuits along the edges ofthe rows and columns.
  • driver circuits along the edges ofthe rows and columns.
  • an enabling signal to the corresponding row driver activates the transistor connected to each pixel in that row to pass the voltage onto the capacitor forming the pixel.
  • This storage mechanism is similar to dynamic memory cells (DRAM) although the cells are typically addressed serially (rasterwise) rather than randomly as DRAM implies.
  • DRAM dynamic memory cells
  • the electronic activation ofthe image must be continuous or persistent through repetition.
  • a constant or highly repetitive source of energy must be applied to the pixel to create photon emission.
  • Phosphor decay times are typically a few milliseconds.
  • the capacitors in the AMLCD array lose their charge through leakage and accurate grayscale levels are lost.
  • many liquid crystal materials exhibit ion migration and must be reversed in polarity with each refresh cycle.
  • displays with limited persistence must be refreshed frequently to avoid noticeable brightness variation known as flicker.
  • displays with substantial persistence cannot display moving images without ghost images. Refreshing the image of most displays requires repeated transmission ofthe image data to the display, either from the broadcast source or from a storage device.
  • High resolution displays may contain hundreds of thousands of pixels.
  • the Super VGA (SVGA) display resolution consists of 480,000 pixels.
  • the frame storage is only equal to the approximately one-half megabit frame size.
  • the frame storage would approach 12 megabits.
  • At the frame rates which are common today for high performance displays at least 60 frames per second and up to 85 frames per second, as many as one gigabits per second must be transferred from the frame buffer to the display.
  • the state of semiconductor technology at present limits clock speeds to a level well below such transfer rates and parallel interfaces of 16 to 32 bit widths are typical in high performance displays.
  • DAC digital-to-analog converter
  • the amount of data written to the display in each subsequent frame can be substantially reduced if the writing operation is organized to be random, such as to write data to any location in the array and only to those locations where the data is changing for reasons that the image is moving or for reasons the array is reused sequentially to create a composite image. To achieve this end however, pixel locations which are not being rewritten must be able to store data and continually display it.
  • micro electro-mechanical system MEMS
  • polymeric dispersed cholesteric liquid crystals which are inherently bistable due to nonlinearities ofthe electro-optic response curve.
  • image storage within the device itself can be indefinite although without color or grayscale.
  • grayscale can be achieved through time division ofthe image frame into a multiplicity of on and off states which on average provide a shade proportional to the signal pattern.
  • a multiplicity of transistors may be provided in correspondence to each pixel such that a static memory (SRAM) cell (typically four or six transistors) can be utilized to activate each pixel.
  • SRAM static memory
  • There are several advantages to static memory such as the on-state output voltage always being at the rail voltage, the low activation current, no voltage decay, and sufficient signal to noise to read from the memory cells any stored data.
  • a static memory cell is itself bistable, the pixel activation will provide no analog grayscale.
  • displays with no analog response fall into three categories.
  • Those displays with an extremely fast response in relation to the time divisions ofthe on- off cycles can achieve grayscale through pulse width modulation.
  • This modulation can be a modulation ofthe liquid crystal response while the illuminating pulse is held constant or a modulation ofthe illumination duration while the liquid crystal is controlled to be either on or off during the period of illumination.
  • Those displays with a relatively slow response time in relation to on-off cycles (as is typical of liquid crystal devices) can achieve grayscale through a root mean square (RMS) voltage level based on the average time-voltage product.
  • RMS root mean square
  • each picture element is divided into three or more sub-pixels and a color filter, typically red, green and blue, is placed in the light path from each sub-pixel.
  • the eye merges these sub-pixels to create a color image.
  • This method suffers from significant light loss in the color filters, requiring up to four times as much power to be supplied to the illumination system.
  • the color filters also add significant additional cost to the display.
  • the second method avoids the high power requirement and added cost ofthe sub-pixel/color filter method. Instead, a single pixel is used for red green and blue images in a sequential manner.
  • the pixel sizes are also small relative to the size of color filters used in TFT AMLCD displays to create color triads for each pixel.
  • LEDs light emitting diodes
  • This method of color creation is called field sequential color wherein each color field is sequentially illuminated by the appropriate diode. Because at least three different color field images need to be displayed at a rate faster than can be resolved by the eye, the field sequential color method at least triples the data transfer rate required as compared to a monochrome display.
  • the display system should also be adaptable for use as a microdisplay.
  • red, green and blue levels are stored into the array as analog voltage levels. These levels control directly the voltage applied to liquid crystal between pixel and ITO layer to produce the various shades of color under constant illumination.
  • the voltage level of each pixel is maintained by the active- matrix circuit until a new value is applied to the pixel.
  • Red, green, and blue component sub-pixels are simultaneously applied to the
  • LC Liquid Crystal
  • Analog control is far more sensitive to variations in cell gap, temperature, and LC contaminates, requiring high levels of quality control during manufacture.
  • a display matrix is provided for forming a composite image from a series of sub-images.
  • the display matrix includes a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel.
  • Each display circuit includes a plurality of memory cells, and a selector for outputting to the pixel data from one memory cell at a time.
  • a plurality of memory cells in the display circuit are continuously electrically connected to the selector ofthe display circuit at the same time.
  • the display circuit including separate conductive elements for each memory cell in the display matrix which electrically connects a memory cell to the selector in the display circuit.
  • the display matrix is formed on a substrate having a plurality of regions where each region includes a memory circuit with a plurality of memory cells, and a selector electrically connected to the plurality of memory cells in the region.
  • the substrate may be any material on which the display circuit may be attached or formed.
  • the substrate is a semiconductor, such as silicon, on which the display circuits are formed by one or more of a variety of methods known in the art.
  • the memory cells are physically inter-dispersed among the selectors within the plurality of display elements.
  • the memory associated with the display matrix is integrated into the display matrix as opposed to be external to the display matrix and the selectors.
  • at least a portion ofthe display circuits of the display matrix include at least 2 memory cells per display circuit.
  • at least a portion ofthe display circuits ofthe display matrix include at least 3 memory cells per display circuit.
  • the display matrix may optionally include 4-18 or more memory cells per display circuit, depending on a variety of factors which will be discussed herein.
  • the display matrix has sufficient memory such that data can be transferred to the display matrix for one sub-image while a different sub-image is displayed.
  • the display matrix may also have sufficient memory to display two or more different sub-images without having to write to the memory cells between displaying the different sub-images.
  • the plurality of memory cells in each circuit can represent different bits of a digital grayscale value. It is possible to vary the digital grayscale value significance of a particular memory cell image to image and field to field.
  • the plurality of memory cells in each circuit can represent bits of different color fields.
  • the display circuit can be operated in a field sequential color (FSC) mode without having to write to the memory cells between displaying different fields.
  • FSC field sequential color
  • the display matrix may optionally be configured to be operated in a field sequential color (FSC) mode without having to write to the memory cells between displaying different fields.
  • Data preferably can be both written to and read from the memory cells.
  • data for forming a sub-image can be written randomly to the memory cells.
  • the memory cells are static random access memory (SRAM) cells.
  • the display matrix is sized to form a microdisplay.
  • the pixels in the plurality of display elements may form a source object having an area equal to or less than about 400 mm 2 and preferably between about 20 mm 2 and 100 mm 2 .
  • the pixels ofthe display matrix preferably have an area less than about 0.01 mm 2 and more preferably between 50 m 2 and 500 m 2 .
  • the present invention also relates to a display system which includes a display matrix according to the present invention and peripheral control circuits for controlling read and write operations to the memory cells.
  • the display system may also include an illumination source for illuminating the pixels.
  • the display includes a light emitting mechanism provided at each pixel.
  • the display system may also include a light modulating mechanism, such as a liquid crystal material, provided at each pixel.
  • the display system may optionally further include logic for reading, inverting and rewriting data stored in the memory cells to provide a refresh cycle, a processor for reading, modifying, and rewriting data stored in the memory cells to compose a bit mapped image without the need of an external frame buffer, control circuits for reading, modifying, and rewriting data stored in the memory cells to provide a cursor function.
  • the peripheral control circuits may also serve to read, move, and rewrite data stored in the memory cells to provide a scroll function.
  • the display system may also include an illumination source capable of providing a plurality of different color illumination to the pixels, the particular color illumination provided to the pixels being coordinated by the peripheral control circuits with the read and write operations to the memory cells. Two, three or more different colors of illumination may be provided.
  • the illumination source preferably provides at least three different colors of illumination.
  • the display matrices and display systems ofthe present invention may be used in a display component of a variety of electronic devices. Examples of such devices include, but are not limited to portable computers, personal communicators, personal digital assistants, modems, pagers, video and camera viewf ⁇ nders, mobile phones, and television monitors. In one particular embodiment, the display matrices and display systems ofthe present invention are used in combination with one or more magnification optics to form a virtual image display system.
  • the present invention also relates to methods of using the display matrices and display systems ofthe present invention to produce composite images as described herein.
  • an image generation system in another embodiment, is provided.
  • a display matrix is provided and has a plurality of display elements which can include liquid crystal. Each display element includes a pixel.
  • a plurality of display circuits are electrically connected to a display element.
  • a plurality of memory cells are associated with each ofthe circuits, or form part ofthe circuit, and a selector continuously electrically connected to more than one of the plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time.
  • Peripheral control circuits preferably control read and write operations to the memory cells.
  • the virtual image display system further includes a light emitting mechanism, which may be a mechanism provided at each pixel, a light modulating mechanism provided at each pixel, and/or an illumination source for illuminating the pixels.
  • a light emitting mechanism which may be a mechanism provided at each pixel, a light modulating mechanism provided at each pixel, and/or an illumination source for illuminating the pixels.
  • Logic suppresses image flicker utilizing balanced binary color. The same data can be used to display monochrome and color information.
  • each memory cell is used to generate either an optically on state or an optically off state in the liquid crystal, when selected.
  • the selector selects one memory cell of each display elements, for all ofthe display elements simultaneously.
  • the light emitting mechanism can produce an LED pulse.
  • the duration ofthe LED pulse provides a binary decoding.
  • the pulse can have a set duration and represent a bit of color information, n pulses of n duration may be applied where each pulse represents the n most significant bit of color information.
  • the system reduces viewing artifacts due to residual ionic contamination of the display material.
  • a balance of an applied voltage and a resulting electric field form a color image rapidly which diminishes the time for ion migration and enhances the color image quality.
  • a polarity reversal to a voltage applied to a liquid crystal is decoupled from a display update frequency.
  • the voltage application and reversal is such that no net voltage is applied to the display elements over a duration of time, thereby maximizing the liquid crystal relaxation response time.
  • a method for generating an image is provided.
  • a display element of a display is switched to zero volts for a first duration of time, where the display element includes a pixel.
  • a first voltage is supplied to an electrode ofthe display element for a second amount of time.
  • the second voltage may be of a substantially equal magnitude and would be supplied to the counterelectrode for about the same time as the aforementioned predetermined time.
  • An illumination pulse is applied to the pixel for illuminating the display element for a predetermined number of units of duration where the units of duration can be in fractions of milliseconds, etc. This process can be repeated for each bit of color information to be displayed.
  • the virtual image display system further includes a light emitting mechanism, which may be a mechanism provided at each pixel, a light modulating mechanism provided at each pixel, and/or an illumination source for illuminating the pixels.
  • a light emitting mechanism which may be a mechanism provided at each pixel, a light modulating mechanism provided at each pixel, and/or an illumination source for illuminating the pixels.
  • Logic increases response speed of an image display utilizing a digitally controlled waveform. The same data can be used to display monochrome and color information.
  • a method for generating an image is also provided. According to the method, a shade of color is generated by controlling a duration that each display element is optically on. Illumination is applied to illuminate the display element.
  • an additional data bit is used to display a color image field for each pixel.
  • n flashes corresponding to the value ofthe data in the memory cell are used to vary the intensity ofthe image display.
  • a single rise and fall time can be used for a color field to enhance image processing.
  • the width of a pulse defines a grayscale of a color.
  • the width of a voltage pulse can be used a grayscale of color.
  • one or more illumination pulses can be applied to the display element for illuminating the display element for generating a shade of color, one pulse for each data bit in a sequence of data bits of a color field.
  • Figure 1 illustrates a display matrix
  • Figure 2 illustrates a display circuit which may be used in the display matrix ofthe present invention.
  • Figure 3 illustrates a prior art display circuit
  • Figure 4A illustrates a cross-sectional view of a liquid crystal device.
  • Figure 4B illustrates a top-down view of a liquid crystal device.
  • FIG. 5 illustrates a backplane integrated circuit (backplane IC) which may be used in a display matrix ofthe present invention.
  • backplane IC backplane integrated circuit
  • Figure 6 illustrates a configuration of strobe lines connected to display circuits.
  • Figure 7A illustrates a virtual image display system which includes a display matrix which projects an image onto a back surface ofthe first magnification optic which reflects (at least partially by total internal reflection) the image to a surface having a magnification function and a reflection function.
  • Figure 7B illustrates a virtual image display system which includes an illumination source which reflects light off the microdisplay system to a beamsplitter which reflects an image formed by the microdisplay to a surface ofthe first magnification optic having a magnification function and a reflection function.
  • Figure 7C illustrates a virtual image display system which includes an illumination source which reflects light off the microdisplay system to a back surface of a first magnification optic which reflects the light to a beamsplitter which reflects the light to a surface ofthe first magnification optic having a magnification function and a reflection function.
  • Figure 8A illustrates the data transfer and display sequence of a prior art display matrix which employs a single memory cell per pixel.
  • Figures 8B and 8C illustrate data transfer and display sequences that may be used when a display matrix according to the present invention which employs two or more memory cells per pixel is operated in an FSC mode.
  • Figure 9A illustrates a time line for displaying one bit plane for a larger portion of the time that a particular frame is displayed by displaying that bit plane longer than other bit planes.
  • Figure 9B illustrates a time line for displaying one bit plane for a larger portion ofthe time that a particular frame is displayed by displaying that bit plane more frequently than other bit planes.
  • Figure 10 illustrates a pair of display circuits and a pair of pixels, wherein the display circuits are partially within the footprints of each ofthe pixels, and the pixels are partially within the footprints of each ofthe display circuits.
  • Figure 11 illustrates a matrix of display circuits and pixels, wherein multiple data circuits overlap the footprints of multiple pixels, and data lines are connected to multiple display circuits.
  • Figure 12 illustrates five display circuits, each of which is partially within the footprint of each of five pixels, wherein a single set of data lines is connected to all five data circuits.
  • Figure 13 illustrates a local decoder connected to four rows of data circuits.
  • Figure 14 illustrates a system in which a processor interfaces directly to the backplane IC.
  • Figure 15A illustrates an address map including scroll buffers.
  • Figure 15B illustrates an address map which can scroll pixel by pixel.
  • Figure 16 illustrates a system in which an external frame buffer is placed between the processor and the backplane IC.
  • Figure 17 illustrates part of a color rich mode sequence.
  • Figure 18 illustrates a color mixing mode
  • Figure 19 shows a block diagram of a display system employed in the present invention.
  • Figure 20 illustrates single color bit dynamics.
  • Figure 21 illustrates how the BBC method is used to produce a single RGB (red, green, blue) color frame.
  • Figure 22 is a flow diagram of a process for generating an image utilizing balanced binary color.
  • Figure 23 illustrates the basic shape of a waveform according to the DCW method.
  • Figure 24 is a flowchart of a process for generating an image utilizing a digitally controlled waveform.
  • Figure 25 is a flow diagram of a process for driving a display utilizing an analog controlled waveform.
  • Figure 26 illustrates spatially distributed phases for 1 bit of temporal color.
  • Figure 27 illustrates spatially distributed phases for 2 bits of temporal color.
  • the present invention relates to a display matrix for forming sequentially formed composite images.
  • a sequentially formed composite image is an image formed by displaying a series of two or more different sub-images to an observer where the different sub-images are displayed one sub-image at a time on the display matrix.
  • These display matrices can be used in a display system component of a variety of electronic devices. Examples of such devices include, but are not limited to portable computers, personal communicators, personal digital assistants, modems, pagers, video and camera viewfinders, mobile phones, and television monitors.
  • the display matrices and display systems ofthe present invention are used in combination with one or more magnification optics to form a virtual image display system.
  • a unique property ofthe display matrix ofthe present invention is that data for a plurality of sub-images may be stored in the display matrix simultaneously. This property eases the instantaneous bandwidth requirements ofthe display matrix and, in certain situations, actually decreases the amount of data which must be transferred to the display matrix from external memory locations.
  • a display system forms a sequentially formed composite image by displaying a series of sub-images to an observer at a rate preferably faster than the eye ofthe observer can resolve.
  • Image quality is reduced if the eye is able to perceive an individual field sub-image, a phenomena known as flicker.
  • flicker In practice, it has been found that frame rates in excess of 60 Hz are necessary to avoid flicker.
  • the data for any sub-image should be present in the display matrix from the beginning until the end ofthe display ofthe sub-image. If the display matrix houses only a single sub-image at a time, then ideally the entire data transfer should take place between the display of one sub-image and the next. This places high instantaneous bandwidth requirements on the system in order to transfer all of the data for a sub-image in the interval between the display of sub-images.
  • FIG. 1 illustrates a typical display matrix 12 which includes a plurality of display elements 14.
  • Each display element 14 includes a pixel 16 and a display circuit 18 which is electrically connected to the pixel and controls the operation of the pixel 16.
  • the plurality of pixels incorporated into the plurality of display elements together form the source object formed by the display matrix 12.
  • the display circuit consists of a plurality of memory cells and a selector.
  • the selector is able to output to the pixel the contents of at most one memory cell at any instant.
  • the selector is controlled by additional input signals provided to the display circuit.
  • Figure 2 illustrates a display circuit 18 which may be used in the display matrix ofthe present invention.
  • the display circuit 18 includes a plurality of memory cells 20A, 20B (two shown) which are each electrically connected to a selector 22.
  • the selector controls which memory cell is electrically connected to the pixel 16.
  • the display circuit 18 can also optionally receive one or more inputs 24 for controlling the operation ofthe selector 22.
  • a feature ofthe display circuit and display matrix ofthe present invention is that a plurality ofthe memory cells in the display circuit are continuously electrically connected to the selector ofthe display circuit at the same time. As a result, there is no need to address a particular memory cell to a particular selector. This may be accomplished, as illustrated in Figure 2, by the display circuit including separate conductive elements 21 for each memory cell in the display matrix which electrically connects a memory cell to the selector in the display circuit. The figure illustrates that all the memory cells in the display circuit are connected. It is noted that less than all ofthe memory cells may optionally be continuously electrically connected.
  • a further feature ofthe display circuit and display matrix ofthe present invention is that the display matrix is formed on a substrate having a plurality of regions where each region includes a memory circuit with a plurality of memory cells, and a selector electrically connected to each memory cell in the region.
  • Figure 1 illustrates a plurality of display circuits in separate regions. By having a plurality of regions which each include a complete memory circuit, a display matrix is provided where the memory cells are physically inter-dispersed among the selectors within the display matrix. This distinguishes the display matrix of the present invention over prior art displays with an external frame buffer.
  • the substrate may be any material on which the display circuit may be attached or formed.
  • the substrate is a semiconductor, such as silicon, on which the display circuits are formed by one or more of a variety of methods known in the art.
  • Yet a further feature ofthe display matrix ofthe present is its ability to store more than one image at a time. Because the display circuit 18 has more than one memory cell per pixel, it is possible to display two or more different sub-images without having to write to the memory cells between displaying the different sub- images. In addition, data may be transfe ⁇ ed to the display matrix for one sub-image while a different sub-image is displayed. Accordingly, the data transfer time for one sub-image can be spread over the entire display time of a different sub-image. This alleviates the need for a high instantaneous bandwidth or a high sub-image display rate, a clear advantage over prior art display systems.
  • Figure 3 illustrates a prior art display circuit.
  • the prior art display circuit includes a single memory cell 20C which is connected to pixel 16.
  • the prior art display circuit thus does not need a selector or input for controlling the operation ofthe selector.
  • the display circuit only includes one memory cell 20C, a memory matrix employing this display circuit can only store data for one sub-image and thus cannot display different sub-images without having to write to the memory cells between displaying the different sub- images.
  • the sub-images are typically composed in a spatial relationship and written simultaneously to the matrix.
  • the display matrix ofthe present invention may be any addressable display which includes a pixel and a display circuit which controls the operation ofthe pixel in response to control signals.
  • a pixel (a contraction of picture element) refers to any mechanism which can either emit light or modulate incident light in response to an electrical field to form one element of a source object.
  • the plurality of pixels incorporated into the plurality of display elements together form the source object formed by the display matrix.
  • suitable pixels include but are not limited to the pixels used in liquid crystal displays, spatial light modulators, gratings, minor light valves, and LED arrays.
  • the pixels can be opaque or light transmissive.
  • Opaque pixels can be further divided into reflective, emissive, and scattering pixels.
  • the pixels used in the display matrix are sized to be a microdisplay.
  • a microdisplay refers to a display matrix which is used in a virtual image display system to form a source object which is then magnified by one or more magnification optics to form a magnified virtual image.
  • the microdisplay forms a source object having an area equal to or less than about 400 mm 2 .
  • the source object has an area between about 10 mm 2 and 400 mm 2 , more preferably between about 20 mm 2 and 100 mm 2 .
  • the pixels ofthe display matrix preferably have an area less than about 0.01mm 2 and more preferably between 50 m 2 and 500 m 2 .
  • microdisplays By designing a microdisplay to include a display circuit according to the present invention, microdisplays with reduced instantaneous bandwidth requirements and reduced average bandwidth are provided.
  • the reduced bandwidth requirements translate into lower power consumption, which is particularly important for battery-powered applications in devices which incorporate microdisplays.
  • a microdisplay which includes a liquid crystal device (LCD) and operates in either reflective or scattering modes.
  • LCD liquid crystal device
  • Figure 4A illustrates a cross-sectional view of a liquid crystal device while Figure 4B illustrates a top-down view of a liquid crystal device.
  • the LCD 32 is composed of a substrate 34 having a plurality of electrodes 36 corresponding to pixels, liquid crystal 38 arranged on the substrate 34, and a counter electrode 40 a ⁇ anged on the liquid crystal 38.
  • the liquid crystal is caused to align or relax at each pixel in response to local electric fields applied across the liquid crystal between the pixel and the counter electrode.
  • the potential at each pixel on the substrate is determined by the co ⁇ esponding display circuit, the design of which is the subject ofthe present invention. Sequentially changing the potentials at any or all ofthe pixels on the substrate via the co ⁇ esponding display circuits causes the LCD as a whole to form a composite image when properly illuminated.
  • a sub-image is observed when the LCD is illuminated after allowing sufficient time for the liquid crystal to align or relax according to the voltage pattern on the pixels.
  • a multicolor image may be produced by performing the following sequence sequentially with different colored illumination sources: (1) turning off illumination; (2) stimulating the liquid crystal with a voltage pattern on the pixels for a first sub-image or field; (3) waiting a sufficient period of time for the liquid crystal to form the source object; and (4) illuminating the liquid crystal. The above sequence is repeated for each light source present.
  • Figure 5 illustrates a backplane integrated circuit (backplane IC) which may be used in a display matrix such as a LCD microdisplay.
  • backplane IC backplane integrated circuit
  • the backplane IC 42 integrates into a single electronic circuit a display matrix 44, programmable registers 46 that generate the control signal logic 48 provided to the display matrix 44 and other timing functions, and an interface 50 to a source of image data.
  • a display matrix for this backplane IC may be sized to include an 800 by 600 two-dimensional a ⁇ ay of display circuits.
  • the display circuit for a backplane IC is composed of two or more memory cells and a selector circuit.
  • the memory cells may be conventional Static Random Access Memory (SRAM) cells composed of six transistors each, though the use of other digital memory cells is intended to fall within the scope ofthe present invention.
  • SRAM Static Random Access Memory
  • SRAM for the memory cells facilitates fabrication ofthe IC.
  • SRAM can be fabricated by the same process steps and fabrication tools as the selector circuit.
  • the selector and SRAM may be formed on a substrate with one poly-silicon layer and three or four metal layers, lp3m or lp4m. This obviates the need for different fabrication processes for the memory and logic components ofthe IC, and reduces the number of mask levels required in fabrication.
  • the SRAM cells may be called RED CELL, GREEN CELL, and BLUE CELL, respectively.
  • the cells are addressed for reading and writing via WORD signals.
  • Data is transferred into and out of the SRAM cells via BIT and BIT BAR signals.
  • the cells can share the BIT and BIT BAR data signals and have separate address signals, possibly named RED WORD, GREEN WORD, and BLUE WORD, respectively. Or the cells can share a WORD address line and have separate data signals, such as RED BIT and RED BIT BAR, etc.
  • the selector is accomplished with switches that connect the SRAM cells to the pixel at the output ofthe display circuit.
  • the switches may be pass gates controlled by RED STROBE, GREEN STROBE, and BLUE STROBE signals, respectively.
  • RED STROBE signal When the RED STROBE signal is asserted, the voltage stored in the RED CELL is transferred to the pixel.
  • the GREEN STROBE and BLUE STROBE signals operate analogously.
  • the various WORD and STROBE signals are provided to each display circuit based on programmable registers inside the backplane IC but outside the display matrix.
  • each cell is connected to a individual strobe line. This design allows each cell to be strobed individually, thereby minimizing the power consumed in the operation ofthe display system and optimizing the operation speed ofthe display.
  • multiple cells are connected to individual strobe lines.
  • This design reduces the wiring density of he IC.
  • the display system can be designed to have a desired level of wiring density. It is noted that power efficiency and operation speed decrease as wiring density decreases. The particular wiring density that is prefe ⁇ ed will depend upon the particular application for which the display is being designed and the wiring density, power efficiency, and operation speed that are required.
  • Figure 6 illustrates an embodiment where the total number of strobe lines in the display system is reduced from a 1 : 1 strobe line to memory cell ratio by increasing the number of memory cells connected to individual strobe lines.
  • Figure 6 illustrates an embodiment where each strobe line co ⁇ esponding to a color and is connected to a plurality of cells ofthe respective color so that each STROBE signal controls a plurality of cells ofthe respective color.
  • the figure depicts four display circuits 600, 602, 604, 606 with three SRAM cells per display circuit.
  • Each display circuit 600 has a RED CELL 608, a GREEN CELL 610, and a BLUE CELL 612.
  • the four RED CELLS (608A-D) are connected to a single RED STROBE 614 by connection 614A
  • the four GREEN CELLS (610A-D) are connected to one GREEN STROBE 616 by connection 616A
  • the four BLUE CELLS (612A-D) are connected to one BLUE STROBE 618 by connection 618 A.
  • the RED STROBE signal is activated, the voltages stored in the four RED CELLS connected to the RED STROBE are transfe ⁇ ed to their respective pixels.
  • the GREEN STROBE and BLUE STROBE signals operate analogously.
  • the display matrix ofthe present invention can be designed to be employed in a wide variety of electronic devices in which a real or virtual image needs to be displayed.
  • the display matrix is intended for use in small sized electronic devices such as portable computers, personal communicators, personal digital assistants, modems, pagers, video and camera viewfmders, mobile phones, television monitors and other hand held devices.
  • the display matrix is employed in a virtual image display system where the display matrix forms a source object which is then magnified by one or more magnification optics.
  • the display matrix is preferably sized to be a microdisplay.
  • Figures 7A-7C illustrate three examples of a virtual image display which include a display matrix according to the present invention, and one or more magnification optics.
  • Figure 7A illustrates a virtual image display system which includes a display matrix 62 which projects an image onto a back surface 63 ofthe first magnification optic 64 which reflects (at least partially by total internal reflection) the image to a surface 65 having a magnification function and a reflection function.
  • the surface 65 reflects the image to a second magnification optic 66 and to an observer 67.
  • Figure 7B illustrates a virtual image display system which includes an illumination source 69 reflects light off the microdisplay system 62 to a beamsplitter 71 which reflects an image formed by the microdisplay to a surface 73 ofthe first magnification optic 64 having a magnification function and a reflection function.
  • the surface 73 reflects the image through the beamsplitter 71 to a second magnification optic 66 and to an observer 67.
  • Figure 7C illustrates a virtual image display system which includes an illumination source 75 which reflects light off the microdisplay system 62 to a back surface 77 of a first magnification optic 64 which reflects the light to a beamsplitter 79 which reflects the light to a surface 81 ofthe first magnification optic 64 having a magnification function and a reflection function.
  • the surface 81 reflects the light through the beamsplitter 79 to a second magnification optic 66 and to an observer 67.
  • Examples of virtual image display systems which can be used include but are not limited to the virtual image display systems described in U.S. Patent Nos.: 5,625,372; 5,644,323; and 5,684,497.
  • One feature ofthe present invention is the efficiency with which the display matrices of the present invention may be operated in a field sequential color (FSC) mode.
  • FSC field sequential color
  • a composite image is formed through the repetition of a sequence of different color sub-images, typically red, green, and blue sub- images.
  • the one or more sub-images 26 co ⁇ esponding to a color is called a field 28.
  • a single sequence of the different fields is called a frame 29.
  • Sub-image data generally differs by field 28 in an FSC system.
  • the composite image appears monochrome with gray levels.
  • Data transfer requirements for an FSC mode are more stringent than for a general system for sequentially formed composite images.
  • the total length of time that a sub-image may be displayed, from the end ofthe display ofthe prior sub- image to the end ofthe display ofthe cu ⁇ ent sub-image, is limited by the minimum frame rate necessary to avoid flicker.
  • the data for a particular sub-image must also be present in the display matrix from the beginning to the end ofthe sub-image. The quality ofthe image produced is reduced if part ofthe one color frame is displayed while a part of another color frame is displayed.
  • FIG 8A illustrates the data transfer and display sequence of a prior art display matrix which employs a single memory cell per pixel.
  • the entire data transfer for a sub-image takes place during a time period TDT after the time period for displaying the prior sub-image T DI - I and before the time period for displaying the cu ⁇ ent sub-image, also TDI-2-
  • TDT time period for displaying the prior sub-image
  • T MFR minimum frame rate
  • the need to transfer the entire data for a sub-image during the time period T D T which is less than the minimum frame rate T MFR time period creates a high instantaneous bandwidth requirement on a prior art display matrix operating in an FSC mode.
  • the average bandwidth requirement which is a direct function ofthe frame rate as well, is accordingly high.
  • Figures 8B and 8C illustrate data transfer and display sequences that may be used when a display matrix according to the present invention which employs two or more memory cells per pixel is operated in an FSC mode.
  • a display matrix employs two or more memory cells per pixel, it is possible to store data for more than one sub-image, whether ofthe same or a different field.
  • the display matrix includes sufficient data to store all ofthe individual sub-images of a field or the entire composite image simultaneously.
  • the use of two or more memory cells per pixel in a display matrix significantly reduces the instantaneous bandwidth requirement of the system.
  • the data for one particular field sub-image is the same as the that for the next sub-image ofthe same field, the data for the next sub-image does not need to be transfe ⁇ ed at all, reducing the average bandwidth requirement.
  • the present invention is intended to encompass display matrices where each memory cell consists of one bit or more than one bit of memory.
  • a digital display system refers to a display system where a single binary bit of memory is associated with each memory cell.
  • the selector outputs a binary value as a function ofthe data stored in the memory cells, and binary control signals are provided to each display circuit.
  • binary is meant a two-level voltage system, where each voltage can be represented by either a 0 or a 1.
  • gray levels within a particular color field may be attained by multiplexing different sub-images of that field.
  • certain sub-images are rendered more significant to the composite field image than other sub-images.
  • the first memory cell in each display circuit may co ⁇ espond to the most significant bit (MSB) ofthe binary representation ofthe grayscale values for a particular field.
  • the second memory cell in each display circuit may co ⁇ espond to the least significant bit (LSB).
  • the first memory cell may be the most significant bit (MSB), the second memory cell the second significant bit (SSB), and the third memory cell the least significant bit (LSB).
  • a multiple grayscale field may be formed.
  • One bit may be displayed for a larger portion ofthe time that a particular frame is displayed either by displaying that bit longer, as illustrated in Figure 9A, or by displaying that bit more frequently, as illustrated in Figure 9B.
  • a four-level grayscale system is achieved in a two bit system when the MSB sub-image is displayed for twice as long as the LSB sub-image.
  • the total display time for both sub-images equals the display time for the field.
  • the number of gray levels possible is equal to 2 N , when N is the number of sub-images.
  • One particular sub-image co ⁇ esponds to the MSB ofthe binary representation ofthe gray level; another to the LSB.
  • Sub-images co ⁇ esponding to the 2 nd (2 nd SB), 3 rd (3 r SB), and further significant bits ofthe binary representation are possible for systems of more than two sub-images.
  • the total duration of one sub-image is proportional to 1 / 2 M , where M is the significance ofthe bit co ⁇ esponding to the sub-image.
  • the total duration for one sub-image may be continuous or broken into smaller time slices for interleaving with other sub-images.
  • the total number of perceived colors possible in a system is the product of the number of gray levels for each constituent color field. For example, 64 colors may be generated by a three color system where each color has a four degree gray level (4x4x4).
  • two memory cells are present in each display circuit. Once data has been loaded into the display matrix, it is possible to form either a dichromic composite static image or a four-level grayscale monochromic composite static image.
  • one memory cell of each display circuit contains the data co ⁇ esponding to one color field and to the location ofthe display circuit within the image.
  • the second memory cell contains the co ⁇ esponding data for the second field.
  • the memory cells of each display circuit contain the MSB and LSB ofthe image data associated with a single color field.
  • the MSB and LSB ofthe image data associated with a single color field.
  • each memory cell in a display circuit ofthe present invention co ⁇ esponds to a sub-image.
  • the sub-images co ⁇ esponding to different memory cells are output from the display matrix according to the control signals provided to each display circuit.
  • the sub-images can have any order and may be displayed for any amount of time. For example, a particular sub-image may be displayed more frequently than other sub-images, as in the case ofthe MSB sub-image.
  • the sub- image may also be displayed for a longer period of time than other sub-images.
  • the assignment of sub-images to different memory cells may be dynamic.
  • the assignment ofthe first, second, and third memory cells as the MSB, SSB, or LSB can be changed, field to field and/or frame to frame.
  • the first memory cell of every display element may at one time be assigned to the MSB sub-image ofthe red field and at another time to the LSB sub-image ofthe green field.
  • the display image data is transfe ⁇ ed to the display matrix from a frame buffer.
  • the frame buffer is typically external to the display system in the sense that the frame buffer is a separate component from the display matrix.
  • an external frame buffer The purpose of an external frame buffer is to house an entire frame of data and act as an intermediary between some sort of processor, which initializes and modifies the image in the frame buffer, and the display matrix, which displays the image or part thereof.
  • the data transfer bandwidth between the processor and the frame buffer varies according to the rate of change in the content ofthe image. For example, a static, monochromic image requires essentially zero bandwidth. In a display system operating in an FSC mode with a high frame rate, the bandwidth requirement remains high regardless of how static the image may be.
  • a display matrix ofthe present invention can also be used to store multiple sub-images, for example all the sub-images of a single color field as opposed to an entire frame.
  • a display matrix ofthe present invention operated in an FSC mode, it is possible to house an entire frame of data in the display matrix itself.
  • the advantage of housing an entire frame of data within the display matrix is that the external frame buffer may be completely eliminated from the display system, saving not only a component but also a great deal of bandwidth. Only the bandwidth between the processor and the display matrix would remain. In contrast, operating a prior art display matrix in FSC mode, there is no room within the display matrix to house multiple sub-images simultaneously, necessitating an external frame buffer.
  • the display matrix behave like an external frame buffer from the processor point of view.
  • the display matrix should behave like a memory: random access addressable as well as readable and writable.
  • the display matrix of prior art typically is not random access addressable and is only writable.
  • the primary interface to the display matrix from the source of image data can mimic that of a synchronous SRAM.
  • the clocked interface includes a general backplane IC chip select and a read / write signal.
  • An internal write buffer supports consecutive writes to the memory cells in the display matrix and to programmable registers outside the display matrix.
  • the latency to the first read data from either the memory cells or the programmable registers is a fixed number of cycles. Data on consecutive cycles is returned on burst reads.
  • the length of burst accesses can be programmed to be 1, 2, 4, or 8 words, where the length of a word is defined as the data bus width. The latter is initialized to 8 bits on reset, but can be reprogrammed to 8, 16, or 32 bits.
  • a total of 20 address lines can be used to specify the destination of a read or write to the memory matrix.
  • the secondary interface can include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock, along with 8, 16, 24, 32, or some other intermediate number of bits of data.
  • the secondary interface can be used to scan data into the display matrix only, with no capability to read data from the matrix.
  • ROM read only memory
  • FPGA field programmable gate a ⁇ ay
  • external frame buffer external frame buffer
  • An aspect ofthe present invention relates to layout designs for positioning a plurality of display circuits adjacent pixels of a corresponding display element. For instance, in a display system ofthe present invention, there are multiple memory elements per pixel. As the number of memory elements per pixel increases, it becomes increasingly difficult to position the display circuit including the plurality of memory elements adjacent the pixel. It is thus necessary to design the layout of the display matrix to accommodate for display circuits which do not fit within the spatial confine, or "footprint", ofthe corresponding pixel.
  • Figure 10 illustrates two rectangular display circuits 202A, 202B placed under two pixels 204 A, 204B.
  • Each display circuit is at least partially located within the footprints of both pixels. Additionally, each pixel is placed within the footprints of both display circuits. However, each ofthe display circuits has an electrical connection to only one ofthe pixels 206A, 206B, thereby preserving the co ⁇ espondence of one pixel to one display circuit in each display element.
  • One feature ofthe layout designs illustrated in Figures 10-12 is the positioning of multiple address lines under each pixel or under each row of pixels.
  • each ofthe display circuits In order to facilitate random access to the memory elements of each display circuit, each ofthe display circuits must be separately addressable. This requires each display circuit to be connected to an address line. When two or more display circuits are placed in the footprint of a pixel, the same number of address lines are placed under the pixel, one for each display circuit.
  • Each ofthe display circuits 202A and 202B is connected to a single address line, 208A and 208B, respectively. But since both display circuits lie within the footprint of one pixel 204A, there are two address lines running under one row of pixels 212 in the display matrix.
  • the layout illustrated in Figures 10-12 were multiple display circuits are positioned within the footprint of a pixel provides a further advantage of enabling a substantial decrease in the number of data lines (e.g., bit and bit bar lines) used in the display system.
  • data lines e.g., bit and bit bar lines
  • the layout also results in an increase in the number of address lines that are used in the display system in order to preserve random access to the memory elements in the display system.
  • the reduction in the number of data lines is more significant.
  • Each display circuit in the display matrix connects to a BIT line and a BIT BAR line.
  • each display circuit within the footprint of a pixel can be connected to the same BIT and BIT BAR lines. This allows for a net reduction in the number of BIT and BIT BAR lines connected entering the display system.
  • display circuits 208A, 208B are both located under pixel 204A and pixel 204B.
  • An address line is provided for each display circuit, shown in the figure as address lines 208A, 208B.
  • a single pair of data lines (BIT 210A and BIT BAR 210B) are used for both display circuits.
  • BIT 210A and BIT BAR 210B are used for both display circuits.
  • Figure 11 illustrates another embodiment where there are two rows and four columns of pixels (300A, 300B, 300C, 300D and 302A, 302B, 302C, 302D).
  • Each row of pixels is divided into two pairs with a pair of display circuits (304A-H) being positioned underneath the pair of pixels, as in Figure 10.
  • Two address lines (306A- D) are positioned under each row of pixels and a pair of data lines (308A-D) are provided for each two columns of pixels.
  • a total of 8 data and address lines are employed.
  • BIT and BIT BAR lines were used for each column of pixels, and an address line were used for each row of pixels, 10 data and address lines would be employed.
  • Figure 12 illustrates yet another embodiment where there are five display circuits (402A-E) and five address lines (404A-E) running under the display circuits. Meanwhile, a single set of data lines (406A-B) are used for the five display circuits. As can be seen, only 7 data and address lines are used. By contrast, if one were to use 1 address line and 5 it would be connected to 3 pairs of data lines, one pair per memory cell. Since there are 800 columns, there would need to be 4800 data lines. Combined, a total of 5400 lines are needed.
  • each display circuit includes 5 memory cells. Assume each display circuit is positioned within the footprint of each pixel. According to this layout design, there would be 600 address lines (1 address line per row) and 8000 data lines (800 columns x 2 lines per memory cell x 5 memory cells) for a total of 8600 lines.
  • An aspect ofthe present invention relates to the use of local decoding of row addresses in the display system to reduce the number of address lines, or "word lines," in the display system.
  • decoders are inserted at periodic intervals in the display matrix. These decoders are connected to surrounding display circuits, so that each decoder is connected to rows ofthe display matrix.
  • Each decoder receives a word line, two sub-word lines, and an enable line.
  • the sub-word lines supply two bits, a Most Significant Bit (MSB) and a Least Significant Bit (LSB) which provide an offset for selecting one of the rows connected to the decoder. This obviates the need to connect an address line to each of the rows connected to the decoder.
  • the enable bit is used to minimize power consumption.
  • Figure 13 is a schematic illustration of local decoding.
  • the local decoder 500 is connected to four rows of display circuits 502A, 502B, 502C, 502D in the display matrix.
  • the rows of display circuits connected to the local decoder 500 are refe ⁇ ed to herein as a cluster of display circuits.
  • the third line entering the local decoder from above is an enable bit 504, intended to save power.
  • the data lines serve as sub-address lines by controlling which display circuits are being operated by the local decoder.
  • the two data lines MSB and LSB provide an offset for selecting one ofthe rows connected to the decoder.
  • Each value ofthe (MSB,LSB) pair connotes exactly one ofthe rows entering the decoder. For instance, "00" may denote the first row 502A, "01" the second row 502B, " 10" the third row 502C, " 11 " the fourth row 502D.
  • the connection ofthe rows to the decoder, coupled with the offset provided to the local decoder, can be used to reduce the number of address lines connected to the rows ofthe display matrix. In particular, the number of address lines may be reduced by a factor equal to the number of values that can be denoted by the offset. To illustrate, consider Figure 13.
  • each of these four rows may be selected by one ofthe four values ofthe offset.
  • the display system needs only one word line connected to the decoder, and a pair of sub-word lines to select one of those four rows connected to the decoder.
  • the number of address lines used in the display system can be reduced by a factor of four.
  • the local decoders are placed after every 16 pixel columns.
  • the number of address lines are reduced by a factor of four, to 150, resulting in 450 fewer address lines.
  • the addition ofthe 150 offset and enable lines is countered by a decrease in 450 address lines.
  • the insertion of local decoders also confers benefits during fabrication ofthe display system, as it obviates the need to fabricate word lines in metal.
  • the present embodiment eliminates the need for global word lines which span each row of display circuits, as global word lines are replaced with relatively short interconnects between decoders.
  • the relative brevity ofthe interconnects allows them to be fabricated in poly-silicon rather than metal.
  • the absence of metal word lines in the IC results in improved packing density, and frees space for other metal interconnects.
  • the display circuit layout designs described above, for example with regard to Figures 10-12, can be combined with local decoding to produce a drastic reduction in the number of address and data lines entering the display matrix.
  • the number of data lines can be significantly reduced by connecting data lines to multiple data circuits.
  • the resulting increase in address lines can then be diminished by replacing global word lines with local decoders.
  • One mode refe ⁇ ed to herein as the "Power Miser Mode” relates to a mode where writing to the display matrix is minimized, there reducing the amount of energy consumed by the display matrix.
  • Another mode of operation refe ⁇ ed to herein as the “Color Rich Mode” relates to a mode where data is written to memory cells forming one bit plane while memory cells of another bit plane are used to display an image in order increase the number of sub-images that can be used to form a composite image. By being able to increase the number of sub-images that can be used to form a composite image, a greater number of colors may be formed by the display matrix.
  • Yet another mode of operation refe ⁇ ed to herein as the "Color Mixing Mode,” involves operating a display matrix in a Power Miser Mode and Color Rich Mode at the same time.
  • FIG. 14 One mode of operating a display matrix according to the present invention is illustrated in Figure 14 in which a processor 54 interfaces directly with the display matrix (backplane IC) 42.
  • This mode is referred to herein as power miser mode because the image is initialized and modified directly in the display matrix memory without the use and associated power consumption of an external frame buffer.
  • the backplane IC is fundamentally digital in nature, component and power consumption costs associated with digital-to-analog converters or other analog circuitry is avoided.
  • the backplane IC offers several functions in support of power miser mode.
  • the synchronous SRAM interface on the chip coincides with the memory model assumed by typical processors.
  • the chip also offers capacity for a red, a green, and a blue bit plane, the minimum necessary for a display matrix to operate in an FSC mode.
  • the chip can also be programmed for FSC control, a sequence such as the following:
  • the RED, GREEN, and BLUE cells of each display circuit are filled with the MSB, SSB, and the LSB ofthe co ⁇ esponding image data.
  • the three bit planes can be strobed in a variety of time modulation schemes to achieve the eight levels of grayscale in the color ofthe single illumination source.
  • One possibility is to strobe the bit planes in RMS fashion using distributed binary coding as described later.
  • Scrolling in the present invention consists of shifting a scroll region horizontally or vertically by a pixel.
  • the contents of a scroll buffer are used to fill in the area vacated by the shift.
  • the scroll region can be an entire bit plane or portion thereof.
  • Figure 15A illustrates an address map including scroll buffers.
  • the address bus illustrated in the figure is 20 bits wide. Bits A 6 through Ao specify the column address of a byte, A ⁇ 6 through A 7 its row address, and A 18 through An its bit plane address.
  • This address scheme assumes the three SRAM cells in each display element have been configured for separate address (WORD) signals.
  • the address space ofthe display matrix encompasses 0-99 in the column address, 0-599 in the row address, and 0-2 in the bit plane address.
  • Bit A ⁇ 9 is the programming bit.
  • Buffers outside the active region are allocated for scrolling.
  • the address space of a horizontal scroll buffer encompasses 100 in the column address and 0-599 in the row address.
  • the address space of a vertical scroll buffer encompasses 0-99 in the column address and 600-607 in the row address.
  • a scroll procedure may comprise the following steps:
  • the scroll buffer for a particular direction and bit plane is modified through processor reads and writes to its address space.
  • the scroll region programming registers are modified as necessary.
  • the scroll command is issued by writing to the appropriate register.
  • the backplane IC begins scrolling.
  • the scroll region is the area over which data will be shifted.
  • the scroll region is defined by the coordinates of its upper left (X UL , Y U L) and lower right (X R , Y LR ) corners.
  • the coordinates in the present invention are specified with byte granularity, so that the possible values are 0-99 in the X-direction and 0-74 in the Y- direction. Values greater than 99 in the X-direction and 74 in the Y-direction are prohibited. Data outside the scroll region will not be affected by the scrolling operation.
  • FIG. 15B A second embodiment of scrolling is illustrated in Figure 15B.
  • a scroll region is first defined.
  • the region is eight pixels high by eight pixels wide. However, it can be any region within the display matrix on a one-pixel boundary in the vertical direction and a two pixel-boundary in the horizontal direction.
  • the scrolling operation can move the contents of the scroll region up or down by one pixel or left or right by two pixels without affecting any of the data outside of the scroll region.
  • one row of pixels is always left unchanged by vertical scrolling and two columns of pixels by horizontal scrolling. These unchanged pixels must be overwritten by the new information from the external system to complete the scroll.
  • Scrolling is an example of hardware assistance for a graphical operation that is outside the operation of display matrices of prior art.
  • the external frame buffer within the display matrix ofthe present invention in power miser mode, a wide variety of hardware assistance functions for image modification become possible and useful within the display matrix.
  • FIG. 16 A second mode of operating a display matrix according to the present invention is illustrated in Figure 16, in which an external frame buffer 56 is placed between the processor 54 and the display matrix (backplane IC) 42.
  • This mode is refe ⁇ ed to herein as color rich mode, because the multiple bit planes in the display matrix are used to generate multiple levels of grayscale in each ofthe color fields. For example, when three bit planes are used, eight levels of grayscale (2 ) are produced in each of three color fields for a total of 512 colors (8 3 ) in FSC operation.
  • Figure 17 illustrates part ofthe above sequence.
  • the numbers 0, 1, and 2 are used to represent the RED, GREEN, and BLUE bit planes, respectively.
  • Each color field in the figure has been divided into a RECOVERY and an ACTIVE period.
  • the length ofthe ACTIVE period equals the length of time that the LEDs are turned on.
  • a detail contained in the figure though omitted in the above sequence is that the turn on time for an LED may be delayed from the start ofthe ACTIVE period.
  • the ACTIVE and RECOVERY periods may have different length. The sum of their lengths is determined by the length of a field, which is typically one-third the length ofthe frame.
  • Gray levels in a particular color field are produced by multiplexing sub- images temporally at a very fast rate.
  • the sub-images co ⁇ espond to bit planes and multiplexing is the same as strobing.
  • RMS Root Mean Squared
  • strobing algorithms are possible to achieve a certain gray level. For instance, in a 3 bit-plane system, a conventional coding scheme might divide up an interval, such as the RECOVERY or ACTIVE period, into seven equal parts, and assign the MSB plane to the first four parts, the SSB plane to the next two parts, and the LSB plane to the last part. Then a gray level 4 would be achieved by a 1111000 sequence, a 5 by a 1111001 sequence, etc.
  • distributed binary coding One algorithm that has been found empirically to have a better RMS effect than the above conventional coding scheme for a particular LCD is called distributed binary coding.
  • a better RMS effect refers to the gradation in voltages driven on the liquid crystal being more uniform.
  • the interval is first always divided into (2 N - 1) time slots.
  • the MSB plane time slots are determined first.
  • the MSB plane is always placed in the first time slot and every other time slot there after.
  • the 2 nd SB plane time slots is calculated next.
  • the SSB plane is placed in the first available time slot and every fourth time slot thereafter.
  • the 3 rd SB occupies the next available time slot and every eighth slot thereafter, and so on until the LSB (N th ) plane is place in the middle time slot.
  • the formula is ⁇ MSB, 2 nd SB, MSB, 3 rd SB, MSB, 2 nd SB, LSB, MSB, 3 rd SB, MSB, 2 nd SB, MSB ⁇ .
  • the ability ofthe display system ofthe present invention to perform distributed binary coding is a strong example of one ofthe advantages that the display circuit ofthe present invention provides.
  • the grayscale level is strobed twice in one color field, once in the RECOVERY period and once in the ACTIVE period, for a total of 14 time slots. In a system with only one memory cell per display circuit, fourteen bit planes would have to be loaded in order to strobe during 14 different time slots. This would require a very high bandwidth transfer rate and pixel refresh rate.
  • the present invention it is possible to alternate the assignment of MSB memory matrices for consecutive color fields.
  • This enables the display matrix to further take advantage of having more than one memory cell in each display circuit.
  • the ⁇ RED, GREEN, BLUE ⁇ memory matrices were assigned to ⁇ MSB, SSB, LSB ⁇ for the RED field, while in the ensuing GREEN field, the assignments were switched to ⁇ LSB, SSB, MSB ⁇ .
  • This algorithm is driven by the nature of distributed binary coding, in which the LSB plane always falls in the middle time slot while the MSB plane is always at the beginning.
  • the memory plane can be used for the first plane needed by the GREEN field, which is the MSB plane.
  • the bit planes as MSB, SSB and LSB, etc., it is possible to increase the number of bit planes which can be written to memory and strobed.
  • the backplane IC can include logic for performing a variety of algorithms. Such software control can also accommodate timing parameter changes which may be necessitated by temperature conditions or other factors.
  • Interrupts to the external frame buffer can also be provided to trigger the transfer of data to the next available memory plane.
  • a third mode of operating a display matrix according to the present invention relates to the overlay of a color rich region on a power miser background. This mode of operation is illustrated in Figure 18.
  • a window of high information content can be formed without incurring the bandwidth and power consumption costs associated with full-screen color rich operation.
  • the reduction in bandwidth requirements improves the compatibility ofthe display matrix with video applications.
  • An example of a color mixing procedure that may be employed is as follows:
  • the power miser mode is specified to be either 3 color fields at 1- bit/field or 3-bit monochrome, by writing to the appropriate configuration register as necessary.
  • the window region is the area over which data will be displayed in color rich mode.
  • the area around the outside ofthe window region operates in power miser mode.
  • the window region is defined by the coordinates of its upper left (X UL , Y UL ) and lower right (XLR, Y LR) corners.
  • the coordinates must be specified with byte granularity, so that the possible values are 0 - 99 in the X-direction and 0 - 74 in the Y-direction. Values greater than 99 in the X-direction and 74 in the Y-direction are prohibited.
  • the present invention also relates to the incorporation of various algorithms into memory resources and their utilization in display systems to control data flow and operation of a display system.
  • Figure 19 shows a block diagram of a display system that may be used in the present invention. It should be noted that other configurations of displays, including those set forth above, may be used in practicing various embodiments ofthe present invention.
  • ASIC 802 is designed to take standard, bit-mapped data from the host system, either directly from the microprocessor 804 or by an interface circuit (not shown), and separate this data into separate color components (e.g., red, blue and green). These components are stored as separate color sub-images so that they may be supplied to the backplane 806 to generate each red, blue and green image (color fields) needed for sequential color definition. Given the compact size of a microdisplay, it may not be feasible to build sufficient memory into the backplane 806 to support displaying images with a large number of colors. As a result, an external memory is used, such as a frame buffer 808, in conjunction with a custom integrated circuit (ASIC) to rapidly provide this information to the backplane 806. Color information is supplied in a format well suited for the different algorithm ofthe present invention to be used. The hardware and software work together in combination with the algorithms ofthe present invention.
  • ASIC custom integrated circuit
  • various types of image processing such as spatial dithering, may be applied to the data either before or after the image data is separated into the color fields.
  • This storage can either take place within the ASIC chip 802 or on a separate frame buffer chip 808 (memory) connected to the ASIC.
  • a second feature ofthe ASIC 802 is its ability to rapidly send each color field to the backplane 806 in a specific sequence as may be required for a given algorithm.
  • the algorithms ofthe present invention involve different applications of individual bits of color field data, depending on the method. These various methods have been optimized for color generation under various device designs, environmental conditions and color requirements, and refresh rates. Data transfer bit sequencing, timing and clock speeds can be set by the ASIC chip.
  • this architecture allows for voltages supplied to the counter electrode 810 to be offset so that only the change in voltage required for liquid crystal transitions need be applied.
  • the counter electrode offset voltage must be supplied for both positive and negative liquid crystal voltages, as needed to possible negative effects caused by steady state (DC) voltage components.
  • the counter-electrode 810 signals originate on the backplane chip 806 and the voltage levels are set by an additional driver chip (not shown in Figure 19).
  • the ASIC chip 802 can work with the backplane 806 to determine when and how the counter-electrode voltage is altered, as will be discussed in the description ofthe drive methods.
  • a black and white image may be presented on a field sequential color display by presenting the same image bit pattern during Red, Green, and Blue sequential illumination. Pixels optically off will appear black, while those optically on will appear white.
  • the image data requires only 1 bit per pixel and this data may be sent to the backplane once for all three color fields.
  • a programmable 2x3 bit lookup table in the ASIC 802 provides a means of mapping colors to substitute for black and white image information, i.e. yellow text on a blue background.
  • the table contains one bit for each primary color (RGB) to substitute for "black” bits, and one bit for each primary color to substitute for "white” bits, in the monochrome image data.
  • the backplane then stores the substituted 3 bit color for each bit written to it.
  • the amount of data written to the backplane is still one bit per pixel, but the backplane can now present three substituted values, one for each ofthe color fields.
  • the 2x3 bit lookup table need not be restricted to use as color substitution in monochrome images. For higher color applications, this same table can be used as a means of generating a unique LC drive method.
  • a method for suppressing image brightness flicker is refe ⁇ ed to herein as the Balanced Binary Color (BBC) method.
  • BBC Balanced Binary Color
  • This method may be used with high color applications where there is a need to suppress image brightness flicker.
  • the method can be used for color images or monochrome images by simply choosing the co ⁇ ect color field sequence. For example, normal color can be obtained by using the method to apply different color sub-images for red, green and blue color fields. The same data for each color field can be used for monochrome images of a black and white nature. Single color images will require only one color field. Other combinations are possible.
  • the core of this method is the way a single bit of color is generated. At this bit level, the method can be applied to other color schemes.
  • each bit is used to generate a voltage across the liquid crystal, and then illuminate the resulting full color field by an LED flash supplied to the full backplane chip image area.
  • the duration ofthe LED pulse provides a binary decoding.
  • the first pulse may be of 1 unit duration and represent the least significant bit of color information.
  • the next bit is then applied and the LED is flashed for 2 units of duration representing the next most significant bit. This is followed by a bit of data and an LED flash 4 units in duration, and so on.
  • the BBC method can be used to reduce viewing artifacts, such as flicker and contrast reduction, due to residual ionic contamination ofthe liquid crystal material.
  • Color depths can range from one to eight or more bits of color per color field. This co ⁇ esponds to from 2 to 256 shades of color for the color field. Consider the example of 4 bits, or 16 shades of color when decoded using binary counting. For a fully digital backplane design, such as the one described in Application Serial No. 09/311 ,804 (which is incorporated herein by reference in its entirety), only one bit at a time can be applied to the pixel electrode.
  • One aspect ofthe invention relates to how each bit is applied at the pixel electrode and counter electrode prior to and during the LED flash.
  • each bit used to generate color is applied in a manner that uses either zero applied voltage or equal plus and minus voltage pulses such that no net DC voltage component is applied.
  • the first two values, Sub[l] and Sub[2] could also be viewed as "data" and "not data".
  • the Sub[3] bit is the same regardless of input data. This data, when switched to the backplane pixels causes all pixels to go to zero volts. Because the Sub[3] bit plane is always written with 0's, new image data can be written (changing Sub[l] and Sub[2]) while the Sub[3] bit plane is switched to the pixel array without affecting the LC.
  • Figure 20 illustrates single color bit dynamics. As shown in Figure 20, at the beginning of each bit of color, all pixels in the image a ⁇ ay are switched to zero volts on the pixel electrode.
  • the command for this action originates in the ASIC chip 802 and is carried out by the backplane 806, but may also be carried out entirely by the backplane 806 if circuit densities permit sufficient control and storage on the backplane 806 so as to negate the need for a separate ASIC chip 802.
  • the liquid crystal molecules are strongly switched into their normal state by the anchoring forces supplied by the alignment layers located at the pixel electrode and the counter electrode.
  • the normal state may result in either a normally bright or a normally dark state in the full display system, depending on the light path, polarizers employed and the type of electro-optic liquid crystal mode.
  • the BBC method works effectively in either case.
  • This zero voltage phase the most rapid possible return to the normal state is realized since any applied voltage during this period would only serve to slow the return of all pixels due to counter acting forces tending to orient the molecules away from this state.
  • This zero voltage phase lasts for a time long enough to allow the liquid crystal molecules to mostly relax to the normal state and may be on the order of a millisecond in duration.
  • two bits of data are supplied to the local storage at each pixel location. These data bits are complimentary and represent a 01 or a 10 pair. For purpose of example, suppose that we associate a 01 pair with a dark pixel and a 10 pair with a bright pixel. Let us further suppose that the normal state is bright. Then zero 01 pair, for example, can be associated with a Vdd pixel voltage followed by a zero pixel electrode voltage. During this time, the counter electrode will first be set at -Vb (during the pixel "0") and then at Ndd+Vb (during the pixel "1"). The result will be a high voltage of magnitude Vdd+Vb applied during the full data phase.
  • the voltage would follow the dark line 2002 in Figure 20, first reaching a value of Vdd+Vb and then an equal and negative voltage of-Vdd-Vb.
  • the liquid crystal molecular orientation responds only to the magnitude of this voltage and so it is acted on by a uniform orienting force during the data phase. In this example, the result would be a dark bit value for this particular pixel.
  • the result is a balance ofthe applied voltage, and the resulting electric field, at each pixel and for each individual bit comprising the color image.
  • This allows extremely little time for ion migration to occur and affect the desired performance. Since these effects can occur on timescales associated with a single polarity of applied voltage, this method can reduce such timescales to the sub-millisecond range. Contrast this to the analog method where a single polarity of applied voltage is applied during each color field. The polarity is not reversed until the next full color frame. Thus a 60 frame per second analog display would see a balanced voltage pulse applied at a rate of only 30 times per second since 2 frames are necessary. Thus the BBC method balances the applied voltages over timescales up to 50 times faster or more.
  • Figure 21 illustrates how the BBC method is used to produce a single RGB (red, green, blue) color frame.
  • the top curve 2102 shows the voltage at the liquid crystal.
  • the middle curve 2104 shows the liquid crystals response to this voltage.
  • the bottom curve 2106 shows the LED flash sequence with binary weighted flash duration.
  • a single full frame of red, green and blue is shown for the case were 3 bits of data are applied for each ofthe red, green and blue colors. This would produce 512 colors total, after the eye and brain ofthe viewer fuses the temporally separate color images.
  • the number of bits in the example is arbitrary. Total time for each color field is approximately:
  • N is the number of bits being displayed per color
  • a display matrix is provided and has a plurality of display elements which can include liquid crystal. Each display element includes a pixel.
  • a plurality of display circuits are electrically connected to a display element.
  • a plurality of memory cells are associated with each ofthe circuits, or form part ofthe circuit, and a selector continuously electrically coimected to more than one ofthe plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time.
  • Peripheral control circuits preferably control read and write operations to the memory cells.
  • the virtual image display system further includes a light emitting mechanism, which may be a mechanism provided at each pixel, a light modulating mechanism provided at each pixel, and/or an illumination source for illuminating the pixels.
  • a light emitting mechanism which may be a mechanism provided at each pixel, a light modulating mechanism provided at each pixel, and/or an illumination source for illuminating the pixels.
  • Logic suppresses image flicker utilizing balanced binary color. The same data can be used to display monochrome and color information.
  • each memory cell is divided into a bit that is used to generate a voltage across the liquid crystal and illuminate a color field using an LED pulse.
  • the duration ofthe LED pulse provides a binary decoding.
  • the pulse can have a set duration and represent a bit of color information, n pulses of n duration may be applied where each pulse represents the n most significant bit of color information.
  • the system reduces viewing artifacts due to residual ionic contamination of the display material.
  • a balance of an applied voltage and a resulting electric field form a color image rapidly which diminishes the time for ion migration and enhances the color image quality.
  • a polarity reversal to a voltage applied to a liquid crystal is decoupled from a display update frequency.
  • Figure 22 is a flow diagram of a process 2200 for generating an image.
  • a display element of a display is switched to zero volts for a first duration of time, where the display element includes a pixel.
  • a first voltage is supplied to an electrode ofthe display element for a second amount of time in operation 2204.
  • the second voltage may be of a substantially equal magnitude and can be supplied to the counterelectrode for about the same time as the aforementioned predetermined time.
  • An illumination pulse is applied to the pixel in operation 2208 for illuminating the display element for a predetermined number of units of duration where the units of duration can be in fractions of milliseconds, etc. This process can be repeated for each bit of color information to be displayed.
  • DCW Digitally Controlled Waveform
  • the DCW method can be performed by controlling individual bit responses using the techniques ofthe BBC method and a simple binary digital application ofthe data.
  • the DCW method is desirable when response speed is important, such as at lower temperatures.
  • the full BBC method is more desirable when it is needed to reduce flicker.
  • the DCW method's response time advantage is made possible by only requiring a single rise and fall time for each color field, rather than one per color bit as needed in standard binary methods.
  • the relaxation time (rise time for a display that is normally white) may or may not occur at zero volts in this method, and so the relaxation time could be somewhat longer. Nevertheless, the method still has a strong overall advantage in terms of response time due to the single waveform approach.
  • the basic shape of the waveform 2300 is shown in Figure 23. According to the method, 4 bits of data are used to display a 3 bit color image field for every pixel.
  • the waveform consists of a single rise and fall waveform incorporating from zero to 4 LED flashes depending on the value ofthe 4 data bits.
  • This scheme is able to fully display the shades of color produced by 3 data bits at the frame buffer.
  • the 3 data bits produce 8 levels of color for the red, blue or green color fields. These 8 levels correspond to values of 0 to 7 in intensity. These 8 levels can be represented by various combinations of LED flashes of weight I, 2, 2, and 2.
  • the 4 bits supplied by the ASIC to the backplane map the original 3 bits into the new 4 bit space with only a single rise and fall. Table 2, below, shows an example ofthe mapping:
  • the waveform has only a single rise and fall.
  • the exact shape ofthe waveform only indirectly controls the intensity value. This is due to the use ofthe waveform as an envelope to include the appropriate LED pulses of duration 1 and 2 units. To the degree that the waveform approaches a square wave, the coupling can be very weak. For finite rise and fall times, some interaction between the LED flashes and the waveform shape occurs. Because of this, the first LED flash of unit duration may be made slightly longer to compensate. Other adjustments can be made to achieve the most faithful representation ofthe original 8 levels. For a full color frame of data, similar sequences are strung together for red, green and blue color fields. Note that no special voltage pulses are required. Also, this technique relies on the use of local data storage for each pixel.
  • the write times for these pixels can be invisible as long as the data transfer rate from the ASIC and frame buffer is faster for each bit than either rise or a fall, but not the sum of rise and fall. This is due to the need only to begin or end the single waveform before or after an LED pulse.
  • max time is the maximum of rise time or fall time
  • the waveforms of Figure 23 include this compensation bit.
  • this method can be considerably faster.
  • the compensated DCW method requires 3 milliseconds per color field and frame rates approximately as high as 111 frames/second can be achieved.
  • lower temperature operation can be provided at 60 frames/second. Compare this to 3 bits per color with standard binary methods where 3(1.5milliseconds) are needed per field, resulting in a maximum frame rate of 74 frames/second.
  • Figure 24 is a flowchart of a process 2400 for generating an image.
  • a shade of color is generated by controlling a duration that each display element is optically on. Illumination is applied to illuminate the display element in operation 2404.
  • an additional data bit is used to display a color image field for each pixel.
  • n flashes corresponding to the value ofthe data in the memory cell are used to vary the intensity ofthe image display.
  • a single rise and fall time can be used for a color field to enhance image processing, and this does not have to be dependent upon the number of bits employed.
  • the width of a pulse defines a grayscale of a color.
  • the width of a voltage pulse can be used a grayscale of color.
  • one or more illumination pulses can be applied to the display element for illuminating the display element for generating a shade of color, one pulse for each data bit in a sequence of data bits of a color field.
  • RGB levels are stored into the a ⁇ ay as analog voltage levels. These levels control directly the voltage applied to liquid crystal between pixel and ITO layer to produce the various shades of color under constant illumination. The voltage level of each pixel is maintained by the active-matrix circuit until a new value is applied to the pixel.
  • Red, green, and blue component sub-pixels are simultaneously applied to the LC as a group to form a single pixel. Variations in color response ofthe LC is accounted for in each pixel, rather than by different voltage levels of ITO.
  • Binary control of LC avoids many complications of analog drive methods. Analog control is far more sensitive to variations in cell gap, temperature, and LC contaminates, requiring high levels of quality control during manufacture.
  • the voltage (at each pixel) is compared to a reference voltage input to the LC to control the duration that the LC is "optically on", such as in a similar manner as set forth above in the section entitled “Digitally Controlled Waveform Method.”
  • a reference voltage input to the LC For each frame (or field when using field sequential color), all pixels in the matrix are allowed to become optically on (or off) prior to the application of illumination.
  • the reference voltage is changed over time, causing each pixel to change state (optically on to off, or off to on) at the precise time that its voltage value matches the reference level.
  • the matching value may instead be a threshold differential value for the transistor used as the analog computer.
  • the analog levels of RGB can be individually selected (multiplexed) over time for presentation to the analog comparitor.
  • the output ofthe comparitor controls the state of a single pixel, which is illuminated with the appropriate color in the field sequence.
  • the described circuit and method can be applied as an improvement to all existing implementations of analog active matrix LC panels and cells.
  • the described circuit may be equally applicable as an improvement to non-active matrix implementations of analog LC panels and cells as well as to MEMS displays and other types of displays.
  • the described circuit may have direct application to control color levels in OLED displays.
  • OLEDs may be driven digitally in their optimum illumination range, resulting in potential power savings and simplified color level control.
  • power consumption can be spread evenly over time. These grouped pixels may, of course, be physically interspersed on the display to avoid flicker a low update rates.
  • FIG. 25 is a flow diagram of a process 2500 for driving a display.
  • a voltage capacitance is stored in an analog memory associated with each pixel of a display, where each ofthe pixels also has a comparator associated with it. Note that there may be single memory cells for each pixel.
  • a reference voltage and the voltage capacitances stored in the analog memory are applied to the comparators ofthe pixels in operation 2504.
  • the comparators are used to compare the voltage capacitances with the reference voltage for determining which ofthe voltage capacitances matches the reference voltage.
  • the state ofthe pixels whose voltage capacitance matches the reference voltage is changed in operation 2508.
  • the display can be an active matrix panel display as well as a non- active matrix display, OLED display, or other type of display.
  • illumination may be applied after the actuation ofthe one or more pixels.
  • the reference voltage can be changed as a function of time to cause each pixel to actuate and de-actuate at a desired time.
  • Groups ofthe pixels can be actuated. In such case, the groups of pixels are actuated in multiple phased cycles. Preferably, the groups are interspersed on the display to avoid flicker at low update rates.
  • SFD SuperFrame Dithering
  • N+M bits of color are applied to N digital bits per color field over several frames where the M bits of additional color are applied in a spatially distributed manner so as to reduce the amount of brightness modulation that is observed.
  • the SFD method may or may not be used with the BBC method.
  • N+l bit per color
  • N bit/color drive method For example, four bits of color data are stored in the frame buffer. To display the fourth bit using a 3 digital bits, the value ofthe fourth bit of data may be added to every other frame where the third bit ofthe data would appear. Table 4 below illustrates the case for the example where the three most significant bits are 010 for both a 0 and a 1 fourth bit value over sequential frames.
  • the perceived pixel values for three bits as shown above correspond to the four bit pixel values.
  • 010 and Oil average to the binary value 0101 as long as we apply the most significant bits with the same weighting for 3 or 4 bit numbers.
  • the same effect on average is achieved that would be achieved by adding one more binary data cycle with a flash duration half as long as the original third bit's flash duration.
  • the SFD method further includes spatially distributing when the additional bit is displayed so that the additional bit is not displayed by all the pixels at the same time. Since the human vision system responds more slowly to data with fine detail, spatially offsetting the frames where the additional bit is being displayed reduces the perceived flicker.
  • Figures 26 shows one method for achieving a spatial offset.
  • each group of 2 pixels along a row or column contains pixels with both A and B frames.
  • the intensity modulation is not perceived. This is easy to see for the case of a region of uniform color.
  • the viewers averages over time and so the full resolution ofthe image is realized.
  • the possible artifact of flicker is minimized due to the averaging over adjacent pixels. This allows the use of temporal dither at color depths that would otherwise not be possible due to the perceivable amount of intensity fluctuation at half the frame rate.
  • a display operating at a frame rate of 80 frames/second will generate the co ⁇ ect intensity perception if the user can average over four frames.
  • the flicker which could be perceived as low as 20 cycles/second is suppressed by the spatial averaging.
  • Various other spatial averaging schemes are possible.

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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

L'invention concerne un système de génération d'images. Une matrice d'affichage comporte une pluralité d'éléments d'affichage qui peut comprendre des cristaux liquides. Chaque élément d'affichage comprend un pixel. Une pluralité de circuits d'affichage est connectée de manière électrique à un élément d'affichage. Une pluralité de cellules de mémoire est associée à chacun desdits circuits, ou forme une partie du circuit, ainsi qu'à un sélecteur continuellement connecté de manière électrique à plus d'une cellule de mémoire de ladite pluralité de cellules, le sélecteur transmettant au pixel les données provenant d'une cellule de mémoire à la fois. Des circuits de commande périphériques commandent de préférence des opérations de lecture et d'écriture vers les cellules de mémoire. L'invention concerne également un mécanisme émetteur de lumière, qui peut être un mécanisme présent à chaque pixel, un mécanisme modulateur de lumière, présent à chaque pixel, et/ou une source d'éclairage pour éclairer les pixels. Un circuit logique supprime le papillotement de l'image au moyen de couleur binaire équilibrée. L'invention concerne également un procédé de génération d'image. Un élément d'affichage d'un affichage est commuté sur zéro volt pendant une première période. Une première tension est appliquée à une électrode de l'élément d'affichage pendant une seconde période. Une seconde tension est appliquée à une contre-électrode dudit élément d'affichage pendant une troisième période, de sorte qu'aucune tension de réseau ne soit appliquée à l'élément d'affichage. Une impulsion d'éclairage est appliquée au pixel pour éclairer l'élément d'affichage pendant un nombre prédéterminé d'unités de temps, lesdites unités de temps pouvant être exprimées en fractions de millisecondes etc.
EP01996011A 2000-11-29 2001-11-29 Procede de commande a couleur binaire equilibree et procedes de commande a forme d'onde regulee numeriquement pour des affichages graphiques et systeme mettant en oeuvre de tels procedes Withdrawn EP1346318A2 (fr)

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US727132 2000-11-29
US09/727,095 US20020101396A1 (en) 2000-04-14 2000-11-29 Balanced binary color drive method for graphical displays and system implementing same
US727095 2000-11-29
US09/727,132 US20020000967A1 (en) 2000-04-14 2000-11-29 System and method for digitally controlled waveform drive methods for graphical displays
PCT/US2001/044919 WO2002045016A2 (fr) 2000-11-29 2001-11-29 Procede de commande a couleur binaire equilibree et procedes de commande a forme d'onde regulee numeriquement pour des affichages graphiques et systeme mettant en oeuvre de tels procedes

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