EP1325547A2 - Systeme et procede de regulation de puissance hautement mis en phase au moyen d'un controle de compensation adaptif - Google Patents

Systeme et procede de regulation de puissance hautement mis en phase au moyen d'un controle de compensation adaptif

Info

Publication number
EP1325547A2
EP1325547A2 EP01981630A EP01981630A EP1325547A2 EP 1325547 A2 EP1325547 A2 EP 1325547A2 EP 01981630 A EP01981630 A EP 01981630A EP 01981630 A EP01981630 A EP 01981630A EP 1325547 A2 EP1325547 A2 EP 1325547A2
Authority
EP
European Patent Office
Prior art keywords
power
controller
voltage
load
regulation system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01981630A
Other languages
German (de)
English (en)
Inventor
Ryan Goodfellow
Malay Trivedi
Kevin Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Primarion Inc
Original Assignee
Primarion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Primarion Inc filed Critical Primarion Inc
Publication of EP1325547A2 publication Critical patent/EP1325547A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10—Parallel operation of dc sources
    • H02J1/102—Parallel operation of dc sources being switching converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/008—Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators

Definitions

  • the present invention relates generally to power regulation systems and, in particular, to a highly phased power regulation system. More particularly, the present invention relates generally to a highly phased power regulation system using a compensation mode.
  • Switching power converters are used to regulate the input voltage to a load. Often times, voltages are initially not suitable for a particular load (e.g., high AC) and must be downscaled (i.e., to a lower voltage) and/or converted (i.e., AC to DC rectified voltage) before applying to the load. In general, conventional SPC systems adequately provide voltage regulation to a load, however, there are drawbacks.
  • Slope compensation is often utilized in current mode power converters to stabilize the current loop.
  • Conventional current mode controlled converters operating above 50% duty cycle need a compensating ramp signal superimposed on a current sense signal, which is used as a control parameter, to avoid open loop instability, subharmonic oscillations, and noise sensitivity.
  • SPCs using current mode control typically include a pair of complex poles at half the regulator switching frequency and external ramp or slope compensation is added into the current loop in order to control the Q of these poles. In general, additional components are required to generate the fixed slope compensation in discrete applications. It is common to couple more than one load to a power regulation system. In these multi-load/multi-output configurations, SPCs have traditionally required a separate controller or transformer with post regulators for each of the outputs.
  • Each control unit requires compensating elements and support components which substantially increases the parts count for the converter. Additionally, in multi-output systems it is often desirable to include time synchronization to produce multi-phased outputs. These complex systems require precise management and control which, in general, the traditional purely analog converter systems cannot adequately manage. While transformers have shown some success in multi-output power conversion, these systems again typically require multiple controllers.
  • Microprocessor loads vary greatly in current and generally require a high di/dt load transient current.
  • the power conversion system must be able to sense the current or voltage droop in order to correct for the load demand.
  • Current sensing of the load is difficult and typically requires bulky, lossy and inaccurate methods.
  • Voltage sensing has the disadvantage of lagging the current in the load. Delays in both methods can lead to inadequate response of the SPC.
  • an improved power regulation system is needed.
  • a highly phased power regulation system having multi-mode capabilities over one or more loads is desired.
  • a versatile and adaptable power conversion and regulation system having an improved control feature is desired.
  • the present invention overcomes the problems outlined above and provides an improved power regulation system.
  • the present invention provides a power regulation system (power converter) with an improved control feature. More particularly, the system and methods of the present invention allow for independent control of one or more outputs from a single controlling unit.
  • a power regulation system of the present invention includes a plurality of power conversion blocks in a multi-phased configuration, a controller, and a communication channel coupled there-between. Digital information is received at the controller from the power blocks.
  • the controller includes an adaptive compensation algorithm which determines appropriate commands to be transmitted back to the power blocks. The controller may anticipate and predict forthcoming conditions and "set" the system into a predictive mode accordingly.
  • a highly phased power conversion system includes a proportional-integral-derivative (PID) compensation control method.
  • PID proportional-integral-derivative
  • Figures 1-3 illustrate, in block format, a power regulation system in accordance with various embodiments of the invention
  • Figure 4 illustrates, in block format, an exemplary power IC for use in a power regulation system of the present invention
  • FIG. 5 illustrates, in block format, a power regulation system in accordance with yet another embodiment of the invention
  • Figure 6 illustrates, in block format, a power regulation system having a compensation control feature in accordance with an embodiment of the invention.
  • Figure 7 illustrates an exemplary PID compensation block in accordance with the present invention.
  • the present invention relates to an improved power regulation system or power conversion system.
  • the power converter disclosed herein may be conveniently described with reference to a single or multiphase buck converter system, it should be appreciated and understood by one skilled in the art that any basic switching power converter (SPC) or regulator topology may be employed, e.g., buck, boost, buck-boost and flyback.
  • SPC switching power converter
  • regulator topology e.g., buck, boost, buck-boost and flyback.
  • FIG. 1 illustrates, in simplified block format, a power regulation system 100 in accordance with one embodiment of the invention.
  • System 100 includes a digital communication bus 101 , a controller 102 and a plurality of power blocks 104.
  • System 100 may be implemented in any basic SPC topology.
  • system 100 receives an input source voltage (VIN) and converts the voltage to a desired number of outputs, with each output at a desired voltage, in a highly efficient and reliable manner.
  • VIN input source voltage
  • System 100 is expandable to many phases (i.e., "N" number of phases), allowing many different load levels and voltage conversion ratios. As shown, system 100 includes "N" number of power blocks 104 which may be limited only by the capabilities of the controller. For instance, in one particular embodiment, system 100 is configured to include eight single-phase converters ("blocks" or “channels”). Alternatively, in another embodiment, system 100 is configured to include one eight- phase converter.
  • Controller 102 receives and sends information to power blocks 104 via digital bus 101 , or the equivalent.
  • the information communicated between the controller and the power blocks allows the system to precisely regulate the output voltage for any given load of the power block. In this manner, controller 102 independently controls multiple voltage outputs. This function will be described in further detail in the following description and accompanying Figures.
  • FIG. 2 illustrates, in block format, a power regulation system 200 in accordance with one embodiment of the invention.
  • System 200 includes a digital bus 101 , a controller 102, a plurality of power ICs 206, a plurality of output inductors 210, an output filter capacitance 225 and a load 220.
  • System 200 is configured as a multiphase buck converter system; however, as previously mentioned, system 200 may be configured as any basic switching power converter (SPC) topology.
  • SPC basic switching power converter
  • System 200 is suitably configured to output a single voltage (VOUT) to load
  • each power IC 206 is configured to provide an output to load 220 in accordance with a predetermined voltage.
  • power ICs 206 are configured to alternately couple inductors 210 between the source voltage and a ground potential (not shown) based on control signals generated by controller 102.
  • any number of output inductors 210 may be coupled simultaneously to either the voltage source or ground potential as needed by the load(s).
  • the inductance of inductor 210 can vary depending upon input and output requirements.
  • Capacitance 225 provides DC filtering of inductor currents and further acts as a charge well during load transient events.
  • each power IC 206 is preferably equally phased in time to minimize output ripple voltage to the load. Power ICs 206 share digital information between them and/or the controller such that each phase shares an equal part of the respective load current. Although each power IC 206 is illustrated as a stand-alone phase, each power IC may be implemented as any suitable number of distinct phases. The structural and functional aspects of power IC 206 are described in more detail below in Figure 4. Information relating to input/output characteristics of the power regulation system may be transmitted from various system elements to controller 102 in a suitable feedback loop. For example, controller 102 preferably receives digital information regarding mode of operation, output voltage, and output current from each power IC 206.
  • controller 102 sends switch state information, such as pulse width and frequency information, to each power IC 206 to, for example, compensate for the demands of the load, the voltage source, and any environmental changes in order to maintain a constant voltage to the load.
  • controller 102 may include a digital signal processor (DSP), a microprocessor or any suitable processing means.
  • DSP digital signal processor
  • controller 102 includes one or more algorithms to facilitate control of the system.
  • power ICs 206 are suitably configured to transmit input/output information to controller 102 and the algorithms are suitably adaptive to the received information. In other words, controller 102 may modify the control algorithms in response to the received information.
  • controller 102 may be programmed with recovery algorithms to effectively respond to sensed transient conditions at the regulated output. For example, in ATRH (active transient response high) and ATRL (active transient response low) modes, the controller includes instruction to align the high side or low side FETs on. This action provides a brief period of high di/dt through the power stage in order to respond to high di/dt load demands (e.g., a microprocessor load).
  • ATRH active transient response high
  • ATRL active transient response low
  • Each power IC 206 is suitably configured to operate in any suitable control mode such as, Pulse Width Modulation (PWM), constant ON time variable frequency, constant ON or OFF time and variable frequency, simultaneous phases ON, and simultaneous phases OFF.
  • controller 102 includes one or more algorithms for providing predictive control of the particular system. For example, a suitable algorithm may be programmed to recognize signs or receive signals indicating a high load, current, or similar situation. The controller may then be able to set the power regulation system to an operational mode best suited for the anticipated condition.
  • a current sharing feature of the power ICs is included.
  • the power ICs may receive substantially equally power from the voltage source or a varied voltage may be supplied to each.
  • a current feedback from each power IC to the controller may be included forming a synchronized share line to facilitate balancing the currents between the blocks or power ICs.
  • Figure 3 illustrates, in block format, a power regulation system 300 in accordance with another embodiment of the invention.
  • System 300 includes substantially the same system elements as system 200 (i.e., digital bus 101 and controller 102) except that system 300 includes a plurality of power ICs 306 and multiple loads 320-321. The operation of system 300 is substantially the same as previously described for systems 100 and 200 and thus will not repeated.
  • system 300 represents a multi-output/multi-load power regulation system.
  • power ICs 306 (labeled POWER IC 1 and POWER IC 2) are coupled to a single load 320 (labeled LOAD 1) and an output filter capacitance 326
  • power IC 306 (labeled POWER IC N) is coupled to a second load 321 (labeled LOAD N) and an output filter capacitance 325.
  • load 320 receives a voltage input which is a combined voltage from two power ICs (VOUT 1).
  • Controller 102 independently manages the operation of voltage input to multiple loads.
  • any number of power ICs may be coupled together to provide regulated voltage to one or more loads.
  • load 320 is shown receiving inputs from two power ICs, however this is not intended to be limited in any way.
  • FIG. 4 illustrates, in block format, a power IC 406 in accordance with one embodiment of the present invention.
  • Power IC 406 may be suitably implemented in a power regulation system of the present invention such as power IC 206,306, and is merely exemplary of one preferred embodiment.
  • the general function of power IC 406 has been described previously for power ICs 206 and 306 and thus will not repeated entirely again; however, the functions of the major individual components comprising power IC 406 will be described below.
  • Power IC 406 in general, includes an integrated circuit (IC) having multiple pins for facilitating suitable connections to and from the IC.
  • power IC 406 may include an integrated, P-channel high side switch 448 and driver 444 as well as a low side gate driver 444.
  • power IC 406 When used in conjunction with external N-FETs and an output inductor (e.g., inductor 210), power IC 406 forms a buck power stage. Power IC 406 is optimized for low voltage power conversion (e.g., 12 volts to approximately 1.8 volts and less) which is typically used in VRM ( voltage regulator module) applications. The present embodiment of power IC 406 has particular usefulness in microprocessor power applications. Power IC 406 includes a voltage sense block 429, a command interface 430, a current A/D 438, a non-overlap circuit 440, a gate drive 444, a switching element 448, and a current limiter 450. Additionally, power IC 406 may include a current sense 449, a zero current detector 442, and/or internal protection features, such as a thermal sensor 436 and various other features which will be discussed below.
  • VRM voltage regulator module
  • command interface 430 includes circuitry and the like to function as a "power IC controller.”
  • command interface 430 may include a portion of the controlling functions of controller 102 as "on-chip" features.
  • Command interface 430 provides a suitable interface for routing signals to and from power IC 406. For most of the components of power IC 406, information from the individual component is routed to the controller through command interface 430.
  • the information provided to the controller may include fault detection of a component or system, component or system updates, and any other pertinent information which may be used by the controller.
  • power IC 406 includes a fault register within command interface 430 which is polled by the controller.
  • Command interface 430 also receives information from the controller which is distributed to the individual components of power IC 406 as needed.
  • command interface 430 includes a serial bus interface.
  • the serial bus is preferably of the type to write data into and may be programmed by the system user. For example, each power IC may be set at a predetermined voltage output level as needed for the corresponding load. In addition, the user may set an absolute window for the output voltage. The predetermined set information may then be used by command interface 430 to send "commands" or set levels to various other components of the power IC.
  • the predetermined output voltage level may be provided from command interface 430 to voltage sense block 429 for configuring comparison levels (the functions of voltage sense block and its components will be described in more detail below).
  • Command interface 430 may also provide information to set "trip points" for current limiter 450 and optional temperature sensor 436.
  • Various other system components may also receive commands, information, set levels and so forth, from command interface 430.
  • the power regulation system of the present invention utilizes various feedback loops to regulate the output voltage and manage current within the power converter.
  • voltage sense block 429 is suitably configured to form a transient feedback loop.
  • voltage sense leads from the load furnish the feedback loop with the input voltage supplied to the load.
  • the components within the feedback loop or voltage sense block 429 perform comparisons and the like between the sensed voltage and a desired "set" voltage which is reported to command interface 430 and/or the controller.
  • Voltage sense block 429 generally includes a voltage A/D 424 and a window comparator 432.
  • voltage A/D 424 communicates to the controller a digital difference between the set voltage and the input voltage and window comparator 432 communicates to the controller whether the input voltage is varied (too high or too low) from the set voltage.
  • Voltage A/D 434 may comprise a variety of electrical components coupled together to cause a voltage analog-to-digital (A/D) configuration as is commonly known in the industry.
  • Voltage A/D 434 receives a constant reference voltage (not shown), a sample, or the equivalent, of the input voltage supplied to the load (via sense leads from the load), and the predetermined "set" voltage or desired output voltage from command interface 430.
  • the voltage A/D 434 is configured to compare the load voltage with the set voltage and generate a digital representation of the absolute difference (i.e., positive or negative), if any, between the two voltages. The difference is then transmitted to the controller via digital bus 101.
  • the transmission to the controller is a direct line, or pin connection; however, the transmission may be suitably routed through the command interface if needed.
  • the controller determines if the input voltage to the load is within an acceptable range and if not, may transmit a command to the power IC (e.g., to command interface 430) to adjust the set voltage.
  • a command to the power IC e.g., to command interface 430
  • sensed voltage from the load may be represented as a positive and a negative sensed voltage.
  • the sensed voltage may be filtered prior to receipt at the power IC.
  • Window comparator 432 preferably comprises a high speed, low offset comparator configuration commonly available in the electrical industry.
  • Window comparator 432 also receives the sensed voltage from the load in a similar manner as just described for voltage A/D 434 and receives the set voltage from voltage A D 434 or, alternatively, from command interface 430 directly. Window comparator 432 suitably compares the two received voltages and transmits a signal ATRH (active transient response high) to the controller indicating a "high" or “low” sensed voltage. For example, if the sensed or load voltage is lower than the set voltage, window comparator 432 may transmit an ATRH to the controller and in a like manner, if the sensed voltage is higher than the set voltage, window comparator 432 may transmit an ATRL (active transient response low) to the controller.
  • ATRH active transient response high
  • the set voltage may include an absolute window which may or may not be considered by the window comparator depending on the desired precision of the particular application.
  • the controller is suitably able to receive the ATR signals from window comparator 432 and either alone or in combination with the digital voltage and current information received, the controller may adjust the load voltage, set voltage, or other system components as needed to coordinate precise control of the output voltage.
  • Current A/D 438 may comprise a variety of electrical components coupled together to cause a current analog-to-digital (A/D) configuration as is commonly known in the industry.
  • Current A/D 438 senses a very small fraction (e.g., 1/10,000) of the input current through the high side power device and samples the voltage at the peak.
  • Current A/D 438 converts the sampled voltage to digital format and transmits the data to the controller.
  • the controller can determine the level of current in the sampled channel to preferably maintain current equilibrium between the two channels.
  • Current limiter 450 essentially comprises another comparator block having electrical components coupled together to cause a comparing structure and function.
  • current limiter 450 also receives a small fraction of the current from the source and compares the current levels between the source voltage and a reference. At a threshold level (which may include a set percentage of the peak channel current), current limiter 450 sends a signal to mode gating logic 444 which effectively turns a "high side" driver off.
  • the current information is passed to the controller digitally via command interface 430. The controller may assess whether all or just a few channels were in current limit across a given fault polling cycle.
  • Isolated, single channel current limit events may be ignored, but if the current limit is detected for a number of consecutive fault polling cycles, the controller may cease PWM to that channel and re-phase the system. If the controller detects that all or substantially all of the power ICs within the system are in current limit, then the system may be sent to the OFF state.
  • Gate drive 444 comprises system level logic to drive power IC 406 either high or low. For example, a pair of driver amplifiers or any suitable gain devices may be included. Switching element 448 receives a signal from gate drive 444 which couples the output inductor to the input source or ground. In this sense, switching element 448 may include any suitable electrical device capable of performing a switching function such as, a bipolar transistor (BJT), field effect transistor (FET), metal oxide semiconductor (MOS, either N or P) and the like.
  • BJT bipolar transistor
  • FET field effect transistor
  • MOS metal oxide semiconductor
  • Non-overlap circuitry 440 prevents the high and low side drivers of mode gating logic 444 from conducting current simultaneously and may include logic gates and/or voltage comparators. Although not illustrated, it should be appreciated that non-overlap circuitry 440 may receive a high side signal (e.g., PWM) and a low side signal which may be utilized to implement various modes of operation. As previously mentioned, the system is uniquely versatile in that it can be operated in virtually any control mode of operation desired. Each mode of operation has advantages for control of the output voltage depending on the respective load demands. For example, in one embodiment a power regulation system of the present invention may be operated in continuous conduction mode (CCM) with external synchronous power FETs in continuous conduction regardless of the load current.
  • CCM continuous conduction mode
  • negative current may be allowed to flow in the main inductor during light loads.
  • the standard PWM control may be performed via an input to non-overlap circuitry 440.
  • the system may be operated in discontinuous conduction mode (DCM) with the external synchronous power FETs turned off when the current reaches zero. In other words, a negative current may not be allowed to flow in the main inductor during light loads.
  • DCM discontinuous conduction mode
  • the controller controls the OFF time of the low side switch in response to the ZCD signal.
  • a power regulation system of the present invention includes a current sense mechanism 449.
  • Current sense 449 detects the level of current by mirroring the level to an op amp. Identifying the input current levels can provide additional fault protection, help to monitor the power regulation, and other advantages to the system which may be best understood by referencing U.S. Patent
  • a power regulation system of the present invention includes a zero current detect circuit (ZCD) 442.
  • ZCD 442 detects when switching element 448 is low or effectively is switched to ground. In this sense, when a substantially zero current is detected, the operation of the system may be changed such that inefficiencies (e.g., due to high RMS currents) are minimized. Additionally, the system is able to respond more rapidly to low-to-high load transitions, resulting in less variations in the regulated output voltage.
  • ZCD 442 may transmit notification of the zero current state directly to the controller via digital bus 101 or, alternatively, may supply the notice to command interface 430 for reporting to the controller.
  • the detailed operation, structure and function of a suitable zero current detect may be best understood by referencing U.S. Patent Application Serial No. , filed on October , 2001 and entitled "System And Method For Detection Of
  • a power regulation system of the present invention includes one or more internal protection features.
  • power IC 406 includes a temperature sensor 436.
  • Temperature sensor 436 may be, but is not limited to, an integrated solid state current modulating sensor or a thermistor. Temperature sensor 436 monitors the temperature of power IC 406 and periodically reports temperature readings to command interface 430. As previously discussed, command interface 430 preferably sets the temperature trip levels, high and low boundaries, and determines if the reading received from sensor 436 is outside the boundaries.
  • command interface 430 notifies the controller and in some situations, the controller may cease PWM to that channel and re-phase the system.
  • another internal protection feature in power IC 406 is an under-voltage/over-voltage (UV/OV) protection mechanism (not shown).
  • An input voltage protection comparator may be present in each power IC to protect the system from operating outside normal thermal and stability boundaries. The comparator senses the voltage across an input capacitor (not shown) to the VRM and if the input voltage lies outside a trigger level, the controller may pause the system.
  • an output UV/OV protection may be included (not shown) in a power regulation system of the present invention.
  • One of the power ICs in the system may be assigned to UV/OV protection and suitably include a comparator for this purpose.
  • the comparator senses the output voltage to ensure the voltage is within the safe operating range of the receiving load.
  • the controller detects the condition through the command interface 430 and may transmit an OFF state to the system.
  • a power regulation system of the present invention includes a soft start mechanism to regulate the power-on voltage rise of the load. At the time of power-on, the system charges rapidly from its rest state to on-state so that it may provide the required load current at the set voltage level.
  • a soft start mechanism provides yet another internal protection feature which prevents false failures and/or damage during initial power-on.
  • controller 102 coordinates identification (ID) and phase assignment of the power ICs in the system.
  • the controller may use PWM inputs and ZCD outputs to coordinate the ID assignment sequence.
  • the controller tracks the number of power ICs available in the system by setting an internal time limit (e.g., 1 ms) for all power ICs to issue a ZCD high following a power-on reset. Active high on the ZCD pin indicates that the power IC is ready to receive an address and be counted in the system.
  • the controller responds by setting the power IC in an "ID acquire” mode and pulls the PWM input to the power IC high.
  • the ID is sent to the power IC and verified through the command interface.
  • PWM is asserted low and the power IC is ready for active operation.
  • the power ICs may be assigned IDs with or without VCC present, but in the latter case, an under-voltage fault may be registered.
  • the controller will not assert PWM signals to the systems until the power ICs are counted and assigned IDs, and the fault registers within the system have been checked.
  • controller 102 preferably manages the removal of damaged power ICs and the re-phasing of operational power ICs during a fault. In this manner, controller 102 recognizes the fault and makes the decision to remove an individual power IC from the system or, alternatively, shut down the system.
  • the controller 102 supports power IC identification to make the system scalable and addressing enables channel dropping and re-phasing for certain failure modes.
  • the address of each power IC in the system is suitably communicated through command interface 430. The controller uses the available number to determine the relative phase relationship between the power IC channels.
  • a clean clock may be received at command interface 430
  • a start-of-conversion signal may be received at voltage A/D 434 to initiate the A/D
  • a clock generated by, for example, an off- chip crystal oscillator, may be received at a pin on the chip as is common in electrical chip configurations.
  • Figure 5 illustrates, in block format, a power regulation system 500 in accordance with yet another embodiment of the present invention.
  • System 500 includes a backplane 501 , a microprocessor 502, a plurality of power blocks 506, an output filter capacitance 225, and a plurality of peripherals 520, 521.
  • the present embodiment of the invention (as well as various other embodiments) is configured to adapt to multi-modes of operation, which advantageously permits the system to optimize the mode of operation to suit the demands of the individual load(s).
  • the present invention may be particularly suited to power high-current low-voltage loads, such as microprocessors, and thus the present embodiment may be conveniently described in that context. It should be appreciated that this is only one particular embodiment and is not intended to be limiting on the scope of the invention.
  • the previously described embodiments may suitably include some or all of the following elements, in particular, the previous embodiments may include a microprocessor load.
  • Backplane 501 is preferably a multifunctional digital backplane such as an optical backplane or the like, that facilitates data transmission between microprocessor 502, power blocks 506 and peripheral devices 520, 521.
  • voltage regulation control algorithms may be transferred from microprocessor 502 to any or all of the power ICs within each power block 506 via backplane 501. Power is transferred through power blocks 506 to microprocessor 502 and peripherals 520, 521.
  • Microprocessor 502 may be similar to controller 102, however, this particular embodiment is especially suited for a microprocessor controller.
  • the microprocessor may be itself a load of the system and thus provide feedback on its own operation. In this manner, the microprocessor receives input from various other system components, such as the power ICs, peripherals, other loads, as well as data relating to its own processes.
  • a suitable algorithm within the microprocessor may be programmed to compile, sort and compute the received data to determine the "state" of the overall system. For example, during pre-periods of high load, high current, or various other situations, the microprocessor could suitably anticipate and predict the forthcoming situation by analyzing the "warning" signals or precursor data.
  • Power blocks 506 are similar in structure and function as previously described power blocks 104, power ICs 206, 306 and 406. Of course, in this particular embodiment, the power ICs may send and receive data via backplane 501 and/or digital bus 101.
  • Peripherals 520, 521 may be internal or external interfaces to electrical equipment coupled to the power regulation system. For example, interfaces to monitors, printers, speakers, networks and other equipment may be coupled to the system via backplane 501.
  • FIG. 6 illustrates, in simplified block format, a power regulation system 600 having an exemplary compensation control in accordance with one embodiment of the invention.
  • Power regulation system 600 is similar to the previously described power regulation systems (e.g., systems 100-300 and 500) except that system 600 includes a compensation control feature.
  • System 600 includes a plurality of power ICs 606, a plurality of output inductors 210, a plurality of loads 320, 321 , a digital bus 101 , and a controller 602. It should be noted that like reference numerals represent similar elements throughout the Figures.
  • each power IC 606 transmits a digital representation of the voltage error (V err ) determined by the power IC and the channel current (l ou t) from the power IC.
  • the voltage error is the absolute difference, as determined by the voltage sense block (e.g., voltage sense block 429 and voltage A/D 434), between the sensed output (load) voltage and the set voltage.
  • a digital representation of the difference (V err ) is communicated to controller 602 via digital bus 101. In this manner, each power IC (1 thru N) determines a voltage error and transmits the difference, if any, to the controller.
  • Each power IC 606 also transmits a digital representation of the current (or the equivalent) (l ou .) in the sampled channel of the power IC to controller 602. It should be recognized that various other inputs and outputs to the power ICs occur, although not illustrated for purposes of this embodiment. Controller 602 is similar in function as the previously discussed controllers
  • Controller 602 includes a compensation control feature which broadly includes a compensator block 630, a gain/phase detector 635, a signal generator 640, and a PWM generator 650. There are numerous methods of compensation which are suitably adaptive to control systems such as power regulation system 600.
  • the transfer function is: ⁇ (c) - c s) - G -W ⁇ S ) R(s) l + G c (s)G p ( S )H(s) where: R(s) equals the input and C(s) equals the output.
  • the plant is the system to be controlled and the compensator provides the excitation for the plant.
  • the compensator transfer function is designed to give the closed-loop system certain specified advantageous characteristics.
  • the compensator can be designed to improve the transient response. Increasing the speed of response is generally accomplished by increasing the open-loop gain at higher frequencies such that the system bandwidth is increased. Reducing overshoot (ringing) in the response generally involves increasing the phase margin of the system, which tends to remove any resonance in the system. The phase margin of the system determines the transient response, output impedance and other performance characteristics of the SPC (switching power converter). A trade-off typically exists between the beneficial effects of increasing the open loop gain and the resulting effects of reducing the stability margins. Hence, increasing the relative stability tends to increase phase and gain margins and generally decrease the overshoot in the system response.
  • the compensator can also be designed to reduce the steady-state error.
  • Steady-state errors are typically decreased by increasing the open-loop gain in the frequency range of the errors.
  • Low frequency errors are typically reduced by increasing the low frequency open loop gain and by increasing the type number of the system (the number of poles at the origin in the open loop function.
  • Compensator block 630 receives the voltage error and channel currents from the individual power ICs 606. This data is used to optimize the compensator transfer function as needed to regulate the output voltage to the load(s) and provide stability to the system.
  • Output voltage regulation typically involves minimizing the voltage error (i.e., reducing the absolute difference between the sensed (load) voltage and the set voltage) and providing active voltage positioning based on the load level.
  • a start-up control loop including gain/phase detector 635 and signal generator 640 is engaged.
  • the data input to compensator block 630 is also received at gain/phase detector 635 where the gain and phase of the output voltage may be determined.
  • Signal generator 640 provides a constant reference, such as a sinusoidal waveform, to gain/phase detector 635.
  • the overall gain of the plant transfer function may be determined by equating the ratio of the absolute magnitude of a feedback signal with respect to the sinusoidal signal. The following equation exemplifies a suitable gain equation:
  • fb is the feedback signal and ref is the injected sinusoidal signal.
  • ref is the injected sinusoidal signal.
  • the start-up control loop is used to optimize the initial compensator transfer function and then the start-up loop may be disengaged until subsequent start-ups occur.
  • PWM generator 650 receives the initial instruction, such as from the start-up control loop, or the compensated instruction and in response, generates a digital signal to the power ICs. It should be noted that controller 602 provides digital instructions to more than one power IC and, in fact, controller 602 may provide instructions to all the power ICs in the system.
  • a power regulation system in accordance with the present invention includes a controller 602 for operating the system in current mode control.
  • Algorithms contained within controller 602 suitably implement adaptive slope compensation to optimize system performance.
  • the slope compensation may be calculated to vary optimally as a function of the load.
  • the current A/D e.g., current A/D 438, provides information to controller 602 in a format that can be suitably multiplied by a gain term to provide adaptive slope compensation.
  • the sensed analog current signal is transmitted to the controller logic.
  • a variable multiplier is then used to increase the sensed current signal.
  • the gain term may be programmed to vary as a function of load or variances resulting from other external components (e.g., output filter).
  • FIG. 7 illustrates, in simplified block format, a compensator block 730 for use in controller 602 in accordance with one embodiment of a power regulation system of the present invention.
  • Compensator block 730 represents an exemplary proportional-integral-derivative (PID) compensator control loop.
  • PID controller may be represented as:
  • Equation 5 K p + ⁇ A-K d s (5) s
  • K p is the proportional gain
  • K ⁇ is the integral gain
  • K d is the derivative gain.
  • the coefficients of the terms of Equation 5 may be determined on the basis of the plant transfer function, for example, as derived using Equations 3 and 4 above.
  • the net error input to compensator block 730 is the sum of the V err and l out inputs.
  • the voltage error for each power IC is received at the compensator block and the sum of all the total currents output by the power ICs (ILOAD) is received at the block.
  • the individual l ou t from each of the power ICs is summed together to determine the total current output to the load (IL O AD)-
  • the load current (IL O AD) and voltage error are then summed to determine the error signal (e).
  • the error signal is passed through a proportional gain (K p ) and an integral gain (Kj) path and offset by differential gain (K d ) to generate the output (y(n)).
  • the digital output (y(n)) at any time (ri) is a function of the present digital input (x(n)) and the previous digital output (y(n-1)).
  • the output of compensator block 730 is the sum of Equations 6 and 7.
  • the proportional controller (K p ) has the effect of reducing the rise time and will reduce, but not eliminate, the steady-state error.
  • the integral controller (Kj) has the effect of reducing, even eliminating, the steady-state error.
  • a load step is typically followed by a steep change in the V err and t inputs.
  • the PI compensator stages are unable to respond immediately to the change and usually takes some time to adjust to the new load conditions.
  • the derivative term (D) is used and may be represented as:
  • a high derivative term may have an adverse influence on steady- state performance. It is preferably to shift the compensator output to the new value corresponding to the load condition. Such a scheme bypasses the ramping time of the PI block and retains the steady-state stability provided by the PI block.
  • Figure 7 illustrates this offset preferred response.
  • the differential gain (K d ) is assigned to the l out signal such that the compensator output is substantially instantaneously shifted by an amount proportional to the change in the load (or other effects resulting in a change in the compensator inputs). In this manner, the differential offset may be active only when there is a change in the load current.
  • the PI block resumes when the load current achieves the new compensated value.
  • This adaptive control feature allows compensator block 730 to rapidly adjust the compensator output to attain a new steady-state condition after a load step.
  • K d residual differential term
  • Compensator block 730 accounts for this by adaptively adjusting the value of K d depending on the load activity.
  • a high K value may be used during a load step and the value may be progressively reduced to the steady-state residual level as the load activity lessens.
  • This adaptive digital control on the compensation system greatly enhances the transient response of the power regulation system without jeopardizing the steady-state response.
  • the controller can rapidly change the output of the compensator by utilizing the sensed load current.
  • the output of the compensator is offset by an amount proportional to the change in the sensed load current.
  • the gain of the difference stage (K d ) changes adaptively with the sensed current to provide a bigger offset for large load steps. This allows the compensator to quickly arrive at the output signal corresponding to the new load current, thus reducing the time required by conventional compensators to reach steady state.
  • an algorithm to adaptively compensate for varying loads utilizes a calibration procedure to provide information to the controller, such as the characteristics of the output inductors, output capacitors and the load(s).
  • This calibration procedure involves injecting a sweeping frequency sinusoidal waveform into the portion of the controller that computes the PWM duty ratio.
  • the feedback voltage and individual inductor current signals are input into the digital feedback loop where the signals are analyzed to determine the residual amount of the injected sinusoid.
  • the value of K p is such that it raises the low- frequency flat-band gain to 20 dB and the value of Kj, which determines the low- frequency gain of the system, is such that the overall loop gain is 20 dB about an octave below the 3 dB frequency of the original plant transfer function.
  • the parameter K d influences the high-frequency response of the system and determines the gain crossover frequency of the loop transfer function.
  • An iterative algorithm is used to incrementally adjust the Kd compensation to maximize the gain crossover frequency and the phase margin.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Supply And Distribution Of Alternating Current (AREA)
  • Control Of Voltage And Current In General (AREA)

Abstract

L'invention concerne un système (convertisseur) de régulation de puissance hautement mis en phase à fonction de contrôle améliorée. Un régulateur, tel qu'un processeur ou un microprocesseur de signaux numériques reçoit des informations numériques provenant de plusieurs blocs de conversion de puissance et transmet ces commandes de contrôle en réponse aux informations. Ce régulateur permet de changer le mode de fonctionnement du système et/ou de remettre en phase les blocs de puissance afin de s'adapter à une exigence de charge dynamique, à des occasions de réponse transitoire élevée ou à une détection d'erreur. Un bloc de compensation situé à l'intérieur du régulateur est utilisé en vue de réguler la tension de sortie et de rendre stable le système. Dans l'un des modes de réalisation de l'invention, le régulateur est mis en oeuvre en tant que régulateur PID compensateur. Dans un autre mode de réalisation, un microprocesseur permet de recevoir une rétroaction sur son propre fonctionnement, permettant ainsi au régulateur d'anticiper et de prévoir des états par analyse de données précurseurs.
EP01981630A 2000-10-13 2001-10-15 Systeme et procede de regulation de puissance hautement mis en phase au moyen d'un controle de compensation adaptif Withdrawn EP1325547A2 (fr)

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US24033700P 2000-10-13 2000-10-13
US240337P 2000-10-13
US97519501A 2001-10-10 2001-10-10
US975195 2001-10-10
PCT/US2001/032263 WO2002031951A2 (fr) 2000-10-13 2001-10-15 Systeme et procede de regulation de puissance hautement mis en phase au moyen d'un controle de compensation adaptif

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107703352A (zh) * 2016-09-13 2018-02-16 郑州云海信息技术有限公司 一种基于Openpower平台的功耗监控方法及系统

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6977492B2 (en) * 2002-07-10 2005-12-20 Marvell World Trade Ltd. Output regulator
EP1524572B1 (fr) * 2002-07-10 2011-12-28 Marvell World Trade Ltd. Circuit convertisseur de puissance et procédé
US7049798B2 (en) 2002-11-13 2006-05-23 Power-One, Inc. System and method for communicating with a voltage regulator
US7456617B2 (en) * 2002-11-13 2008-11-25 Power-One, Inc. System for controlling and monitoring an array of point-of-load regulators by a host
US6906502B2 (en) 2002-11-14 2005-06-14 Fyre Storm, Inc. Method for regulating an output voltage of a power coverter
US6911809B2 (en) * 2002-11-14 2005-06-28 Fyre Storm, Inc. Switching power supply controller
US6833691B2 (en) 2002-11-19 2004-12-21 Power-One Limited System and method for providing digital pulse width modulation
US7373527B2 (en) * 2002-12-23 2008-05-13 Power-One, Inc. System and method for interleaving point-of-load regulators
US7023190B2 (en) 2003-02-10 2006-04-04 Power-One, Inc. ADC transfer function providing improved dynamic regulation in a switched mode power supply
US6936999B2 (en) * 2003-03-14 2005-08-30 Power-One Limited System and method for controlling output-timing parameters of power converters
US7080265B2 (en) 2003-03-14 2006-07-18 Power-One, Inc. Voltage set point control scheme
US7454643B2 (en) 2003-04-30 2008-11-18 Marvell World Trade Ltd. Pre-emptive power supply control system and method
US7135789B2 (en) * 2003-05-12 2006-11-14 Potentia Semiconductor, Inc. Controlling devices using cascaded control units
US7446435B2 (en) 2005-11-30 2008-11-04 General Electric Company Power converter system and method
US7956592B2 (en) * 2008-06-13 2011-06-07 The Regents Of The University Of Colorado Monitoring and control of power converters
JP5317127B2 (ja) * 2010-04-23 2013-10-16 ルネサスエレクトロニクス株式会社 半導体装置
US9466980B2 (en) 2010-11-22 2016-10-11 Saab Ab Power arrangement for preventing circulating loop currents within the arrangement
JP2012122879A (ja) 2010-12-09 2012-06-28 Advantest Corp 電源装置、その制御方法ならびにそれらを用いた試験装置
JP5559724B2 (ja) * 2011-02-24 2014-07-23 株式会社アドバンテスト 試験装置用の電源装置およびそれを用いた試験装置
JP6382065B2 (ja) * 2014-10-24 2018-08-29 ローム株式会社 Ｕｓｂ給電装置、それを用いた電子機器、ｕｓｂ給電装置の制御方法
CN106707740A (zh) * 2017-03-09 2017-05-24 西安电子科技大学 基于积分分离pid的数字电源环路补偿器的设计方法
GB2568664B (en) * 2017-11-15 2020-09-16 Sensiotech Ltd A power converting arrangement and a method for converting power

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100676A (en) * 1998-10-30 2000-08-08 Volterra Semiconductor Corporation Method and apparatus for digital voltage regulation

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0231951A2 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107703352A (zh) * 2016-09-13 2018-02-16 郑州云海信息技术有限公司 一种基于Openpower平台的功耗监控方法及系统
CN107703352B (zh) * 2016-09-13 2020-08-21 苏州浪潮智能科技有限公司 一种基于Openpower平台的功耗监控方法及系统

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AU2002213260A1 (en) 2002-04-22

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