EP1321843A1 - Current source circuit - Google Patents
Current source circuit Download PDFInfo
- Publication number
- EP1321843A1 EP1321843A1 EP02102824A EP02102824A EP1321843A1 EP 1321843 A1 EP1321843 A1 EP 1321843A1 EP 02102824 A EP02102824 A EP 02102824A EP 02102824 A EP02102824 A EP 02102824A EP 1321843 A1 EP1321843 A1 EP 1321843A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- mos field
- effect transistor
- field effect
- output
- current source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
Definitions
- the invention relates to a current source circuit in which a first and a second MOS field effect transistor form a current mirror circuit, the first MOS field effect transistor via a third MOS field-effect transistor connected in cascode a reference current can be supplied and the drain electrode with the second MOS field-effect transistor fourth MOS field-effect transistor connected in cascode has an output forms.
- a simple current mirror circuit consists of two transistors, in particular MOS field-effect transistors, whose source and gate electrodes are connected to each other are. Furthermore, the gate electrode and the drain electrode of the one transistor are together connected and are acted upon by a reference current. The drain electrode of the other MOS field effect transistor can then the desired output current be removed. However, this is different from that on the other MOS field-effect transistor following also called output transistor - depending on the applied voltage, since its Parameters are voltage dependent.
- the object of the invention is to provide a current source circuit which is large Output voltage range has a high output impedance.
- This object is achieved in that the source electrodes of the third and the fourth MOS field effect transistor connected to inputs of a control amplifier are, the output with the gate electrode of the fourth MOS field effect transistor is connected that the fourth MOS field effect transistor is an extended drain MOS field effect transistor and that the drain electrode and the gate electrode of the fourth MOS field effect transistor connected to one another via a further MOS field effect transistor are whose gate electrode is supplied with an operating voltage for the circuit is.
- an embodiment of the invention is particularly advantageous, that the extended drain MOS field effect transistor is an extended drain n well MOS field effect transistor and that the further MOS field-effect transistor is a p-channel MOS field-effect transistor is.
- the current source circuit according to the invention has the advantage of a high output impedance over a very wide output voltage range, with the output voltage may exceed the operating voltage allowed for this technology. To reach these properties are no additional mask steps for special high-voltage transistors needed. Furthermore, the current source circuit according to the invention can also be operated at an output voltage that is higher than the operating voltage of the rest Circuit is. In addition, the current source circuit according to the invention has a high accuracy of the current mirror ratio in the operating voltage, output voltage and temperature range.
- the current source circuit according to the invention serves as a current mirror when the reference current is fed from the outside.
- the invention provides Power source switching is also a highly accurate power source.
- the current source circuit according to the invention has the advantage that, in contrast to other known circuits is not destroyed if one at the output transistor Voltage is present while the circuit itself, i.e. the control amplifier and others Circuit elements are not yet supplied with an operating voltage.
- the current source circuit according to the invention has the advantage that it is highly integrated Standard CMOS technologies can be used. By avoiding the hot carrier effect at high output voltages, the lifespan of the power source circuit also increases.
- Another advantageous embodiment is designed such that the output of the control amplifier via a resistor to the gate electrode of the fourth MOS field effect transistor is connected, wherein it is preferably provided that the control amplifier is formed by an operational transconductance amplifier.
- Extended-drain MOS field-effect transistors which are also lightly doped drain n-well transistors or lightly doped drift region transistor are described, for example in: Y.Q. Li, C.A.T. Salama, M. Seufert, M. King “Submicron BiCMOS compatible highvoltage MOS transistors ", ISPSD Proc., 1994, pp. 355-359.
- the transistors are designed as n-channel MOS field-effect transistors.
- a first MOS field effect transistor 1 and a second MOS field effect transistor 2 represents the actual current mirror, to which a reference current Iin is fed via an input 5 can be.
- a current mirror circuit is known per se and needs context not to be explained in more detail with the present invention. However, it is briefly mentioned that the current Iout that can be taken from the output 6 in one pass Transistor geometries certain ratio to the reference current Iin is.
- the MOS field-effect transistor 4 hereinafter also referred to as the output transistor.
- an OTA (operational transconductance amplifier) 7 the two source voltages of the cascode transistors 3, 4 compared with each other, whereby a control signal arises, which is fed via a resistor 8 to the gate electrode of the output transistor 4 becomes.
- a MOS field effect transistor is used to dampen the tendency to oscillate in the control loop 9 connected as a capacitance between the output of the OTA 7 and ground potential.
- the n-well drift region achieves a long service life up to the maximum output voltage.
- a gate oxide breakdown is achieved under all conditions by the transistor combination 10, 11, 12 prevented.
- Embodiment protects the series circuit from a p-channel MOS field effect transistor 10 and the two n- or p-channel MOS field-effect transistors connected as diodes 11 and 12 the output transistor 4 in the event that a voltage at the output 6 is already present, while the operating voltage supplied at 13 is not (yet) present is.
- the transistor 10 receives 0V as the gate potential and switches via the MOS field-effect transistors 11, 12 the gate-drain voltage of the output transistor 4 a value that is below the gate oxide breakdown voltage.
- the resistance serves 8 for decoupling the OTA output. After starting the operating voltage at 13 the MOS field-effect transistor 10 switches off, so that the function of the cascode control is no longer influenced.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
Die Erfindung betrifft eine Stromquellenschaltung, bei welcher ein erster und ein zweiter MOS-Feldeffekttransistor eine Stromspiegelschaltung bilden, wobei dem ersten MOS-Feldeffekttransistor über einen in Kaskode geschalteten dritten MOS-Feldeffekttransistor ein Referenzstrom zuführbar ist und die Drain-Elektrode eines mit dem zweiten MOS-Feldeffekttransistor in Kaskode geschalteten vierten MOS-Feldeffekttransistors einen Ausgang bildet.The invention relates to a current source circuit in which a first and a second MOS field effect transistor form a current mirror circuit, the first MOS field effect transistor via a third MOS field-effect transistor connected in cascode a reference current can be supplied and the drain electrode with the second MOS field-effect transistor fourth MOS field-effect transistor connected in cascode has an output forms.
Für verschiedene schaltungstechnische Zwecke werden Stromquellen benötigt, die eine möglichst hohe Ausgangsimpedanz aufweisen sollten. Je höher die Ausgangsimpedanz, desto geringer ist die Abhängigkeit des Ausgangsstroms von der anliegenden Spannung.Current sources, one of which are required for various circuit-related purposes should have the highest possible output impedance. The higher the output impedance, the less the dependency of the output current on the applied voltage.
Eine einfache Stromspiegelschaltung besteht aus zwei Transistoren, insbesondere MOS-Feldeffekttransistoren, deren Source- und Gate-Elektroden jeweils miteinander verbunden sind. Ferner sind die Gate-Elektrode und die Drain-Elektrode des einen Transistors miteinander verbunden und werden von einem Referenzstrom beaufschlagt. Der Drain-Elektrode des anderen MOS-Feldeffekttransistors kann dann der gewünschte Ausgangsstrom entnommen werden. Dieser ist jedoch von der am anderen MOS-Feldeffekttransistor - im folgenden auch Ausgangstransistor genannt - anliegenden Spannung abhängig, da dessen Parameter spannungsabhängig sind.A simple current mirror circuit consists of two transistors, in particular MOS field-effect transistors, whose source and gate electrodes are connected to each other are. Furthermore, the gate electrode and the drain electrode of the one transistor are together connected and are acted upon by a reference current. The drain electrode of the other MOS field effect transistor can then the desired output current be removed. However, this is different from that on the other MOS field-effect transistor following also called output transistor - depending on the applied voltage, since its Parameters are voltage dependent.
Eine Verminderung dieser Abhängigkeiten ist mit Kaskode-Schaltungen möglich, wie sie beispielsweise in US 5,844,434 dargestellt sind. Zur weiteren Stabilisierung des Stroms ist es beispielsweise aus JP 0060061859 AA bekanntgeworden, die Source-Elektrode des Ausgangstransistors durch Steuerung der Gate-Elektrode auf konstantes Potential zu regeln. Damit wird die Ausgangsimpedanz gegenüber einer einfachen Kaskode-Schaltung um die Schleifenverstärkung erhöht. A reduction of these dependencies is possible with cascode circuits as they do are shown for example in US 5,844,434. To further stabilize the current is it has become known, for example, from JP 0060061859 AA, the source electrode of the output transistor to regulate to constant potential by controlling the gate electrode. Thus, the output impedance compared to a simple cascode circuit Loop gain increased.
Diese hohe Ausgangsimpedanz steht bei Realisierung in einem Sub-micron-Prozess jedoch nur in einem begrenzten Ausgangsspannungsbereich zur Verfügung. Bei höheren Ausgangsspannungen fließt aufgrund des Hot-carrier-Effekts ein Substratstrom direkt vom Drain des Kaskode-Transistors zum Substrat. Dieser Substratstrom wird durch die Regelung nicht beeinflußt und führt zu einer drastischen Verringerung der Ausgangsimpedanz. Selbst durch höhere Kanallänge des Ausgangstransistors läßt sich die Reduktion der Ausgangsimpedanz nur geringfügig kompensieren.However, this high output impedance is realized in a sub-micron process only available in a limited output voltage range. At higher output voltages due to the hot carrier effect, a substrate current flows directly from the Drain the cascode transistor to the substrate. This flow of substrate is controlled unaffected and drastically reduces output impedance. The output impedance can be reduced even by increasing the length of the output transistor compensate only slightly.
Aufgabe der Erfindung ist es, eine Stromquellenschaltung anzugeben, die in einem großen Ausgangsspannungsbereich eine hohe Ausgangsimpedanz aufweist.The object of the invention is to provide a current source circuit which is large Output voltage range has a high output impedance.
Diese Aufgabe wird erfindungsgemäß dadurch gelöst, dass die Source-Elektroden des dritten und des vierten MOS-Feldeffekttransistors an Eingänge eines Regelverstärkers angeschlossen sind, dessen Ausgang mit der Gate-Elektrode des vierten MOS-Feldeffekttransistors verbunden ist, dass der vierte MOS-Feldeffekttransistor ein Extended-drain-MOS-Feldeffekttransistor ist und dass die Drain-Elektrode und die Gate-Elektrode des vierten MOS-Feldeffekttransistors über einen weiteren MOS-Feldeffekttransistor miteinander verbunden sind, dessen Gate-Elektrode mit einer Betriebsspannung für die Schaltung beaufschlagt ist.This object is achieved in that the source electrodes of the third and the fourth MOS field effect transistor connected to inputs of a control amplifier are, the output with the gate electrode of the fourth MOS field effect transistor is connected that the fourth MOS field effect transistor is an extended drain MOS field effect transistor and that the drain electrode and the gate electrode of the fourth MOS field effect transistor connected to one another via a further MOS field effect transistor are whose gate electrode is supplied with an operating voltage for the circuit is.
Da die eingangs genannten Probleme bei n-Kanal-MOS-Feldeffekttransistoren wesentlich gravierender auftreten, ist eine Ausgestaltung der Erfindung derart besonders vorteilhaft, dass der Extended-drain-MOS-Feldeffekttransistor ein Extended-drain-n-well-MOS-Feldeffekttransistor ist und dass der weitere MOS-Feldeffekttransistor ein p-Kanal-MOS-Feldeffekttransistor ist.Since the problems mentioned at the beginning with n-channel MOS field-effect transistors are essential occur more seriously, an embodiment of the invention is particularly advantageous, that the extended drain MOS field effect transistor is an extended drain n well MOS field effect transistor and that the further MOS field-effect transistor is a p-channel MOS field-effect transistor is.
Die erfindungsgemäße Stromquellenschaltung weist den Vorteil einer hohen Ausgangsimpedanz über einen sehr großen Ausgangsspannungsbereich auf, wobei die Ausgangsspannung die für diese Technologie zulässige Betriebsspannung überschreiten kann. Zum Erreichen dieser Eigenschaften werden keine zusätzlichen Maskenschritte für spezielle Hochvolttransistoren benötigt. Ferner kann die erfindungsgemäße Stromquellenschaltung auch bei einer Ausgangsspannung betrieben werden, die höher als die Betriebsspannung der übrigen Schaltung ist. Außerdem weist die erfindungsgemäße Stromquellenschaltung eine hohe Genauigkeit des Stromspiegelverhältnisses im Betriebsspannungs-, Ausgangsspannungs- und Temperaturbereich auf.The current source circuit according to the invention has the advantage of a high output impedance over a very wide output voltage range, with the output voltage may exceed the operating voltage allowed for this technology. To reach these properties are no additional mask steps for special high-voltage transistors needed. Furthermore, the current source circuit according to the invention can also be operated at an output voltage that is higher than the operating voltage of the rest Circuit is. In addition, the current source circuit according to the invention has a high accuracy of the current mirror ratio in the operating voltage, output voltage and temperature range.
Die erfindungsgemäße Stromquellenschaltung dient als Stromspiegel, wenn der Referenzstrom von außen zugeführt wird. Mit einer internen Referenzstromquelle stellt die erfindungsgemäße Stromquellenschaltung auch eine hochgenaue Stromquelle dar.The current source circuit according to the invention serves as a current mirror when the reference current is fed from the outside. With an internal reference current source, the invention provides Power source switching is also a highly accurate power source.
Neben der hohen Ausgangsimpedanz in einem großen Ausgangsspannungsbereich weist die erfindungsgemäße Stromquellenschaltung den Vorteil auf, dass sie im Gegensatz zu anderen bekannten Schaltungen nicht zerstört wird, wenn am Ausgangstransistor eine Spannung anliegt, während die Schaltung selbst, also der Regelverstärker und weitere Schaltungselemente noch nicht mit einer Betriebsspannung versorgt werden. Schließlich hat die erfindungsgemäße Stromquellenschaltung den Vorteil, dass sie in hochintegrierten Standard-CMOS-Technologien einsetzbar ist. Durch die Vermeidung des Hot-carrier-Effekts bei hohen Ausgangsspannungen erhöht sich außerdem die Lebensdauer der Stromquellenschaltung.In addition to the high output impedance in a large output voltage range the current source circuit according to the invention has the advantage that, in contrast to other known circuits is not destroyed if one at the output transistor Voltage is present while the circuit itself, i.e. the control amplifier and others Circuit elements are not yet supplied with an operating voltage. Finally The current source circuit according to the invention has the advantage that it is highly integrated Standard CMOS technologies can be used. By avoiding the hot carrier effect at high output voltages, the lifespan of the power source circuit also increases.
Eine vorteilhafte Ausgestaltung der erfindungsgemäßen Stromquellenschaltung besteht darin, dass mit dem weiteren MOS-Feldeffekttransistor mindestens ein als Diode geschalteter MOS-Feldeffekttransistor in Reihe geschaltet ist.There is an advantageous embodiment of the current source circuit according to the invention in that with the further MOS field effect transistor at least one connected as a diode MOS field effect transistor is connected in series.
Eine andere vorteilhafte Ausgestaltung ist derart ausgebildet, dass der Ausgang des Regelverstärkers über einen Widerstand mit der Gate-Elektrode des vierten MOS-Feldeffekttransistors verbunden ist, wobei vorzugsweise vorgesehen ist, dass der Regelverstärker von einem Operational-transconductance-amplifier gebildet ist. Bei dieser Ausgestaltung wird vermieden, dass für den Fall einer Spannung am Ausgangstransistor, die höher als die Betriebsspannung ist, der von dem weiteren MOS-Feldeffekttransistor zur Gate-Elektrode geleitete Strom durch ausgangsseitig im Regelverstärker befindliche Dioden kurzgeschlossen wird. Another advantageous embodiment is designed such that the output of the control amplifier via a resistor to the gate electrode of the fourth MOS field effect transistor is connected, wherein it is preferably provided that the control amplifier is formed by an operational transconductance amplifier. With this configuration it is avoided that in the event of a voltage at the output transistor that is higher than the operating voltage is that from the further MOS field-effect transistor to the gate electrode conducted current through diodes on the output side in the control amplifier is short-circuited.
Extended-drain-MOS-Feldeffekttransistoren, die auch lightly doped drain n-well transistor oder lightly doped drift region transistor genannt werden, sind beispielsweise beschrieben in: Y.Q. Li, C.A.T. Salama, M. Seufert, M. King "Submicron BiCMOS compatible highvoltage MOS transistors", ISPSD Proc., 1994, pp. 355-359.Extended-drain MOS field-effect transistors, which are also lightly doped drain n-well transistors or lightly doped drift region transistor are described, for example in: Y.Q. Li, C.A.T. Salama, M. Seufert, M. King "Submicron BiCMOS compatible highvoltage MOS transistors ", ISPSD Proc., 1994, pp. 355-359.
Ein Ausführungsbeispiel der Erfindung ist in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Dabei sind - von näher angegebenen Ausnahmen abgesehen, die Transistoren als n-Kanal-MOS-Feldeffekttransistoren ausgebildet.An embodiment of the invention is shown in the drawing and in the following Description explained in more detail. With the exception of specified exceptions, the transistors are designed as n-channel MOS field-effect transistors.
Ein erster MOS-Feldeffekttransistor 1 und ein zweiter MOS-Feldeffekttransistor 2 stellen
den eigentlichen Stromspiegel dar, dem über einen Eingang 5 ein Referenzstrom Iin zugeführt
werden kann. Eine Stromspiegelschaltung ist an sich bekannt und braucht im Zusammenhang
mit der vorliegenden Erfindung nicht näher erläutert zu werden. Es sei jedoch
kurz erwähnt, dass der dem Ausgang 6 entnehmbare Strom Iout in einem durch
Transistorgeometrien bestimmten Verhältnis zum Referenzstrom Iin steht. Um die Wirkung
verschieden hoher Spannungen am Eingang 5 und am Ausgang 6 zu vermindern, ist
ein dritter Transistor 3 mit einer bei 14 zugeführten Vorspannung und ein vierter Transistor
dem ersten und zweiten Transistor jeweils in Kaskode zugeschaltet, wobei der MOS-Feldeffekttransistor
4 im folgenden auch Ausgangstransistor genannt wird. Außerdem werden
in einem OTA (Operational-transconductance-amplifier) 7 die beiden Source-Spannungen
der Kaskode-Transistoren 3, 4 miteinander verglichen, wodurch ein Steuersignal
entsteht, das über einen Widerstand 8 der Gate-Elektrode des Ausgangstransistors 4 zugeführt
wird. Zur Dämpfung der Schwingneigung der Regelschleife ist ein MOS-Feldeffekttransistor
9 als Kapazität zwischen den Ausgang des OTA 7 und Massepotential geschaltet.Provide a first MOS field effect transistor 1 and a second MOS field effect transistor 2
represents the actual current mirror, to which a reference current Iin is fed via an input 5
can be. A current mirror circuit is known per se and needs context
not to be explained in more detail with the present invention. However, it is
briefly mentioned that the current Iout that can be taken from the
Der Trend moderner CMOS-Technologien geht zu weiterer Verringerung der Transistorabmessungen und Verringerung der Gate-oxide-Dicke der Transistoren. Damit verbunden ist eine Reduzierung der Versorgungsspannung solcher in Deep-submicron-Technologie gefertigter Chips. In bestimmten Applikationen, wie zum Beispiel Interface mit Chips höherer Versorgungsspannung oder Ansteuerung von Leistungstreibern, ist es erforderlich, dass die Ausgangsstufe eine höhere Spannung als die eigene, für diese Technologie zulässige Versorgungsspannung annehmen kann. Für solche "High-voltage"-Applikationen stellt dabei die Lebensdauer der in der Ausgangsstufe zum Einsatz kommenden Transistoren das Hauptproblem dar.The trend of modern CMOS technologies continues to reduce the transistor dimensions and reducing the gate oxide thickness of the transistors. Associated with it is a reduction in the supply voltage of such in deep-submicron technology manufactured chips. In certain applications, such as interface with higher chips Supply voltage or control of power drivers, it is necessary that the output stage has a higher voltage than its own allowed for this technology Can assume supply voltage. For such "high-voltage" applications it poses the lifespan of the transistors used in the output stage Main problem.
Durch den Einsatz eines Extended-drain-Transistors wird bei geeigneter Dimensionierung
der n-Well-drift-region eine hohe Lebensdauer bis zur maximalen Ausgangsspannung erzielt.
Ein Gate-oxide-breakdown wird unter allen Bedingungen durch die Transistorkombination
10, 11, 12 verhindert.By using an extended drain transistor with suitable dimensions
the n-well drift region achieves a long service life up to the maximum output voltage.
A gate oxide breakdown is achieved under all conditions by the
In Schaltungssystemen mit unterschiedlichen Spannungsversorgungen kann es vorkommen,
dass die Spannungsversorgung nach dem Starten bereits den maximalen Spannungswert
erreicht hat, eine andere Spannungsversorgung aber noch nicht vorhanden ist. Für
diesen Betriebszustand ist ein sogenannter Fail-save-mode erforderlich. Bei dem dargestellten
Ausführungsbeispiel schützt die Reihenschaltung aus einem p-Kanal-MOS-Feldeffekttransistor
10 und den beiden als Dioden geschalteten n- bzw. p-Kanal-MOS-Feldeffekttransistoren
11 und 12 den Ausgangstransistor 4 für den Fall, dass eine Spannung am Ausgang
6 bereits anliegt, während die bei 13 zugeführte Betriebsspannung (noch) nicht vorhanden
ist. Der Transistor 10 erhält dabei als Gate-Potential 0V und schaltet über die
MOS-Feldeffekttransistoren 11, 12 die Gate-drain-Spannung des Ausgangstransistors 4 auf
einen Wert, der unter der Gate-oxide-Durchbruchsspannung liegt. Dabei dient der Widerstand
8 zur Entkopplung des OTA-Ausgangs. Nach dem Aufstarten der Betriebsspannung
bei 13 schaltet der MOS-Feldeffekttransistor 10 ab, so dass die Funktion der Kaskode-Regelung
nicht mehr beeinflußt wird.In circuit systems with different power supplies,
that the voltage supply already has the maximum voltage value after starting
has reached, but another power supply is not yet available. For
this operating state requires a so-called fail-save mode. In the illustrated
Embodiment protects the series circuit from a p-channel MOS
Claims (5)
dadurch gekennzeichnet, dass die Source-Elektroden des dritten (3) und des vierten (4) MOS-Feldeffekttransistors an Eingänge eines Regelverstärkers (7) angeschlossen sind, dessen Ausgang mit der Gate-Elektrode des vierten MOS-Feldeffekttransistors (4) verbunden ist, dass der vierte MOS-Feldeffekttransistor (4) ein Extended-drain-MOS-Feldeffekttransistor ist und dass die Drain-Elektrode und die Gate-Elektrode des vierten MOS-Feldeffekttransistors (4) über einen weiteren MOS-Feldeffekttransistor (10) miteinander verbunden sind, dessen Gate-Elektrode mit einer Betriebsspannung für die Schaltung beaufschlagt ist.Current source circuit in which a first and a second MOS field effect transistor form a current mirror circuit, a reference current being able to be supplied to the first MOS field effect transistor via a cascode-connected third MOS field effect transistor and the drain electrode of a cascode connected to the second MOS field effect transistor fourth MOS field effect transistor forms an output,
characterized in that the source electrodes of the third (3) and fourth (4) MOS field effect transistors are connected to inputs of a control amplifier (7), the output of which is connected to the gate electrode of the fourth MOS field effect transistor (4), that the fourth MOS field effect transistor (4) is an extended drain MOS field effect transistor and that the drain electrode and the gate electrode of the fourth MOS field effect transistor (4) are connected to one another via a further MOS field effect transistor (10), whose gate electrode is supplied with an operating voltage for the circuit.
dadurch gekennzeichnet, dass der Extended-drain-MOS-Feldeffekttransistor ein Extended-drain-n-well-MOS-Feldeffekttransistor (4) ist und dass der weitere MOS-Feldeffekttransistor ein p-Kanal-MOS-Feldeffekttransistor (10) ist.Current source circuit according to claim 1,
characterized in that the extended drain MOS field effect transistor is an extended drain n-well MOS field effect transistor (4) and that the further MOS field effect transistor is a p-channel MOS field effect transistor (10).
dadurch gekennzeichnet, dass mit dem weiteren MOS-Feldeffekttransistor (10) mindestens ein als Diode geschalteter MOS-Feldeffekttransistor (11, 12) in Reihe geschaltet ist. Current source circuit according to claim 2,
characterized in that at least one MOS field-effect transistor (11, 12) connected as a diode is connected in series with the further MOS field-effect transistor (10).
dadurch gekennzeichnet, dass der Ausgang des Regelverstärkers (7) über einen Widerstand (8) mit der Gate-Elektrode des vierten MOS-Feldeffekttransistors (4) verbunden ist.Current source circuit according to one of the preceding claims,
characterized in that the output of the control amplifier (7) is connected to the gate electrode of the fourth MOS field-effect transistor (4) via a resistor (8).
dadurch gekennzeichnet, dass der Regelverstärker von einem Operational-transconductance-amplifier (7) gebildet ist.Current source circuit according to one of the preceding claims,
characterized in that the control amplifier is formed by an operational transconductance amplifier (7).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10163633 | 2001-12-21 | ||
DE10163633A DE10163633A1 (en) | 2001-12-21 | 2001-12-21 | Current source circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1321843A1 true EP1321843A1 (en) | 2003-06-25 |
EP1321843B1 EP1321843B1 (en) | 2005-12-14 |
Family
ID=7710634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02102824A Expired - Lifetime EP1321843B1 (en) | 2001-12-21 | 2002-12-19 | Current source circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US6690229B2 (en) |
EP (1) | EP1321843B1 (en) |
JP (1) | JP4157928B2 (en) |
AT (1) | ATE313109T1 (en) |
DE (2) | DE10163633A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102455727A (en) * | 2010-10-28 | 2012-05-16 | 南京航空航天大学 | Current control circuit |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7049935B1 (en) | 1999-07-20 | 2006-05-23 | Stmicroelectronics S.A. | Sizing of an electromagnetic transponder system for a dedicated distant coupling operation |
FR2796781A1 (en) * | 1999-07-20 | 2001-01-26 | St Microelectronics Sa | DIMENSIONING OF AN ELECTROMAGNETIC TRANSPONDER SYSTEM FOR HYPERPROXIMITY OPERATION |
FR2804557B1 (en) * | 2000-01-31 | 2003-06-27 | St Microelectronics Sa | ADAPTING THE TRANSMISSION POWER OF AN ELECTROMAGNETIC TRANSPONDER DRIVE |
FR2808941B1 (en) * | 2000-05-12 | 2002-08-16 | St Microelectronics Sa | VALIDATION OF THE PRESENCE OF AN ELECTROMAGNETIC TRANSPONDER IN THE FIELD OF AN AMPLITUDE DEMODULATION READER |
FR2808946A1 (en) * | 2000-05-12 | 2001-11-16 | St Microelectronics Sa | VALIDATION OF THE PRESENCE OF AN ELECTROMAGNETIC TRANSPONDER IN THE FIELD OF A READER |
FR2808945B1 (en) * | 2000-05-12 | 2002-08-16 | St Microelectronics Sa | EVALUATION OF THE NUMBER OF ELECTROMAGNETIC TRANSPONDERS IN THE FIELD OF A READER |
FR2809235A1 (en) * | 2000-05-17 | 2001-11-23 | St Microelectronics Sa | ANTENNA FOR GENERATING AN ELECTROMAGNETIC FIELD FOR TRANSPONDER |
FR2809251B1 (en) * | 2000-05-17 | 2003-08-15 | St Microelectronics Sa | DEVICE FOR PRODUCING AN ELECTROMAGNETIC FIELD FOR A TRANSPONDER |
FR2812986B1 (en) * | 2000-08-09 | 2002-10-31 | St Microelectronics Sa | DETECTION OF AN ELECTRIC SIGNATURE OF AN ELECTROMAGNETIC TRANSPONDER |
US20030169169A1 (en) * | 2000-08-17 | 2003-09-11 | Luc Wuidart | Antenna generating an electromagnetic field for transponder |
US7071785B2 (en) * | 2003-10-22 | 2006-07-04 | Broadcom Corporation | Use of a thick oxide device as a cascode for a thin oxide transcoductance device in MOSFET technology and its application to a power amplifier design |
US7071769B1 (en) * | 2004-02-27 | 2006-07-04 | Marvell International Ltd. | Frequency boosting circuit for high swing cascode |
US7049894B1 (en) | 2004-02-27 | 2006-05-23 | Marvell International Ltd. | Ahuja compensation circuit with enhanced bandwidth |
US7425862B2 (en) * | 2004-08-10 | 2008-09-16 | Avago Technologies Ecbu Ip (Singapore) Pte Ltd | Driver circuit that employs feedback to enable operation of output transistor in triode region and saturation region |
KR100688803B1 (en) * | 2004-11-23 | 2007-03-02 | 삼성에스디아이 주식회사 | Current range control circuit, data driver and light emitting display |
JP5078502B2 (en) * | 2007-08-16 | 2012-11-21 | セイコーインスツル株式会社 | Reference voltage circuit |
JP4408935B2 (en) * | 2008-02-07 | 2010-02-03 | 日本テキサス・インスツルメンツ株式会社 | Driver circuit |
CN108683167B (en) * | 2018-07-03 | 2024-04-09 | 苏州锴威特半导体股份有限公司 | Anti-surge circuit of PD equipment |
CN112787490B (en) * | 2021-01-28 | 2024-09-06 | 深圳市矽塔科技有限公司 | Full-bridge lower tube driving circuit and driver thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4199733A (en) * | 1978-01-09 | 1980-04-22 | Rca Corporation | Extended-drain MOS mirrors |
EP0403195A1 (en) * | 1989-06-12 | 1990-12-19 | Inmos Limited | Current mirror circuit |
US5612614A (en) * | 1995-10-05 | 1997-03-18 | Motorola Inc. | Current mirror and self-starting reference current generator |
US5847556A (en) * | 1997-12-18 | 1998-12-08 | Lucent Technologies Inc. | Precision current source |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3499250B2 (en) | 1992-08-10 | 2004-02-23 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device and A / D conversion circuit |
US5680037A (en) * | 1994-10-27 | 1997-10-21 | Sgs-Thomson Microelectronics, Inc. | High accuracy current mirror |
US5694072A (en) * | 1995-08-28 | 1997-12-02 | Pericom Semiconductor Corp. | Programmable substrate bias generator with current-mirrored differential comparator and isolated bulk-node sensing transistor for bias voltage control |
KR100202635B1 (en) * | 1995-10-13 | 1999-06-15 | 구본준 | Resurf edmos transistor and high voltage analog multiplex circuit using the same |
US5844434A (en) | 1997-04-24 | 1998-12-01 | Philips Electronics North America Corporation | Start-up circuit for maximum headroom CMOS devices |
US6087820A (en) * | 1999-03-09 | 2000-07-11 | Siemens Aktiengesellschaft | Current source |
US6381491B1 (en) * | 2000-08-18 | 2002-04-30 | Cardiac Pacemakers, Inc. | Digitally trimmable resistor for bandgap voltage reference |
US6466081B1 (en) * | 2000-11-08 | 2002-10-15 | Applied Micro Circuits Corporation | Temperature stable CMOS device |
-
2001
- 2001-12-21 DE DE10163633A patent/DE10163633A1/en not_active Withdrawn
-
2002
- 2002-12-18 JP JP2002366385A patent/JP4157928B2/en not_active Expired - Fee Related
- 2002-12-18 US US10/323,352 patent/US6690229B2/en not_active Expired - Lifetime
- 2002-12-19 DE DE50205270T patent/DE50205270D1/en not_active Expired - Lifetime
- 2002-12-19 AT AT02102824T patent/ATE313109T1/en not_active IP Right Cessation
- 2002-12-19 EP EP02102824A patent/EP1321843B1/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4199733A (en) * | 1978-01-09 | 1980-04-22 | Rca Corporation | Extended-drain MOS mirrors |
EP0403195A1 (en) * | 1989-06-12 | 1990-12-19 | Inmos Limited | Current mirror circuit |
US5612614A (en) * | 1995-10-05 | 1997-03-18 | Motorola Inc. | Current mirror and self-starting reference current generator |
US5847556A (en) * | 1997-12-18 | 1998-12-08 | Lucent Technologies Inc. | Precision current source |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102455727A (en) * | 2010-10-28 | 2012-05-16 | 南京航空航天大学 | Current control circuit |
CN102455727B (en) * | 2010-10-28 | 2013-10-23 | 南京航空航天大学 | Current control circuit with rang of 100pA-1muA |
Also Published As
Publication number | Publication date |
---|---|
DE10163633A1 (en) | 2003-07-10 |
DE50205270D1 (en) | 2006-01-19 |
JP2003223232A (en) | 2003-08-08 |
ATE313109T1 (en) | 2005-12-15 |
US6690229B2 (en) | 2004-02-10 |
US20030117210A1 (en) | 2003-06-26 |
EP1321843B1 (en) | 2005-12-14 |
JP4157928B2 (en) | 2008-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1321843B1 (en) | Current source circuit | |
DE102005039114B4 (en) | Voltage regulator with a low voltage drop | |
DE10215084A1 (en) | Circuit arrangement for voltage regulation | |
DE3736380C2 (en) | amplifier | |
DE2855303A1 (en) | LINEAR AMPLIFIER | |
DE10142707A1 (en) | Multistage differential amplifier includes current source that additionally feeds current into feedback loop, to prevent current mirror from being switched OFF | |
EP0648019A2 (en) | CMOS circuit with high withstand-voltage | |
EP1004165B1 (en) | Active operating point regulation for power amplifiers | |
EP0582125A1 (en) | Control circuit for a power MOSFET having a load connected to the source | |
DE10328605A1 (en) | Current source generating constant reference current, with amplifier circuit, invertingly amplifying negative feedback voltage, applied to first resistor, as amplified output voltage | |
DE69815289T2 (en) | VOLTAGE REGULATOR CIRCUITS AND SEMICONDUCTOR CIRCUIT | |
EP0556644B1 (en) | Integrated circuit | |
WO2005104370A1 (en) | Output stage system | |
EP0523266B1 (en) | Integratable current mirror | |
EP1099308B1 (en) | Driving circuit | |
DE3017654C2 (en) | ||
EP0990199B1 (en) | Regulating device | |
DE19940382A1 (en) | Power source for low operating voltages with high output resistance | |
DE4134176C2 (en) | Semiconductor arrangement with a tetrode integrated in the semiconductor body and made up of two field effect transistors | |
DE4344447A1 (en) | Electrical constant current source | |
DE10060842A1 (en) | Current mirror circuit for producing an output current which mirrors a reference input current, generates a base current between two bipolar transistors using a further current mirror circuit | |
EP1391035B1 (en) | Circuit arrangement comprising cascaded field effect transistors | |
DE10102443A1 (en) | Current source circuit | |
EP0719474B1 (en) | BiCMOS OPERATIONAL AMPLIFIER FOR SWITCH-CAPACITOR CIRCUITS | |
EP1926012A1 (en) | Current mirror connection |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL LT LV MK RO |
|
17P | Request for examination filed |
Effective date: 20031229 |
|
AKX | Designation fees paid |
Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED. Effective date: 20051214 Ref country code: IE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051214 Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051214 Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051214 Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051214 Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051214 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051214 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051214 Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051214 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20051219 Ref country code: AT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20051219 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20051231 Ref country code: MC Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20051231 |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: LANGUAGE OF EP DOCUMENT: GERMAN |
|
REF | Corresponds to: |
Ref document number: 50205270 Country of ref document: DE Date of ref document: 20060119 Kind code of ref document: P |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20060214 |
|
GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20060213 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20060314 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20060314 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20060314 Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20060314 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20060325 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20060515 |
|
NLV1 | Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act | ||
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FD4D |
|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20060915 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20061231 Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20061231 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: TP |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
BERE | Be: lapsed |
Owner name: PHILIPS INTELLECTUAL PROPERTY & STANDARDS G.M.B.H. Effective date: 20051231 Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V. Effective date: 20051231 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20091221 Year of fee payment: 8 Ref country code: GB Payment date: 20091216 Year of fee payment: 8 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20091217 Year of fee payment: 8 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20101219 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20110831 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20110103 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 50205270 Country of ref document: DE Effective date: 20110701 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20110701 Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20101219 |